Re: [RFC PATCH 4/7] iommu/riscv: Program QoS IDs for assigned groups

[Drew Fustini <fustini@kernel.org>]

On Tue, Jul 14, 2026 at 09:06:54PM +0800, Zhanpeng Zhang wrote:
> Program RCID and MCID for RISC-V IOMMU groups through the device context
> TA fields. The resctrl group assignment is per device group, so reject
> BARE mode where only the per-IOMMU iommu_qosid global default is
> available.
> 
> Validate every group member, firmware ID, device context, field value,
> and QoS ID capability before changing hardware. Then update all members
> through the checked IOMMU group helper so a validation failure leaves the
> group unchanged.
> 
> Serialize DC.ta changes with context setup under qosid_lock. Change only
> the RCID and MCID fields with ordinary accesses so fixed DDT mappings are
> not subject to atomic LR/SC operations, invalidate active device contexts
> after an update, and clear the IDs when a device is released.
> 
> Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
> ---
>  arch/riscv/include/asm/qos.h     |  16 +++
>  drivers/iommu/riscv/iommu-bits.h |  15 +++
>  drivers/iommu/riscv/iommu.c      | 200 ++++++++++++++++++++++++++++++-
>  drivers/iommu/riscv/iommu.h      |   3 +
>  4 files changed, 232 insertions(+), 2 deletions(-)
[..]
> diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h
> index f2ef9bd3cde9..782de5c92727 100644
> --- a/drivers/iommu/riscv/iommu-bits.h
> +++ b/drivers/iommu/riscv/iommu-bits.h
> @@ -63,6 +63,7 @@
>  #define RISCV_IOMMU_CAPABILITIES_PD8		BIT_ULL(38)
>  #define RISCV_IOMMU_CAPABILITIES_PD17		BIT_ULL(39)
>  #define RISCV_IOMMU_CAPABILITIES_PD20		BIT_ULL(40)
> +#define RISCV_IOMMU_CAPABILITIES_QOSID		BIT_ULL(41)
>  #define RISCV_IOMMU_CAPABILITIES_NL		BIT_ULL(42)
>  #define RISCV_IOMMU_CAPABILITIES_S		BIT_ULL(43)
>  
> @@ -274,6 +275,14 @@ enum riscv_iommu_hpmevent_id {
>  #define RISCV_IOMMU_TR_RESPONSE_SZ	BIT_ULL(9)
>  #define RISCV_IOMMU_TR_RESPONSE_PPN	RISCV_IOMMU_PPN_FIELD
>  
> +/* 6.27 IOMMU QoS IDs for IOMMU-initiated requests (32bits) */
> +#define RISCV_IOMMU_REG_IOMMU_QOSID	0x0270
> +#define RISCV_IOMMU_IOMMU_QOSID_RCID	GENMASK(11, 0)
> +#define RISCV_IOMMU_IOMMU_QOSID_MCID	GENMASK(27, 16)
> +
> +#define RISCV_IOMMU_IOMMU_QOSID_RCID_SHIFT	0
> +#define RISCV_IOMMU_IOMMU_QOSID_MCID_SHIFT	16

Sorry for not making all my comments in one pass but I think these two
shifts are left over from before you were using GENMASK?

Drew