From: Leonardo Bras <leo.bras@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Leonardo Bras <leo.bras@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Shuah Khan <shuah@kernel.org>, Fuad Tabba <tabba@google.com>,
Oliver Upton <oupton@kernel.org>,
Peter Maydell <peter.maydell@linaro.org>,
Yao Yuan <yaoyuan@linux.alibaba.com>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v19 03/14] KVM: arm64: Manage GCS access and registers for guests
Date: Thu, 20 Aug 2026 15:28:39 +0100 [thread overview]
Message-ID: <aocOi3wjcliZqoe7@LeoBrasDK> (raw)
In-Reply-To: <97ad6e83-b22b-4881-b644-66fa99f68d64@sirena.org.uk>
On Thu, Aug 20, 2026 at 03:07:14PM +0100, Mark Brown wrote:
> On Thu, Aug 20, 2026 at 11:16:59AM +0100, Leonardo Bras wrote:
> > On Wed, Aug 19, 2026 at 05:46:00PM +0100, Mark Brown wrote:
>
> > > This is just because there isn't a preexisting ctxt_has_tcrx() check
> > > already there, FEAT_GCS architecturally depends on FEAT_TCRX and there
> > > was a request to make this explicit in the code to try to optimise
> > > things a bit. The compiler should skip over both blocks at once if TCRX
> > > isn't there rather than having two separate tests or static branches. I
> > > didn't add new checks where there were none since I expect that to be
> > > unhelpful for code generation, you'd get the reverse situation and emit
> > > two checks.
>
> > Humm, but then why saving GCSPR_EL2 does not depend on TCRX/E2H? Or maybe a
> > better question, why are not GCSPR_EL2 and GCSCR_EL2 saved in the same 'if'
> > clause under ctxt_has_tcrx() (and E2H set), if they are restored in the
> > same 'if' clause?
>
> > As you mentioned, GCS depends on TCRX, so it should be fine, but just by
> > reading the code I see:
> > - GCSCR_EL2 :
> > Save if GCS=1, TCRX=1, E2H=1
> > Restore if GCS=1, TCRX=1
> > - GCSPR_EL2 :
> > Save if GCS=1,
> > Restore if GCS=1, TCRX=1
>
> > Which looks kind of confusing for the as a first time reader.
>
> > Does it make sense?
>
> I agree that the current situation is a bit hard to follow, I'd actually
> originally written things without the explict dependency because of that
> but Marc wanted the optimisation.
Well, I am not against the explicit dependency thing, it just looks odd
to me that some save/restore have a dependency and it's counterpart does
not. As well as the dependencies for both registers being different.
> There's similar things with other
> registers in the current code (eg, the PIE and POE registers are in the
> same situaton as GCSCR_EL2). One thing I did miss here is some nesting
> inside the PIE checks for EL2, I'll update for that.
>
Awesome!
> I think what would help here would be to move to generating more of the
> save/restore sequences rather than open coding them, we could have lists
> of registers and then use data about the feature dependencies that the
> architecture has (hopefully it's already in the MRS, I didn't check) to
> generate these optimised feature checks rather than having to open code
> them. Possibly even list features and generate some of the register
> lists, though that would need far more special case handling and it's
> *much* less clear if there could be a benefit.
Yeah, that would automatize the feature dependency for register loading,
but maybe code would not be that clear on how it works? I have questionable
taste, though.
Thanks!
Leo
next prev parent reply other threads:[~2026-08-20 14:28 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 19:11 [PATCH v19 00/14] KVM: arm64: Provide guest support for GCS Mark Brown
2026-08-12 19:12 ` [PATCH v19 01/14] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Mark Brown
2026-08-19 13:41 ` Leonardo Bras
2026-08-19 14:21 ` Mark Brown
2026-08-19 16:41 ` Leonardo Bras
2026-08-12 19:12 ` [PATCH v19 02/14] KVM: arm64: Fix FGT mapping for HFGITR_EL2.nGCSEPP Mark Brown
2026-08-19 13:55 ` Leonardo Bras
2026-08-19 16:42 ` Leonardo Bras
2026-08-12 19:12 ` [PATCH v19 03/14] KVM: arm64: Manage GCS access and registers for guests Mark Brown
2026-08-19 16:32 ` Leonardo Bras
2026-08-19 16:46 ` Mark Brown
2026-08-20 10:16 ` Leonardo Bras
2026-08-20 14:07 ` Mark Brown
2026-08-20 14:28 ` Leonardo Bras [this message]
2026-08-20 15:19 ` Mark Brown
2026-08-12 19:12 ` [PATCH v19 04/14] KVM: arm64: Ensure GCS memory effects are visible Mark Brown
2026-08-19 17:23 ` Leonardo Bras
2026-08-19 18:08 ` Mark Brown
2026-08-20 11:32 ` Marc Zyngier
2026-08-12 19:12 ` [PATCH v19 05/14] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Mark Brown
2026-08-20 17:04 ` Leonardo Bras
2026-08-12 19:12 ` [PATCH v19 06/14] KVM: arm64: Validate GCS exception lock when emulating ERET Mark Brown
2026-08-12 19:12 ` [PATCH v19 07/14] KVM: arm64: Forward GCS exceptions to nested guests Mark Brown
2026-08-12 19:12 ` [PATCH v19 08/14] KVM: arm64: Enforce EXLOCK for SPSR and ELR Mark Brown
2026-08-12 19:12 ` [PATCH v19 09/14] KVM: arm64: Allow GCS to be enabled for guests Mark Brown
2026-08-12 19:12 ` [PATCH v19 10/14] KVM: selftests: arm64: Add GCS registers to get-reg-list Mark Brown
2026-08-12 19:12 ` [PATCH v19 11/14] KVM: selftests: arm64: Add GCS to set_id_regs Mark Brown
2026-08-12 19:12 ` [PATCH v19 12/14] KVM: selftests: arm64: Only restore SPSR_EL1 and ELR_EL1 if they change Mark Brown
2026-08-12 19:12 ` [PATCH v19 13/14] tools: Synchronise the kernel esr.h Mark Brown
2026-08-12 19:12 ` [PATCH v19 14/14] KVM: selftests: arm64: Add GCS EXLOCK exception emulation test Mark Brown
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