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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48588135600sm25224381f8f.2.2026.09.07.07.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 07:44:25 -0700 (PDT) Date: Mon, 7 Sep 2026 14:44:22 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: Catalin Marinas , Jonathan Corbet , iommu@lists.linux.dev, "Joerg Roedel (AMD)" , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, Mark Rutland , Randy Dunlap , Robin Murphy , Shuah Khan , Will Deacon , David Matlack , Jean-Philippe Brucker , Jonathan Cameron , Nicolin Chen , Pasha Tatashin , patches@lists.linux.dev, Pranjal Shrivastava , Samiullah Khawaja , stable@vger.kernel.org, Vijayanand Jitta Subject: Re: [PATCH v5 9/9] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Message-ID: References: <0-v5-b810cf379bfc+13d738-smmu_tlbi_jgg@nvidia.com> <9-v5-b810cf379bfc+13d738-smmu_tlbi_jgg@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9-v5-b810cf379bfc+13d738-smmu_tlbi_jgg@nvidia.com> On Tue, Sep 01, 2026 at 02:49:58PM -0300, Jason Gunthorpe wrote: > If DS is supported then SCALE can go up to 39. Compute a scale max that is > compatible for the entire invs list. I see in some places scale is still assumed to 32 as in: - arm_smmu_ril_init_end - arm_smmu_tlbi_calc_range Would those need to be updated also? Thanks, Mostafa > > Reviewed-by: Nicolin Chen > Tested-by: Nicolin Chen > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++++++--- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ > 2 files changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index b99229a5bbacca..2a159be751891e 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1060,9 +1060,16 @@ static void arm_smmu_invs_update_caps(struct arm_smmu_invs *invs, > invs->has_ats = true; > > if (inv->smmu->features & ARM_SMMU_FEAT_RANGE_INV) { > + unsigned int scale_max; > + > invs->has_range_inv = true; > if (inv->smmu->options & ARM_SMMU_OPT_FULL_CONT_RIL) > invs->has_full_cont_ril = true; > + > + scale_max = (inv->smmu->features & ARM_SMMU_FEAT_DS) ? 39 : 31; > + if (!invs->range_inv_scale_max || > + scale_max < invs->range_inv_scale_max) > + invs->range_inv_scale_max = scale_max; > } > } > > @@ -2625,7 +2632,8 @@ static unsigned int arm_smmu_compute_ttl(u8 leaf_bitmap, u8 table_bitmap, > * covered by one command. > */ > static void arm_smmu_tlbi_calc_range(struct arm_smmu_tlbi *tlbi, > - bool single_ril) > + bool single_ril, > + unsigned int scale_max) > { > u8 tgsz_lg2 = tlbi->tgsz_lg2; > unsigned int ttl = arm_smmu_compute_ttl( > @@ -2647,7 +2655,7 @@ static void arm_smmu_tlbi_calc_range(struct arm_smmu_tlbi *tlbi, > * address beyond alignment to tg (so long as TTL=0). > */ > first.scale = fls64((num_tg - 1) / 32); > - if (first.scale > 31) { > + if (first.scale > scale_max) { > /* Range too large for a single command do full invalidation */ > tlbi->range.use_full_inv = true; > return; > @@ -2917,7 +2925,8 @@ void arm_smmu_domain_tlbi(struct arm_smmu_tlbi *tlbi, > arm_smmu_tlbi_calc_range( > tlbi, > smmu_domain->stage == ARM_SMMU_DOMAIN_SVA && > - invs->has_full_cont_ril); > + invs->has_full_cont_ril, > + invs->range_inv_scale_max); > } > } > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 6582203eb7425f..8b251a188810c9 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -760,6 +760,7 @@ static inline bool arm_smmu_inv_is_ats(const struct arm_smmu_inv *inv) > * @has_ats: flag if the array contains an INV_TYPE_ATS or INV_TYPE_ATS_FULL > * @has_range_inv: flag if any entry's SMMU supports range invalidation > * @has_full_cont_ril: flag if any entry's SMMU requires the CONT RIL workaround > + * @range_inv_scale_max: max SCALE usable by all range-capable SMMUs > * @rcu: rcu head for kfree_rcu() > * @inv: flexible invalidation array > * > @@ -791,6 +792,7 @@ struct arm_smmu_invs { > bool has_ats; > bool has_range_inv; > bool has_full_cont_ril; > + u8 range_inv_scale_max; > struct rcu_head rcu; > struct arm_smmu_inv inv[] __counted_by(max_invs); > }; > -- > 2.43.0 >