From: Richard Cheng <icheng@nvidia.com>
To: mhonap@nvidia.com
Cc: alex@shazbot.org, jgg@ziepe.ca, ankita@nvidia.com,
jic23@kernel.org, dave.jiang@intel.com,
alejandro.lucero-palau@amd.com, smadhavan@nvidia.com,
corbet@lwn.net, skhan@linuxfoundation.org, dave@stgolabs.net,
alison.schofield@intel.com, vishal.l.verma@intel.com,
iweiny@kernel.org, ming.li@zohomail.com, yishaih@nvidia.com,
skolothumtho@nvidia.com, kevin.tian@intel.com,
bhelgaas@google.com, dmatlack@google.com, kees@kernel.org,
gustavoars@kernel.org, cjia@nvidia.com, kjaju@nvidia.com,
vsethi@nvidia.com, zhiw@nvidia.com, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kselftest@vger.kernel.org,
linux-hardening@vger.kernel.org
Subject: Re: [PATCH v5 06/27] vfio/pci: Detect CXL devices and load the CXL provider on demand
Date: Thu, 17 Sep 2026 16:48:08 +0800 [thread overview]
Message-ID: <aqun1vZcE3gQzXD9@MWDK4CY14F> (raw)
In-Reply-To: <20260916183540.3813685-7-mhonap@nvidia.com>
On Thu, Sep 17, 2026 at 12:05:19AM +0800, mhonap@nvidia.com wrote:
> From: Manish Honap <mhonap@nvidia.com>
>
> A CXL device needs the vfio-cxl callbacks, but pulling vfio-cxl and the
> CXL core in unconditionally would bloat every vfio-pci setup. Detect a
> CXL Type-2 device at bind and request_module("vfio-cxl") only then, then
> hand the device to the registered ops.
>
> Each bound CXL device pins the provider through
> vfio_pci_get_cxl_ops() (try_module_get) and drops it with
> vfio_pci_put_cxl_ops() at release, so vfio-cxl can unload once no CXL
> device is bound.
>
> If the provider is absent the device is driven as plain vfio-pci. A
> built-in provider whose initcall has not run yet is waited for with
> -EPROBE_DEFER; the deferred-probe machinery will retry the bind once the
> provider registers.
>
> Assisted-by: LLM
> Signed-off-by: Manish Honap <mhonap@nvidia.com>
> ---
> drivers/vfio/pci/vfio_pci_core.c | 84 ++++++++++++++++++++++++++++++++
> include/linux/vfio_pci_core.h | 3 ++
> 2 files changed, 87 insertions(+)
>
> diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c
> index 2cc5dd20396c..9eede1e56ab5 100644
> --- a/drivers/vfio/pci/vfio_pci_core.c
> +++ b/drivers/vfio/pci/vfio_pci_core.c
> @@ -2202,6 +2202,84 @@ void vfio_pci_core_unregister_cxl_ops(const struct vfio_cxl_ops *ops)
> }
> EXPORT_SYMBOL_GPL(vfio_pci_core_unregister_cxl_ops);
>
> +static const struct vfio_cxl_ops *vfio_pci_get_cxl_ops(void)
> +{
> + guard(rwsem_read)(&vfio_pci_cxl_ops_rwsem);
> +
> + if (vfio_pci_cxl_ops && try_module_get(vfio_pci_cxl_ops->owner))
> + return vfio_pci_cxl_ops;
> +
> + return NULL;
> +}
> +
> +static void vfio_pci_put_cxl_ops(const struct vfio_cxl_ops *ops)
> +{
> + module_put(ops->owner);
> +}
> +
Anything guarantees that we can finish devres cleanup before dropping module ref ?
This function drops the module ref during vfio_pci_remove(), while devres might still pending.
I see in patch 18 it register vfio_cxl_release_hpa() as a devres callback, and it lives in vfio-cxl.
If this drops the last module ref, another process could unload vfio-cxl before devres invokes that callback.
Best regards,
Richard Cheng.
> +/*
> + * A CXL Type-2 device advertises both CXL.cache and CXL.mem in its CXL DVSEC.
> + * pcie_is_cxl() is also true for Type-1 (cache only) and Type-3 (mem only)
> + * devices, which the vfio-cxl provider does not handle, so confirm the Type-2
> + * identity before engaging it.
> + */
> +static bool vfio_pci_is_cxl_type2(struct pci_dev *pdev)
> +{
> + u16 dvsec, cap;
> +
> + if (!pcie_is_cxl(pdev))
> + return false;
> +
> + dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
> + PCI_DVSEC_CXL_DEVICE);
> + if (!dvsec)
> + return false;
> +
> + if (pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CAP, &cap))
> + return false;
> +
> + return (cap & PCI_DVSEC_CXL_CACHE_CAPABLE) &&
> + (cap & PCI_DVSEC_CXL_MEM_CAPABLE);
> +}
> +
> +/*
> + * Load vfio-cxl on demand for a CXL Type-2 device and hand the device to its
> + * ops. If the provider is absent the device is driven as plain vfio-pci; a
> + * built-in provider whose initcall has not run yet is waited for with
> + * -EPROBE_DEFER.
> + */
> +static int vfio_pci_core_cxl_init(struct vfio_pci_core_device *vdev)
> +{
> + const struct vfio_cxl_ops *ops;
> + int ret;
> +
> + if (!vfio_pci_is_cxl_type2(vdev->pdev))
> + return 0;
> +
> + request_module("vfio-cxl");
> + ops = vfio_pci_get_cxl_ops();
> + if (!ops)
> + return IS_BUILTIN(CONFIG_VFIO_CXL) ? -EPROBE_DEFER : 0;
> +
> + ret = ops->init(vdev);
> + if (ret) {
> + vfio_pci_put_cxl_ops(ops);
> + return ret;
> + }
> +
> + vdev->cxl_ops = ops;
> + return 0;
> +}
> +
> +static void vfio_pci_core_cxl_release(struct vfio_pci_core_device *vdev)
> +{
> + if (!vdev->cxl_ops)
> + return;
> +
> + vdev->cxl_ops->release(vdev);
> + vfio_pci_put_cxl_ops(vdev->cxl_ops);
> +}
> +
> int vfio_pci_core_init_dev(struct vfio_device *core_vdev)
> {
> struct vfio_pci_core_device *vdev =
> @@ -2223,6 +2301,10 @@ int vfio_pci_core_init_dev(struct vfio_device *core_vdev)
> init_rwsem(&vdev->memory_lock);
> xa_init(&vdev->ctx);
>
> + ret = vfio_pci_core_cxl_init(vdev);
> + if (ret)
> + return ret;
> +
> return 0;
> }
> EXPORT_SYMBOL_GPL(vfio_pci_core_init_dev);
> @@ -2232,6 +2314,8 @@ void vfio_pci_core_release_dev(struct vfio_device *core_vdev)
> struct vfio_pci_core_device *vdev =
> container_of(core_vdev, struct vfio_pci_core_device, vdev);
>
> + vfio_pci_core_cxl_release(vdev);
> +
> mutex_destroy(&vdev->igate);
> mutex_destroy(&vdev->ioeventfds_lock);
> kfree(vdev->region);
> diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h
> index 9fe0d1a3a370..7f3a2bcb5830 100644
> --- a/include/linux/vfio_pci_core.h
> +++ b/include/linux/vfio_pci_core.h
> @@ -29,6 +29,7 @@ struct vfio_pci_core_device;
> struct vfio_pci_region;
> struct p2pdma_provider;
> struct dma_buf_attachment;
> +struct vfio_cxl_state;
>
> struct vfio_pci_eventfd {
> struct eventfd_ctx *ctx;
> @@ -109,6 +110,8 @@ struct vfio_pci_core_device {
> struct vfio_device vdev;
> struct pci_dev *pdev;
> const struct vfio_pci_device_ops *pci_ops;
> + const struct vfio_cxl_ops *cxl_ops;
> + struct vfio_cxl_state *cxl;
> void __iomem *barmap[PCI_STD_NUM_BARS];
> bool bar_mmap_supported[PCI_STD_NUM_BARS];
> /* Flags modified at runtime - dedicated storage unit */
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2026-09-17 8:48 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 18:35 [PATCH v5 00/27] vfio/pci: Add CXL Type-2 device passthrough support mhonap
2026-09-16 18:35 ` [PATCH v5 01/27] cxl/regs: Split the BAR block request and ioremap helpers mhonap
2026-09-22 1:28 ` Jonathan Cameron
2026-09-16 18:35 ` [PATCH v5 02/27] cxl/regs: Let a BAR-owning driver own the component register block mhonap
2026-09-22 1:36 ` Jonathan Cameron
2026-10-09 6:13 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 03/27] cxl: Move component register defines to uapi/cxl/cxl_regs.h mhonap
2026-09-22 1:43 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 04/27] cxl: Add cxl_reset_dvsec_sequence() for vfio-pci mhonap
2026-09-25 20:41 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 05/27] vfio/pci: Add the CXL provider ops registration interface mhonap
2026-09-16 18:35 ` [PATCH v5 06/27] vfio/pci: Detect CXL devices and load the CXL provider on demand mhonap
2026-09-17 8:48 ` Richard Cheng [this message]
2026-09-21 10:05 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 07/27] vfio/pci: Honor -EPROBE_DEFER from CXL provider probe mhonap
2026-09-16 18:35 ` [PATCH v5 08/27] vfio/pci: Fall back to plain vfio-pci when CXL init fails mhonap
2026-09-22 2:15 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 09/27] vfio/pci: Add a generic excluded-range list mhonap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-25 22:05 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 10/27] vfio/pci: Migrate MSI-X exclusion onto the " mhonap
2026-09-16 18:35 ` [PATCH v5 11/27] vfio/pci: Virtualize the CXL DVSEC in vfio_pci_config.c mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-25 22:15 ` Jonathan Cameron
2026-10-09 6:15 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 12/27] vfio/pci: Call the CXL open and close hooks around device use mhonap
2026-09-25 22:17 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 13/27] vfio/pci: Bracket PCI resets with the CXL reset hooks mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 14/27] vfio/pci: Provide an opt-out for the CXL Type-2 extensions mhonap
2026-09-16 18:35 ` [PATCH v5 15/27] vfio/cxl: Add the vfio-cxl provider module skeleton mhonap
2026-09-16 18:35 ` [PATCH v5 16/27] vfio/cxl: Create the CXL memdev and set media ready at bind mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-25 22:22 ` Jonathan Cameron
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 17/27] vfio/cxl: Own the whole component register BAR mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 18/27] vfio/cxl: Expose the HDM memory region to the guest mhonap
2026-09-22 2:14 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 19/27] vfio/cxl: Contain HDM memory errors with memory_failure() mhonap
2026-09-16 18:35 ` [PATCH v5 20/27] vfio/cxl: Expose the HDM decoder registers read-only to the guest mhonap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 21/27] vfio/cxl: Exclude the HDM decoder registers from direct BAR access mhonap
2026-09-17 7:28 ` Richard Cheng
2026-09-21 9:52 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 22/27] vfio/cxl: Clear the HDM access gate after a hot reset mhonap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 23/27] vfio/cxl: Describe the CXL device and decoder geometry to userspace mhonap
2026-09-16 18:35 ` [PATCH v5 24/27] vfio/cxl: Export the HDM memory region as a dma-buf mhonap
2026-09-17 7:55 ` Richard Cheng
2026-09-21 9:58 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 25/27] vfio/cxl: Run the CXL reset at the vfio reset points mhonap
2026-09-17 8:11 ` Richard Cheng
2026-09-21 10:01 ` Manish Honap
2026-09-22 2:13 ` Alex Williamson
2026-10-09 6:14 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 26/27] Documentation: vfio-pci: Document CXL Type-2 device passthrough mhonap
2026-09-16 19:33 ` Gregory Price
2026-09-21 9:43 ` Manish Honap
2026-09-24 0:54 ` Jonathan Cameron
2026-10-09 6:15 ` Manish Honap
2026-09-16 18:35 ` [PATCH v5 27/27] selftests/vfio: Add CXL Type-2 passthrough tests mhonap
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