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[34.142.211.105]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a4986a1910sm767152a91.14.2026.09.28.11.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 11:44:41 -0700 (PDT) Date: Mon, 28 Sep 2026 18:44:34 +0000 From: Pranjal Shrivastava To: Jason Gunthorpe Cc: Catalin Marinas , Jonathan Corbet , iommu@lists.linux.dev, "Joerg Roedel (AMD)" , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, Mark Rutland , Randy Dunlap , Robin Murphy , Shuah Khan , Will Deacon , David Matlack , Jean-Philippe Brucker , Jonathan Cameron , Nicolin Chen , Pasha Tatashin , patches@lists.linux.dev, Samiullah Khawaja , Mostafa Saleh , stable@vger.kernel.org, Vijayanand Jitta Subject: Re: [PATCH v7 9/9] iommu/arm-smmu-v3: Support the DS expansion of range invalidation SCALE Message-ID: References: <0-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> <9-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> On Mon, Sep 21, 2026 at 08:55:17PM -0300, Jason Gunthorpe wrote: > If DS is supported then SCALE can go up to 39. Compute a scale max that is > compatible for the entire invs list. > > Replace the has_range_inv in the invs list with a 0 range_inv_scale_max > to mean range invalidation is unavailable. > > Reviewed-by: Nicolin Chen > Tested-by: Nicolin Chen > Signed-off-by: Jason Gunthorpe > --- [...] > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1060,9 +1060,15 @@ static void arm_smmu_invs_update_caps(struct arm_smmu_invs *invs, > invs->has_ats = true; > > if (inv->smmu->features & ARM_SMMU_FEAT_RANGE_INV) { > - invs->has_range_inv = true; > + unsigned int scale_max; > + > if (inv->smmu->options & ARM_SMMU_OPT_FULL_CONT_RANGE_INV) > invs->has_full_cont_range_inv = true; > + > + scale_max = (inv->smmu->features & ARM_SMMU_FEAT_DS) ? 39 : 31; > + if (!invs->range_inv_scale_max || > + scale_max < invs->range_inv_scale_max) > + invs->range_inv_scale_max = scale_max; Nit: maybe a short comment here, e.g. "SCALE is 6 bits when SMMU_IDR5.DS == 1, values above 39 are treated as 39 (H.a 4.4.1.1)"? Reviewed-by: Pranjal Shrivastava Thanks, Praan