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Fri, 4 Jul 2025 18:14:36 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 27/29] iommu/tegra241-cmdqv: Do not statically map LVCMDQs Date: Fri, 4 Jul 2025 18:13:43 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AD:EE_|CH3PR12MB8710:EE_ X-MS-Office365-Filtering-Correlation-Id: 34927e83-3aa0-418b-a7b6-08ddbb615604 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?mx57ljjCRz98tcUckr3ESiGVb/0QxgWXrMS7nBkFkhTP/F1QDyMaJIYEe9gA?= =?us-ascii?Q?/+hFxz4Bj0VVHODRQKUMcyJFcwGiXW0POqoBQHkiAfS0TK+USdIkXh2a0R4V?= =?us-ascii?Q?1wChxwHeTo2uHcv1QRDqT0V8cD20Dn8MzqF6hX6BTu7dYbehubvBFP/auUiD?= =?us-ascii?Q?Et287x0h00rHDZJCoYvMV4lljKCmw/wkhyNb2JCzQnt/Jjn1/h6pZzl/NHhV?= =?us-ascii?Q?K1PEZq4xEFXCmoU9S9aWG4UvyP6hSal3ZeYfzLpXVoS4ADv91M7EncPGXJqk?= =?us-ascii?Q?PdqX9vlsZ0YDE9zh/6pBA1/J27MzMcPnhhljyNuCQKXTf/qarRJalKPnAsUk?= =?us-ascii?Q?crIvnFTWsWmo/tFESQg7oG4rthbiPk0VMQvhBlmoIHX6O4TNMea1tTQc9Uy7?= =?us-ascii?Q?HiazwSkcClILrfMAQitetsnjZRuUvaAMelKcy0ACPCBc/ku1iSTKWysI2UYu?= =?us-ascii?Q?ukWO7gOraXumJXqcUHSK6opaQ6cKqCUVZFg0GnrG4qL1zqhOgz7sFybNpfQR?= =?us-ascii?Q?JIZO9DLO2eYKlPU9rPLjTfDfpiFH1c2PzM/ZZdJ69T02+gqPjK57rfGlHV1N?= =?us-ascii?Q?jO2fAgAGC+ChJfLDZEYenMF2MovnpMwq9pQtLQ+r+v5yTFvUdJsQ4XOeTEq9?= =?us-ascii?Q?sFN6h3bRA2mmABYfbcHCMAsqCTa7MvNgFOnQj4Rf4GW1EflNa+FM/IAgNs0Z?= =?us-ascii?Q?593e3aa82BvUnIuguIVlJT/Fu1SbhLFEpEvF3h+n1M9PMbBVbr7ih9sjMfZO?= =?us-ascii?Q?UtnPJgWadoUlz8WsArGsLtMYw/Kc2UISrn7y2xANgaiBNMejLKJrSBkTwp4A?= =?us-ascii?Q?9FoCTq6vk929nY4TH7RgTooZ/VTOcTYZ2fdNdrGeqJgNN1GUGa5vD/GZqGSW?= =?us-ascii?Q?U1royvLJ2Po0r+hcYKs1/IT98mOpuR1kO0yNZ+YEDxAkwSIggMmyv6QoqmgQ?= =?us-ascii?Q?vl4TpKbze7zQpfMg1hKAnCXsNyWWs36cZx9zncmqSMttr7sGqGHLzOP0X+xi?= =?us-ascii?Q?2Y1nEHPziTejZjn8/mkiP+ZwDrM58pohPn5LQAPSPHNNlpS0sIDwL1RTf2xr?= =?us-ascii?Q?qfQSyVJRO4OdI7+iGEna59XSuMwMmyNrUFDNeD3vZYMQ3UlmUDxwiJ/DSoMr?= =?us-ascii?Q?4PpnFT+a1MjDvAOeNdUs7K/nNj5UF47ZVFc4ntSjTPuEELWZTX9G0HCxB23a?= =?us-ascii?Q?NUI49idLB0iZSfoxC5Blv7RfGc47lGXAKZVmFPqy2J58FpPwHaGfILsQ4PGg?= =?us-ascii?Q?Irm1HCyMgLFvtDueULRdREnYLd7zMrn85/PdDLaPZ26UeK1zH1H344xghcS/?= =?us-ascii?Q?ML/4IBLbt/SF7y+PFdsXBhsEuVb8yg0EAqgVNl5gEavjeWP+35QXbA9dUwpu?= =?us-ascii?Q?f8C2gn7Q6ekpDiff1ODYEwMXopfTZCF5jFxSnnxzC1EBZUYs46z1KGw9GGNB?= =?us-ascii?Q?6GUoTZQBiVuXJq0VM088suQmnyxpbBaqa7nnFIQ09YKDoftHwMxVFDpV88Dh?= =?us-ascii?Q?2reyczQo5TxQh4mhjdIePmIp8tIDCAflyVrf?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2025 01:14:48.4769 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34927e83-3aa0-418b-a7b6-08ddbb615604 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8710 To simplify the mappings from global VCMDQs to VINTFs' LVCMDQs, the design chose to do static allocations and mappings in the global reset function. However, with the user-owned VINTF support, it exposes a security concern: if user space VM only wants one LVCMDQ for a VINTF, statically mapping two or more LVCMDQs creates a hidden VCMDQ that user space could DoS attack by writing random stuff to overwhelm the kernel with unhandleable IRQs. Thus, to support the user-owned VINTF feature, a LVCMDQ mapping has to be done dynamically. HW allows pre-assigning global VCMDQs in the CMDQ_ALLOC registers, without finalizing the mappings by keeping CMDQV_CMDQ_ALLOCATED=0. So, add a pair of map/unmap helper that simply sets/clears that bit. For kernel-owned VINTF0, move LVCMDQ mappings to tegra241_vintf_hw_init(), and the unmappings to tegra241_vintf_hw_deinit(). For user-owned VINTFs that will be added, the mappings/unmappings will be on demand upon an LVCMDQ allocation from the user space. However, the dynamic LVCMDQ mapping/unmapping can complicate the timing of calling tegra241_vcmdq_hw_init/deinit(), which write LVCMDQ address space, i.e. requiring LVCMDQ to be mapped. Highlight that with a note to the top of either of them. Acked-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 37 +++++++++++++++++-- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 8d418c131b1b..869c90b660c1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -351,6 +351,7 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, /* HW Reset Functions */ +/* This function is for LVCMDQ, so @vcmdq must not be unmapped yet */ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -379,6 +380,7 @@ static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) dev_dbg(vcmdq->cmdqv->dev, "%sdeinited\n", h); } +/* This function is for LVCMDQ, so @vcmdq must be mapped prior */ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) { char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); @@ -404,16 +406,42 @@ static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) return 0; } +/* Unmap a global VCMDQ from the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_unmap_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval & ~CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%sunmapped\n", h); +} + static void tegra241_vintf_hw_deinit(struct tegra241_vintf *vintf) { - u16 lidx; + u16 lidx = vintf->cmdqv->num_lvcmdqs_per_vintf; - for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) - if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) + /* HW requires to unmap LVCMDQs in descending order */ + while (lidx--) { + if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]); + tegra241_vcmdq_unmap_lvcmdq(vintf->lvcmdqs[lidx]); + } + } vintf_write_config(vintf, 0); } +/* Map a global VCMDQ to the pre-assigned LVCMDQ */ +static void tegra241_vcmdq_map_lvcmdq(struct tegra241_vcmdq *vcmdq) +{ + u32 regval = readl(REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + char header[64], *h = lvcmdq_error_header(vcmdq, header, 64); + + writel(regval | CMDQV_CMDQ_ALLOCATED, + REG_CMDQV(vcmdq->cmdqv, CMDQ_ALLOC(vcmdq->idx))); + dev_dbg(vcmdq->cmdqv->dev, "%smapped\n", h); +} + static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) { u32 regval; @@ -441,8 +469,10 @@ static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) */ vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG))); + /* HW requires to map LVCMDQs in ascending order */ for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) { if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { + tegra241_vcmdq_map_lvcmdq(vintf->lvcmdqs[lidx]); ret = tegra241_vcmdq_hw_init(vintf->lvcmdqs[lidx]); if (ret) { tegra241_vintf_hw_deinit(vintf); @@ -476,7 +506,6 @@ static int tegra241_cmdqv_hw_reset(struct arm_smmu_device *smmu) for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) { regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx); regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx); - regval |= CMDQV_CMDQ_ALLOCATED; writel_relaxed(regval, REG_CMDQV(cmdqv, CMDQ_ALLOC(qidx++))); } -- 2.43.0