From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CB0DEE4996 for ; Mon, 21 Aug 2023 02:35:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232569AbjHUCfN (ORCPT ); Sun, 20 Aug 2023 22:35:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232568AbjHUCfL (ORCPT ); Sun, 20 Aug 2023 22:35:11 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 40A48B0; Sun, 20 Aug 2023 19:35:05 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 90D371FB; Sun, 20 Aug 2023 19:35:45 -0700 (PDT) Received: from [10.162.42.6] (a077893.blr.arm.com [10.162.42.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4293E3F762; Sun, 20 Aug 2023 19:35:00 -0700 (PDT) Message-ID: Date: Mon, 21 Aug 2023 08:04:58 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH V4 1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus Content-Language: en-US To: Randy Dunlap , linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org References: <20230818112051.594986-1-anshuman.khandual@arm.com> <20230818112051.594986-2-anshuman.khandual@arm.com> <51f4b571-a5b2-b1bb-b990-fe2c4c5387bf@infradead.org> From: Anshuman Khandual In-Reply-To: <51f4b571-a5b2-b1bb-b990-fe2c4c5387bf@infradead.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On 8/19/23 02:41, Randy Dunlap wrote: > Hi-- > > On 8/18/23 04:20, Anshuman Khandual wrote: >> This work arounds errata 1490853 on Cortex-A76, and Neoverse-N1, errata >> 1491015 on Cortex-A77, errata 1502854 on Cortex-X1, and errata 1619801 on >> Neoverse-V1, based affected cpus, where software read for TRCIDR3.CCITMIN >> field in ETM gets an wrong value. >> >> If software uses the value returned by the TRCIDR3.CCITMIN register field, >> then it will limit the range which could be used for programming the ETM. >> In reality, the ETM could be programmed with a much smaller value than what >> is indicated by the TRCIDR3.CCITMIN field and still function correctly. >> >> If software reads the TRCIDR3.CCITMIN register field, corresponding to the >> instruction trace counting minimum threshold, observe the value 0x100 or a >> minimum cycle count threshold of 256. The correct value should be 0x4 or a >> minimum cycle count threshold of 4. >> >> This work arounds the problem via storing 4 in drvdata->ccitmin on affected >> systems where the TRCIDR3.CCITMIN has been 256, thus preserving cycle count >> threshold granularity. >> >> These errata information has been updated in arch/arm64/silicon-errata.rst, >> but without their corresponding configs because these have been implemented >> directly in the driver. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Suzuki K Poulose >> Cc: Mike Leach >> Cc: James Clark >> Cc: Jonathan Corbet >> Cc: linux-doc@vger.kernel.org >> Cc: coresight@lists.linaro.org >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual >> --- >> Documentation/arch/arm64/silicon-errata.rst | 10 ++++++ >> .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++++++ >> 2 files changed, 46 insertions(+) >> > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 7e307022303a..591fab73ee79 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -1131,6 +1131,39 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) >> drvdata->trfcr = trfcr; >> } >> >> +/* >> + * The following errata on applicable cpu ranges, affect the CCITMIN filed >> + * in TCRIDR3 register. Software read for the field returns 0x100 limiting >> + * the cycle threshold granularity, where as the right value should have > > whereas > >> + * been 0x4, which is well supported in the hardware. >> + */ >> +static struct midr_range etm_wrong_ccitmin_cpus[] = { >> + /* Erratum #1490853 - Cortex-A76 */ >> + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0), >> + /* Erratum #1490853 - Neoverse-N1 */ >> + MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0), >> + /* Erratum #1491015 - Cortex-A77 */ >> + MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0), >> + /* Erratum #1502854 - Cortex-X1 */ >> + MIDR_REV(MIDR_CORTEX_X1, 0, 0), >> + /* Erratum #1619801 - Neoverse-V1 */ >> + MIDR_REV(MIDR_NEOVERSE_V1, 0, 0), >> + {}, >> +}; >> + >> +static bool etm4_core_reads_wrong_ccitmin(struct etmv4_drvdata *drvdata) >> +{ >> + /* >> + * Erratum affected cpus will read 256 as the minimum >> + * instruction trace cycle counting threshold where as > > whereas Right, 'whereas' is a single word indeed. I will change these as required.