From: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
To: "Tomeu Vizoso" <tomeu@tomeuvizoso.net>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Oded Gabbay" <ogabbay@kernel.org>,
"Jonathan Corbet" <corbet@lwn.net>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>,
"Sebastian Reichel" <sebastian.reichel@collabora.com>,
"Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>,
"Kever Yang" <kever.yang@rock-chips.com>,
"Robin Murphy" <robin.murphy@arm.com>,
"Daniel Stone" <daniel@fooishbar.org>,
"Da Xue" <da@libre.computer>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org,
linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org,
Robert Foss <rfoss@kernel.org>
Subject: Re: [PATCH v8 01/10] accel/rocket: Add registers header
Date: Fri, 18 Jul 2025 11:09:33 -0600 [thread overview]
Message-ID: <b7653a05-f747-4764-9c33-793346cae223@oss.qualcomm.com> (raw)
In-Reply-To: <20250713-6-10-rocket-v8-1-64fa3115e910@tomeuvizoso.net>
On 7/13/2025 2:38 AM, Tomeu Vizoso wrote:
> A XML file was generated with the data from the TRM, and then this
> header was generated from it.
>
> The canonical location for the XML file is the Mesa3D repository.
>
> v3:
> - Make use of GPL-2.0-only for the copyright notice (Jeff Hugo)
>
> v8:
> - Remove full MIT license blob, to match other files with the same
> licensing arrangement in the kernel
>
> Reviewed-by: Robert Foss <rfoss@kernel.org>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Structure of the file and markings look sane. I'm not familiar with the
hardware specifics, so the autogenerated content is a bit over my head,
but I guess for something so large using automated generation should
minimize errors.
Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
next prev parent reply other threads:[~2025-07-18 17:09 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-13 8:38 [PATCH v8 00/10] New DRM accel driver for Rockchip's RKNN NPU Tomeu Vizoso
2025-07-13 8:38 ` [PATCH v8 01/10] accel/rocket: Add registers header Tomeu Vizoso
2025-07-18 17:09 ` Jeff Hugo [this message]
2025-07-13 8:38 ` [PATCH v8 02/10] accel/rocket: Add a new driver for Rockchip's NPU Tomeu Vizoso
2025-07-18 17:14 ` Jeff Hugo
2025-07-13 8:38 ` [PATCH v8 03/10] accel/rocket: Add IOCTL for BO creation Tomeu Vizoso
2025-07-13 8:38 ` [PATCH v8 04/10] accel/rocket: Add job submission IOCTL Tomeu Vizoso
2025-07-18 17:26 ` Jeff Hugo
2025-07-13 8:38 ` [PATCH v8 05/10] accel/rocket: Add IOCTLs for synchronizing memory accesses Tomeu Vizoso
2025-07-13 8:38 ` [PATCH v8 06/10] dt-bindings: npu: rockchip,rknn: Add bindings Tomeu Vizoso
2025-07-13 8:38 ` [PATCH v8 07/10] arm64: dts: rockchip: add pd_npu label for RK3588 power domains Tomeu Vizoso
2025-07-13 8:38 ` [PATCH v8 08/10] arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588-base Tomeu Vizoso
2025-07-16 14:58 ` Heiko Stübner
2025-07-13 8:38 ` [PATCH v8 09/10] arm64: dts: rockchip: Enable the NPU on quartzpro64 Tomeu Vizoso
2025-07-13 8:39 ` [PATCH v8 10/10] arm64: dts: rockchip: enable NPU on ROCK 5B Tomeu Vizoso
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