From: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>
To: "Mehta, Sohil" <sohil.mehta@intel.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
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Subject: Re: [PATCH v10 12/15] x86/traps: Communicate a LASS violation in #GP message
Date: Tue, 7 Oct 2025 18:07:20 +0000 [thread overview]
Message-ID: <b8876f149adfcd47e60a0a6e1640b97c321e6a74.camel@intel.com> (raw)
In-Reply-To: <20251007065119.148605-13-sohil.mehta@intel.com>
On Mon, 2025-10-06 at 23:51 -0700, Sohil Mehta wrote:
> From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
>
> A LASS violation typically results in a #GP. Provide a more helpful
> message for a #GP when a kernel-side LASS violation is detected.
>
> Currently, a kernel NULL pointer dereference triggers a #PF, which
> prints a helpful message. Because LASS enforcement is pre-paging,
> accesses to the first page frame would now be reported as a #GP, with an
> LASS violation hint. Add a special case to print a friendly message
> specifically for kernel NULL pointer dereferences.
>
> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
> ---
> v10:
> - Minor improvement to code comments and hints.
> ---
> arch/x86/kernel/traps.c | 45 ++++++++++++++++++++++++++++++-----------
> 1 file changed, 33 insertions(+), 12 deletions(-)
>
> diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
> index 59bfbdf0a1a0..a5d10f7ae038 100644
> --- a/arch/x86/kernel/traps.c
> +++ b/arch/x86/kernel/traps.c
> @@ -636,13 +636,23 @@ DEFINE_IDTENTRY(exc_bounds)
> enum kernel_gp_hint {
> GP_NO_HINT,
> GP_NON_CANONICAL,
> - GP_CANONICAL
> + GP_CANONICAL,
> + GP_LASS_VIOLATION,
> + GP_NULL_POINTER,
> +};
> +
> +static const char * const kernel_gp_hint_help[] = {
> + [GP_NON_CANONICAL] = "probably for non-canonical address",
> + [GP_CANONICAL] = "maybe for address",
> + [GP_LASS_VIOLATION] = "probably LASS violation for address",
> + [GP_NULL_POINTER] = "kernel NULL pointer dereference",
> };
>
> /*
> * When an uncaught #GP occurs, try to determine the memory address accessed by
> * the instruction and return that address to the caller. Also, try to figure
> - * out whether any part of the access to that address was non-canonical.
> + * out whether any part of the access to that address was non-canonical or
> + * across privilege levels.
> */
> static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
> unsigned long *addr)
> @@ -664,14 +674,27 @@ static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
> return GP_NO_HINT;
The patch looks good. I'm not sure how fancy we want to get here, but an idea if
you want it...
Above this hunk is:
if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
MAX_INSN_SIZE))
return EXC_NO_HINT;
If cpu_feature_enabled(X86_FEATURE_LASS) and regs->ip is in the lower half, we
could make a pretty strong guess that it was a LASS violation. I guess the same
argument could be made for the canonical guess work, but maybe calling a NULL
function pointer is more likely.
>
> #ifdef CONFIG_X86_64
> - /*
> - * Check that:
> - * - the operand is not in the kernel half
> - * - the last byte of the operand is not in the user canonical half
> - */
> - if (*addr < ~__VIRTUAL_MASK &&
> - *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
> + /* Operand is in the kernel half */
> + if (*addr >= ~__VIRTUAL_MASK)
> + return GP_CANONICAL;
> +
> + /* The last byte of the operand is not in the user canonical half */
> + if (*addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
> return GP_NON_CANONICAL;
> +
> + /*
> + * If LASS is active, a NULL pointer dereference generates a #GP
> + * instead of a #PF.
> + */
> + if (*addr < PAGE_SIZE)
> + return GP_NULL_POINTER;
> +
> + /*
> + * Assume that LASS caused the exception, because the address is
> + * canonical and in the user half.
> + */
> + if (cpu_feature_enabled(X86_FEATURE_LASS))
> + return GP_LASS_VIOLATION;
> #endif
>
> return GP_CANONICAL;
> @@ -835,9 +858,7 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
>
> if (hint != GP_NO_HINT)
> snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
> - (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
> - : "maybe for address",
> - gp_addr);
> + kernel_gp_hint_help[hint], gp_addr);
>
> /*
> * KASAN is interested only in the non-canonical case, clear it
next prev parent reply other threads:[~2025-10-07 18:07 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-07 6:51 [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 01/15] x86/cpu: Enumerate the LASS feature bits Sohil Mehta
2025-10-07 18:19 ` Edgecombe, Rick P
2025-10-07 18:28 ` Dave Hansen
2025-10-07 20:20 ` Sohil Mehta
2025-10-07 20:38 ` Edgecombe, Rick P
2025-10-07 20:53 ` Sohil Mehta
2025-10-16 3:10 ` H. Peter Anvin
2025-10-07 20:49 ` Sohil Mehta
2025-10-07 23:16 ` Xin Li
2025-10-08 16:00 ` Edgecombe, Rick P
2025-10-16 15:35 ` Borislav Petkov
2025-10-21 18:03 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 02/15] x86/asm: Introduce inline memcpy and memset Sohil Mehta
2025-10-21 12:47 ` Borislav Petkov
2025-10-21 13:48 ` David Laight
2025-10-21 18:06 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 03/15] x86/alternatives: Disable LASS when patching kernel alternatives Sohil Mehta
2025-10-07 16:55 ` Edgecombe, Rick P
2025-10-07 22:28 ` Sohil Mehta
2025-10-08 16:22 ` Edgecombe, Rick P
2025-10-10 17:10 ` Sohil Mehta
2025-10-21 20:03 ` Borislav Petkov
2025-10-21 20:55 ` Sohil Mehta
2025-10-22 9:56 ` Borislav Petkov
2025-10-22 19:49 ` Sohil Mehta
2025-10-22 20:03 ` Luck, Tony
2025-10-22 8:25 ` Peter Zijlstra
2025-10-22 9:40 ` Borislav Petkov
2025-10-22 10:22 ` Peter Zijlstra
2025-10-22 10:52 ` Borislav Petkov
2025-10-07 6:51 ` [PATCH v10 04/15] x86/cpu: Set LASS CR4 bit as pinning sensitive Sohil Mehta
2025-10-07 18:24 ` Edgecombe, Rick P
2025-10-07 23:11 ` Sohil Mehta
2025-10-08 16:52 ` Edgecombe, Rick P
2025-10-10 19:03 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 05/15] x86/cpu: Defer CR pinning enforcement until late_initcall() Sohil Mehta
2025-10-07 17:23 ` Edgecombe, Rick P
2025-10-07 23:05 ` Sohil Mehta
2025-10-08 17:36 ` Edgecombe, Rick P
2025-10-10 20:45 ` Sohil Mehta
2025-10-15 21:17 ` Sohil Mehta
2025-10-17 19:28 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 06/15] x86/efi: Disable LASS while mapping the EFI runtime services Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 07/15] x86/kexec: Disable LASS during relocate kernel Sohil Mehta
2025-10-07 17:43 ` Edgecombe, Rick P
2025-10-07 22:33 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 08/15] x86/vsyscall: Reorganize the page fault emulation code Sohil Mehta
2025-10-07 18:37 ` Edgecombe, Rick P
2025-10-07 18:48 ` Dave Hansen
2025-10-07 19:53 ` Edgecombe, Rick P
2025-10-07 22:52 ` Sohil Mehta
2025-10-08 17:42 ` Edgecombe, Rick P
2025-10-30 16:58 ` Andy Lutomirski
2025-10-30 17:22 ` H. Peter Anvin
2025-10-30 17:35 ` Andy Lutomirski
2025-10-30 19:28 ` Sohil Mehta
2025-10-30 21:37 ` David Laight
2025-10-07 6:51 ` [PATCH v10 09/15] x86/traps: Consolidate user fixups in exc_general_protection() Sohil Mehta
2025-10-07 17:46 ` Edgecombe, Rick P
2025-10-07 22:41 ` Sohil Mehta
2025-10-08 17:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 10/15] x86/vsyscall: Add vsyscall emulation for #GP Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 11/15] x86/vsyscall: Disable LASS if vsyscall mode is set to EMULATE Sohil Mehta
2025-10-07 18:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 12/15] x86/traps: Communicate a LASS violation in #GP message Sohil Mehta
2025-10-07 18:07 ` Edgecombe, Rick P [this message]
2025-10-07 6:51 ` [PATCH v10 13/15] x86/traps: Generalize #GP address decode and hint code Sohil Mehta
2025-10-07 18:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 14/15] x86/traps: Provide additional hints for a kernel stack segment fault Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 15/15] x86/cpu: Enable LASS by default during CPU initialization Sohil Mehta
2025-10-07 18:42 ` Edgecombe, Rick P
2025-10-07 16:23 ` [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Edgecombe, Rick P
2025-10-17 19:52 ` Sohil Mehta
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