From: Randy Dunlap <rdunlap@infradead.org>
To: Avi Radinsky <avi.radinsky@tennr.com>,
palmer@dabbelt.com, pjw@kernel.org, aou@eecs.berkeley.edu,
alex@ghiti.fr, corbet@lwn.net
Cc: linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] Documentation: riscv: cmodx: fix typos
Date: Wed, 29 Apr 2026 15:38:46 -0700 [thread overview]
Message-ID: <bae95436-6685-4fe7-b795-feba4192cb58@infradead.org> (raw)
In-Reply-To: <391d16fb-5f11-45fa-8f3b-1debe095695e@tennr.com>
On 4/29/26 3:35 PM, Avi Radinsky wrote:
> Fix typos in the dynamic ftrace section: atmoic -> atomic (twice),
> pacthable -> patchable, derect -> directed.
>
> Signed-off-by: Avi Radinsky <avi.radinsky@tennr.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Thanks.
> ---
> Documentation/arch/riscv/cmodx.rst | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/cmodx.rst
> index 40ba53bed..cbfa812a1 100644
> --- a/Documentation/arch/riscv/cmodx.rst
> +++ b/Documentation/arch/riscv/cmodx.rst
> @@ -21,13 +21,13 @@ call at each patchable function entry, and patches it dynamically at runtime to
> enable or disable the redirection. In the case of RISC-V, 2 instructions,
> AUIPC + JALR, are required to compose a function call. However, it is impossible
> to patch 2 instructions and expect that a concurrent read-side executes them
> -without a race condition. This series makes atmoic code patching possible in
> +without a race condition. This series makes atomic code patching possible in
> RISC-V ftrace. Kernel preemption makes things even worse as it allows the old
> state to persist across the patching process with stop_machine().
>
> In order to get rid of stop_machine() and run dynamic ftrace with full kernel
> preemption, we partially initialize each patchable function entry at boot-time,
> -setting the first instruction to AUIPC, and the second to NOP. Now, atmoic
> +setting the first instruction to AUIPC, and the second to NOP. Now, atomic
> patching is possible because the kernel only has to update one instruction.
> According to Ziccif, as long as an instruction is naturally aligned, the ISA
> guarantee an atomic update.
> @@ -36,8 +36,8 @@ By fixing down the first instruction, AUIPC, the range of the ftrace trampoline
> is limited to +-2K from the predetermined target, ftrace_caller, due to the lack
> of immediate encoding space in RISC-V. To address the issue, we introduce
> CALL_OPS, where an 8B naturally align metadata is added in front of each
> -pacthable function. The metadata is resolved at the first trampoline, then the
> -execution can be derect to another custom trampoline.
> +patchable function. The metadata is resolved at the first trampoline, then the
> +execution can be directed to another custom trampoline.
>
> CMODX in the User Space
> -----------------------
--
~Randy
next prev parent reply other threads:[~2026-04-29 22:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-29 22:35 [PATCH] Documentation: riscv: cmodx: fix typos Avi Radinsky
2026-04-29 22:38 ` Randy Dunlap [this message]
2026-04-30 20:08 ` Paul Walmsley
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