From: "Bowman, Terry" <terry.bowman@amd.com>
To: Jonathan Cameron <jic23@kernel.org>
Cc: Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Bjorn Helgaas <bhelgaas@google.com>,
Dan Williams <djbw@kernel.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
linux-cxl@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
Borislav Petkov <bp@alien8.de>, Hanjun Guo <guohanjun@huawei.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Shuai Xue <xueshuai@linux.alibaba.com>,
Len Brown <lenb@kernel.org>, Ira Weiny <iweiny@kernel.org>,
Li Ming <ming.li@zohomail.com>,
Shuah Khan <skhan@linuxfoundation.org>,
Ben Cheatham <Benjamin.Cheatham@amd.com>,
Richard Cheng <icheng@nvidia.com>,
Robert Richter <rrichter@amd.com>, Lukas Wunner <lukas@wunner.de>,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v20 1/9] PCI/AER: Introduce AER-CXL protocol error kfifo
Date: Wed, 9 Sep 2026 10:38:53 -0500 [thread overview]
Message-ID: <bb5a6b0a-c30b-4475-8be6-f3e3686c93be@amd.com> (raw)
In-Reply-To: <20260908015144.62ee9c1c@jic23-huawei>
On 9/7/2026 7:51 PM, Jonathan Cameron wrote:
> On Wed, 2 Sep 2026 08:39:25 -0500
> Terry Bowman <terry.bowman@amd.com> wrote:
>
>> CXL VH RAS handling requires the AER driver to hand off CXL protocol
>> errors to cxl_core for logging and recovery before PCIe AER recovery
>> tears down the device. Introduce pci/pcie/aer_cxl_vh.c to implement
>> this handoff via a kfifo-backed work item.
>>
>> The producer, cxl_forward_error(), is gated by is_cxl_error() and
>> enqueues the error source PCI device and severity. cxl_core registers a
>> consumer via cxl_register_proto_err_work(); the consumer drains the
>> kfifo with for_each_cxl_proto_err(). For uncorrectable errors,
>> cxl_proto_err_wait_for_empty() lets the AER path block until the CXL
>> plane has finished so recovery does not race device teardown.
>
> Do we need most of this last paragraph?
> Maybe the bit about letting AER block but the rest smells like implementation
> details to me with no info on 'why' or anything unexpected.
It is implementation centric. This can be reduced.
>>
>> A rwsem serializes registration, deregistration, enqueue, and dequeue
>> against concurrent AER IRQ threads; a spinlock serializes concurrent
>> kfifo writers. is_aer_internal_error() moves into this file and now
>> evaluates info->status & ~info->mask rather than the raw info->status,
>> so a masked internal-error bit is treated as not-set. For the RCH RCEC
>> path this is equivalent because cxl_rch_enable_rcec() first calls
>> pci_aer_unmask_internal_errors(), which clears those mask bits in
>> hardware before the AER status is read back.
>>
>> A subsequent patch wires cxl_forward_error() into handle_error_source().
>>
>> Add MAINTAINERS entries for aer_cxl_vh.c and aer_cxl_rch.c under the CXL
>> entry.
>
> I couldn't immediately find any discussion about switching away from panic
> on a kfifo overflow. Was there a reply to an earlier version with a
> discussion of that? I'm not against the change but a 'why'
> here would be good to have.
>
The driver panics on kfifo full error during UCE enqueue. This was recommended by you and
Richard. Changes are at the link below in cxl_forward_error():
https://lore.kernel.org/linux-cxl/20260902133933.2992457-2-terry.bowman@amd.com/
>>
>> Co-developed-by: Dan Williams <djbw@kernel.org>
>> Signed-off-by: Dan Williams <djbw@kernel.org>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> One trivial thing inline to add to Ben's nits.
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
>
>> +/**
>> + * Callback for processing a CXL protocol error from the AER-CXL kfifo.
>> + */
>> +typedef void (*cxl_proto_err_fn_t)(struct cxl_proto_err_work_data *wd);
>> +
>> +void cxl_register_proto_err_work(struct work_struct *work,
>> + void (*flush)(void));
>
> Align to after the ( Looks to be 1 space short. If this is a local
> style thing ignore me ;)
>
Ok.
-Terry
>> +void for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,
>> + cxl_proto_err_fn_t fn);
>> +void cxl_unregister_proto_err_work(void);
>> +#endif
>> +
>> void pci_print_aer(struct pci_dev *dev, int aer_severity,
>> struct aer_capability_regs *aer);
>> int cper_severity_to_aer(int cper_severity);
>>
>> base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
>
next prev parent reply other threads:[~2026-09-09 15:39 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 13:39 [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-09-02 13:39 ` [PATCH v20 1/9] PCI/AER: Introduce AER-CXL protocol error kfifo Terry Bowman
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-08 0:51 ` Jonathan Cameron
2026-09-09 15:38 ` Bowman, Terry [this message]
2026-09-09 22:02 ` Jonathan Cameron
2026-09-10 14:57 ` Bowman, Terry
2026-09-02 13:39 ` [PATCH v20 2/9] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-10 16:55 ` Bowman, Terry
2026-09-08 0:57 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 3/9] cxl/ras: Handle RCH correctable and uncorrectable errors in one pass Terry Bowman
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-08 1:06 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 4/9] cxl/pci: Thread port and dport through RAS handling helpers Terry Bowman
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-09 14:42 ` Bowman, Terry
2026-09-09 15:21 ` Bowman, Terry
2026-09-08 17:47 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 5/9] cxl: Update CXL Endpoint AER handler Terry Bowman
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-02 13:39 ` [PATCH v20 6/9] PCI: Cache PCI DSN into pci_dev->dsn during probe Terry Bowman
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-09 15:16 ` Lukas Wunner
2026-09-02 13:39 ` [PATCH v20 7/9] cxl: Add port and dport identifiers to CXL AER trace events Terry Bowman
2026-09-08 18:13 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 8/9] PCI/CXL: Mask/Unmask CXL protocol errors Terry Bowman
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-02 13:39 ` [PATCH v20 9/9] Documentation: cxl: Document CXL protocol error handling Terry Bowman
2026-09-08 18:39 ` Jonathan Cameron
2026-09-10 15:19 ` Bowman, Terry
2026-09-09 16:03 ` [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging Lukas Wunner
2026-09-09 20:31 ` Bowman, Terry
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