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([2600:8803:e7e4:1d00:f7b4:dfbd:5110:c59d]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3196d4c1132sm369525fac.28.2025.08.30.10.33.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Aug 2025 10:33:04 -0700 (PDT) Message-ID: Date: Sat, 30 Aug 2025 12:33:04 -0500 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 13/15] iio: adc: ad4030: Enable dual data rate To: Marcelo Schmitt , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-spi@vger.kernel.org Cc: jic23@kernel.org, Michael.Hennerich@analog.com, nuno.sa@analog.com, eblanc@baylibre.com, andy@kernel.org, corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org, Jonathan.Cameron@huawei.com, andriy.shevchenko@linux.intel.com, ahaslam@baylibre.com, sergiu.cuciurean@analog.com, marcelo.schmitt1@gmail.com References: <47b2cf01555c31126bc2133526317c7829cb59ab.1756511030.git.marcelo.schmitt@analog.com> Content-Language: en-US From: David Lechner In-Reply-To: <47b2cf01555c31126bc2133526317c7829cb59ab.1756511030.git.marcelo.schmitt@analog.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 8/29/25 7:45 PM, Marcelo Schmitt wrote: > Set AD4030 series device to do two data bit transitions per clock cycle per > active lane when specified by firmware. The dual data rate (DDR) feature is > available only for host clock mode and echo clock mode. > > Co-developed-by: Sergiu Cuciurean > Signed-off-by: Sergiu Cuciurean > Signed-off-by: Marcelo Schmitt > --- > drivers/iio/adc/ad4030.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c > index a5931056936a..37ba00097efe 100644 > --- a/drivers/iio/adc/ad4030.c > +++ b/drivers/iio/adc/ad4030.c > @@ -74,6 +74,7 @@ > (AD4030_REG_GAIN_X0_MSB + (AD4030_REG_GAIN_BYTES_NB * (ch))) > #define AD4030_REG_MODES 0x20 > #define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0) > +#define AD4030_REG_MODES_MASK_DDR_MODE BIT(3) > #define AD4030_REG_MODES_MASK_CLOCK_MODE GENMASK(5, 4) > #define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6) > #define AD4030_REG_OSCILATOR 0x21 > @@ -175,6 +176,7 @@ struct ad4030_state { > enum ad4030_out_mode mode; > enum ad4030_lane_mode lane_mode; > enum ad4030_clock_mode clock_mode; > + bool ddr; > /* offload sampling spi message */ > struct spi_transfer offload_xfer; > struct spi_message offload_msg; > @@ -1218,6 +1220,9 @@ static void ad4030_prepare_offload_msg(struct ad4030_state *st) > else > offload_bpw = data_width / (1 << st->lane_mode); > > + if (st->ddr) > + offload_bpw /= 2; > + There is already an existing dtr_mode flag in struct spi_transfer. We should be using that instead of providing an inaccurate bits per word value. > st->offload_xfer.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED; > st->offload_xfer.bits_per_word = offload_bpw; > st->offload_xfer.len = roundup_pow_of_two(BITS_TO_BYTES(offload_bpw)); > @@ -1271,6 +1276,12 @@ static int ad4030_config(struct ad4030_state *st) > reg_modes |= FIELD_PREP(AD4030_REG_MODES_MASK_CLOCK_MODE, > ret >= 0 ? ret : AD4030_SPI_CLOCK_MODE); > > + /* DDR is only valid for echo clock and host clock modes */ > + if (ret == AD4030_ECHO_CLOCK_MODE || ret == AD4030_CLOCK_HOST_MODE) { > + st->ddr = device_property_read_bool(dev, "adi,dual-data-rate"); As mentioned in the dt-bindings patch review, we can already get this info from the spi controller via dtr_caps. > + reg_modes |= FIELD_PREP(AD4030_REG_MODES_MASK_DDR_MODE, st->ddr); > + } > + > ret = regmap_write(st->regmap, AD4030_REG_MODES, reg_modes); > if (ret) > return ret; We will need a separate patch to add support for dtr_caps and dtr_mode to the axi-spi-engine driver. And likely some HDL work for that as well. So I would suggest splitting this out into a separate series.