Re: [PATCH v3] cxl: docs/driver-api/conventions resolve conflicts btw CFMWS, LMH, ED

[Dave Jiang <dave.jiang@intel.com>]

On 6/23/25 12:19 PM, Gregory Price wrote:
> On Mon, Jun 23, 2025 at 05:29:02PM +0200, Fabio M. De Francesco wrote:
>> Add documentation on how to resolve conflicts between CXL Fixed Memory
>> Windows, Platform Memory Holes, and Endpoint Decoders.
>>
>> Signed-off-by: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
> 
> I won't block a doc update on a suggestion so
> 
> Reviewed-by: Gregory Price <gourry@gourry.net>
> 
>> +Platform Firmware (BIOS) might reserve part of physical addresses below
>> +4 GB (e.g., the Low Memory Hole that describes PCIe memory space for MMIO
>> +or a requirement for the greater than 8 way interleave CXL regions starting
>> +at address 0). In that case the Window Size value cannot be anymore
>> +constrained to the NIW * 256 MB above-mentioned rule.
> 
> It might be nice to have a diagram that explains this visually, as it's
> difficult for me to understand the implications through words alone...

+1 on request for diagram to explain. We should try to document this issue as clearly as possible. Thank you.

> 
> which is likely why the conflict exists in the first place :]
> 
> ~Gregory