From: Sohil Mehta <sohil.mehta@intel.com>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
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"Paul E. McKenney" <paulmck@kernel.org>,
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Tony Luck <tony.luck@intel.com>,
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Cc: Jonathan Corbet <corbet@lwn.net>, Ingo Molnar <mingo@kernel.org>,
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<linux-efi@vger.kernel.org>, <linux-mm@kvack.org>
Subject: Re: [PATCHv8 13/17] x86/traps: Generalize #GP address decode and hint code
Date: Tue, 1 Jul 2025 17:54:44 -0700 [thread overview]
Message-ID: <d777b118-68d1-4212-a33e-d129d777515f@intel.com> (raw)
In-Reply-To: <20250701095849.2360685-14-kirill.shutemov@linux.intel.com>
On 7/1/2025 2:58 AM, Kirill A. Shutemov wrote:
> Handlers for #GP and #SS will now share code to decode the exception
> address and retrieve the exception hint string.
>
This is missing an essential "why"? Why do #GP and #SS handlers need to
share code? None of the patches prior to this have hinted this.
It can probably be deduced from a later patch, but it needs to be
clarified in this one. Maybe a simplified version of the text from the SDM:
"In most cases, an access causing a LASS violation results in a general
protection exception (#GP); for stack accesses (those due to
stack-oriented instructions, as well as accesses that implicitly or
explicitly use the SS segment register), a stack fault (#SS) is generated."
> The helper, enum, and array should be renamed as they are no longer
> specific to #GP.
>
> No functional change intended.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> ---
> arch/x86/kernel/traps.c | 62 ++++++++++++++++++++---------------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
The code changes look okay to me except a minor nit below.
> #define GPFSTR "general protection fault"
> @@ -808,8 +808,8 @@ static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr,
> DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
> {
> char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
> - enum kernel_gp_hint hint = GP_NO_HINT;
> - unsigned long gp_addr;
gp_addr is a local variable to the #GP handler. It can probably stay the
same.
> + enum kernel_exc_hint hint = EXC_NO_HINT;
> + unsigned long exc_addr;
>
> if (user_mode(regs) && try_fixup_enqcmd_gp())
> return;
> @@ -846,21 +846,21 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
> if (error_code)
> snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
> else
> - hint = get_kernel_gp_address(regs, &gp_addr);
> + hint = get_kernel_exc_address(regs, &exc_addr);
>
> - if (hint != GP_NO_HINT) {
> + if (hint != EXC_NO_HINT) {
> snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
> - kernel_gp_hint_help[hint], gp_addr);
> + kernel_exc_hint_help[hint], exc_addr);
> }
>
> /*
> * KASAN is interested only in the non-canonical case, clear it
> * otherwise.
> */
> - if (hint != GP_NON_CANONICAL)
> - gp_addr = 0;
> + if (hint != EXC_NON_CANONICAL)
> + exc_addr = 0;
>
> - die_addr(desc, regs, error_code, gp_addr);
> + die_addr(desc, regs, error_code, exc_addr);
>
> exit:
> cond_local_irq_disable(regs);
next prev parent reply other threads:[~2025-07-02 0:55 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-01 9:58 [PATCHv8 00/17] x86: Enable Linear Address Space Separation support Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 01/17] x86/cpu: Enumerate the LASS feature bits Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 02/17] x86/asm: Introduce inline memcpy and memset Kirill A. Shutemov
2025-07-03 8:44 ` David Laight
2025-07-03 10:39 ` Kirill A. Shutemov
2025-07-03 12:15 ` David Laight
2025-07-03 13:33 ` Vegard Nossum
2025-07-03 16:52 ` David Laight
2025-07-03 14:10 ` Kirill A. Shutemov
2025-07-03 17:02 ` David Laight
2025-07-03 17:13 ` Dave Hansen
2025-07-04 9:04 ` Kirill A. Shutemov
2025-07-06 9:13 ` David Laight
2025-07-07 8:02 ` Kirill A. Shutemov
2025-07-07 9:33 ` David Laight
2025-07-01 9:58 ` [PATCHv8 03/17] x86/alternatives: Disable LASS when patching kernel alternatives Kirill A. Shutemov
2025-07-01 18:44 ` Sohil Mehta
2025-07-01 9:58 ` [PATCHv8 04/17] x86/cpu: Defer CR pinning setup until after EFI initialization Kirill A. Shutemov
2025-07-01 19:03 ` Sohil Mehta
2025-07-02 9:47 ` Kirill A. Shutemov
2025-07-01 23:10 ` Dave Hansen
2025-07-02 10:05 ` Kirill A. Shutemov
2025-07-04 12:23 ` Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 05/17] efi: Disable LASS around set_virtual_address_map() EFI call Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 06/17] x86/vsyscall: Do not require X86_PF_INSTR to emulate vsyscall Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 07/17] x86/vsyscall: Reorganize the #PF emulation code Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 08/17] x86/traps: Consolidate user fixups in exc_general_protection() Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 09/17] x86/vsyscall: Add vsyscall emulation for #GP Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 10/17] x86/vsyscall: Disable LASS if vsyscall mode is set to EMULATE Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 11/17] x86/cpu: Set LASS CR4 bit as pinning sensitive Kirill A. Shutemov
2025-07-01 22:51 ` Sohil Mehta
2025-07-01 9:58 ` [PATCHv8 12/17] x86/traps: Communicate a LASS violation in #GP message Kirill A. Shutemov
2025-07-02 0:36 ` Sohil Mehta
2025-07-02 10:10 ` Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 13/17] x86/traps: Generalize #GP address decode and hint code Kirill A. Shutemov
2025-07-02 0:54 ` Sohil Mehta [this message]
2025-07-01 9:58 ` [PATCHv8 14/17] x86/traps: Handle LASS thrown #SS Kirill A. Shutemov
2025-07-02 1:35 ` Sohil Mehta
2025-07-02 2:00 ` H. Peter Anvin
2025-07-02 2:06 ` H. Peter Anvin
2025-07-02 10:17 ` Kirill A. Shutemov
2025-07-02 14:37 ` H. Peter Anvin
2025-07-02 14:47 ` Kirill A. Shutemov
2025-07-02 17:10 ` H. Peter Anvin
2025-07-02 23:42 ` Andrew Cooper
2025-07-03 0:44 ` H. Peter Anvin
2025-07-06 9:22 ` David Laight
2025-07-06 15:07 ` H. Peter Anvin
2025-07-02 13:27 ` Kirill A. Shutemov
2025-07-02 17:56 ` Sohil Mehta
2025-07-03 10:40 ` Kirill A. Shutemov
2025-07-02 20:05 ` Sohil Mehta
2025-07-03 11:31 ` Kirill A. Shutemov
2025-07-03 20:12 ` Sohil Mehta
2025-07-04 9:23 ` Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 15/17] x86/cpu: Make LAM depend on LASS Kirill A. Shutemov
2025-07-01 23:03 ` Sohil Mehta
2025-07-01 9:58 ` [PATCHv8 16/17] x86/cpu: Enable LASS during CPU initialization Kirill A. Shutemov
2025-07-01 9:58 ` [PATCHv8 17/17] x86: Re-enable Linear Address Masking Kirill A. Shutemov
2025-07-01 23:13 ` Sohil Mehta
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