From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-173.mta0.migadu.com (out-173.mta0.migadu.com [91.218.175.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4F8431A567 for ; Tue, 26 Aug 2025 16:09:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.173 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756224543; cv=none; b=k/rC0XuFGX03waCKFlLd4CvlxTr0reYw1BTeP2fOH5gkRCnFPdWVK3QhqFxw7IyP3GUVKNFUBKxs4/w5Uv8k+ynsnZeWjJPtBsKbHEpnv7Ws78meAdAaxzwEk8OIWD27zY31284coLmC67HY6fl6vsB0pFPtHEuSqXHn4LjnCRE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756224543; c=relaxed/simple; bh=JsPCrAShvmrujDQQBA9SPlEujcEeHWEZeiiLzvDO7Y0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NJ8/NIzAEIreP2ScA99ho4lk46rb+9NAiB51H7nkpbxvxaJ1Jdp/MxZiGp6RUpYDhqi8Wa5PZce9tYIbc2b8b1sNRyoXltuQhuzConrVk2jRveiyO3LngLRb7dou2/kvJdG/f9Pyf5KrwvjJnOsqExU3yY5Z/1qzL04IjsXjE30= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=c+wKEpVu; arc=none smtp.client-ip=91.218.175.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="c+wKEpVu" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1756224539; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OE4jLvMS6uO3y2vgaMfshtzsi+abCnBQzBD93FRis7A=; b=c+wKEpVucr0QXYUkhDCENcM4dxbVhyHuGs2uKQrpP0yGoYEclDtFg9zdALOROHTGbJ+9qb Tc80Tz7qjAX3TwD/JmRqqb9L23cGjx9pBPqX9hPBDSSzunFC+/XidpGrziHPJXX3jMAlxg xRDy+PbLhkPi0VVESWCN38WErmGCCzU= Date: Tue, 26 Aug 2025 17:08:55 +0100 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH net-next v01 07/12] hinic3: Queue pair resource initialization To: Fan Gong , Zhu Yikai Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Andrew Lunn , linux-doc@vger.kernel.org, Jonathan Corbet , Bjorn Helgaas , luosifu , Xin Guo , Shen Chenyang , Zhou Shuai , Wu Like , Shi Jing , Meny Yossefi , Gur Stavi , Lee Trager , Michael Ellerman , Suman Ghosh , Przemek Kitszel , Christophe JAILLET References: Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Vadim Fedorenko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 26/08/2025 10:05, Fan Gong wrote: > Add Tx & Rx queue resources and functions for packet transmission > and reception. > > Co-developed-by: Xin Guo > Signed-off-by: Xin Guo > Co-developed-by: Zhu Yikai > Signed-off-by: Zhu Yikai > Signed-off-by: Fan Gong > --- [...] > struct hinic3_nic_db { > - u32 db_info; > - u32 pi_hi; > + __le32 db_info; > + __le32 pi_hi; > }; > > static inline void hinic3_write_db(struct hinic3_io_queue *queue, int cos, > @@ -84,15 +84,25 @@ static inline void hinic3_write_db(struct hinic3_io_queue *queue, int cos, > { > struct hinic3_nic_db db; > > - db.db_info = DB_INFO_SET(DB_SRC_TYPE, TYPE) | > - DB_INFO_SET(cflag, CFLAG) | > - DB_INFO_SET(cos, COS) | > - DB_INFO_SET(queue->q_id, QID); > - db.pi_hi = DB_PI_HIGH(pi); > + db.db_info = > + cpu_to_le32(DB_INFO_SET(DB_SRC_TYPE, TYPE) | > + DB_INFO_SET(cflag, CFLAG) | > + DB_INFO_SET(cos, COS) | > + DB_INFO_SET(queue->q_id, QID)); > + db.pi_hi = cpu_to_le32(DB_PI_HIGH(pi)); > > writeq(*((u64 *)&db), DB_ADDR(queue, pi)); > } [...] > @@ -66,8 +97,8 @@ static void rq_wqe_buf_set(struct hinic3_io_queue *rq, uint32_t wqe_idx, > struct hinic3_rq_wqe *rq_wqe; > > rq_wqe = get_q_element(&rq->wq.qpages, wqe_idx, NULL); > - rq_wqe->buf_hi_addr = upper_32_bits(dma_addr); > - rq_wqe->buf_lo_addr = lower_32_bits(dma_addr); > + rq_wqe->buf_hi_addr = cpu_to_le32(upper_32_bits(dma_addr)); > + rq_wqe->buf_lo_addr = cpu_to_le32(lower_32_bits(dma_addr)); > } [...] > @@ -27,21 +27,21 @@ > > /* RX Completion information that is provided by HW for a specific RX WQE */ > struct hinic3_rq_cqe { > - u32 status; > - u32 vlan_len; > - u32 offload_type; > - u32 rsvd3; > - u32 rsvd4; > - u32 rsvd5; > - u32 rsvd6; > - u32 pkt_info; > + __le32 status; > + __le32 vlan_len; > + __le32 offload_type; > + __le32 rsvd3; > + __le32 rsvd4; > + __le32 rsvd5; > + __le32 rsvd6; > + __le32 pkt_info; > }; > > struct hinic3_rq_wqe { > - u32 buf_hi_addr; > - u32 buf_lo_addr; > - u32 cqe_hi_addr; > - u32 cqe_lo_addr; > + __le32 buf_hi_addr; > + __le32 buf_lo_addr; > + __le32 cqe_hi_addr; > + __le32 cqe_lo_addr; > }; This patch has a lot of endianess-improvements changes which are not stated in the commit message. It's better to move them to a separate patch to avoid mixing things.