From: "Clément Léger" <cleger@rivosinc.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v3 02/17] riscv: sbi: add FWFT extension interface
Date: Fri, 14 Mar 2025 12:33:55 +0100 [thread overview]
Message-ID: <dad465de-e5da-4ebb-8395-ea9e181a6f57@rivosinc.com> (raw)
In-Reply-To: <20250313-5c22df0c08337905367fa125@orel>
On 13/03/2025 13:39, Andrew Jones wrote:
> On Mon, Mar 10, 2025 at 04:12:09PM +0100, Clément Léger wrote:
>> This SBI extensions enables supervisor mode to control feature that are
>> under M-mode control (For instance, Svadu menvcfg ADUE bit, Ssdbltrp
>> DTE, etc).
>>
>> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>> ---
>> arch/riscv/include/asm/sbi.h | 5 ++
>> arch/riscv/kernel/sbi.c | 97 ++++++++++++++++++++++++++++++++++++
>> 2 files changed, 102 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>> index bb077d0c912f..fc87c609c11a 100644
>> --- a/arch/riscv/include/asm/sbi.h
>> +++ b/arch/riscv/include/asm/sbi.h
>> @@ -503,6 +503,11 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
>> unsigned long asid);
>> long sbi_probe_extension(int ext);
>>
>> +int sbi_fwft_all_cpus_set(u32 feature, unsigned long value, unsigned long flags,
>> + bool revert_on_failure);
>> +int sbi_fwft_get(u32 feature, unsigned long *value);
>> +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags);
>> +
>> /* Check if current SBI specification version is 0.1 or not */
>> static inline int sbi_spec_is_0_1(void)
>> {
>> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
>> index 1989b8cade1b..256910db1307 100644
>> --- a/arch/riscv/kernel/sbi.c
>> +++ b/arch/riscv/kernel/sbi.c
>> @@ -299,6 +299,103 @@ static int __sbi_rfence_v02(int fid, const struct cpumask *cpu_mask,
>> return 0;
>> }
>>
>> +int sbi_fwft_get(u32 feature, unsigned long *value)
>> +{
>> + return -EOPNOTSUPP;
>> +}
>> +
>> +/**
>> + * sbi_fwft_set() - Set a feature on all online cpus
>
> copy+paste of description from sbi_fwft_all_cpus_set(). This function
> only sets the feature on the calling hart.
>
>> + * @feature: The feature to be set
>> + * @value: The feature value to be set
>> + * @flags: FWFT feature set flags
>> + *
>> + * Return: 0 on success, appropriate linux error code otherwise.
>> + */
>> +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags)
>> +{
>> + return -EOPNOTSUPP;
>> +}
>> +
>> +struct fwft_set_req {
>> + u32 feature;
>> + unsigned long value;
>> + unsigned long flags;
>> + cpumask_t mask;
>> +};
>> +
>> +static void cpu_sbi_fwft_set(void *arg)
>> +{
>> + struct fwft_set_req *req = arg;
>> +
>> + if (sbi_fwft_set(req->feature, req->value, req->flags))
>> + cpumask_clear_cpu(smp_processor_id(), &req->mask);
>> +}
>> +
>> +static int sbi_fwft_feature_local_set(u32 feature, unsigned long value,
>> + unsigned long flags,
>> + bool revert_on_fail)
>> +{
>> + int ret;
>> + unsigned long prev_value;
>> + cpumask_t tmp;
>> + struct fwft_set_req req = {
>> + .feature = feature,
>> + .value = value,
>> + .flags = flags,
>> + };
>> +
>> + cpumask_copy(&req.mask, cpu_online_mask);
>> +
>> + /* We can not revert if features are locked */
>> + if (revert_on_fail && flags & SBI_FWFT_SET_FLAG_LOCK)
>
> Should use () around the flags &. I thought checkpatch complained about
> that?
>
>> + return -EINVAL;
>> +
>> + /* Reset value is the same for all cpus, read it once. */
>
> How do we know we're reading the reset value? sbi_fwft_all_cpus_set() may
> be called multiple times on the same feature. And harts may have had
> sbi_fwft_set() called on them independently. I think we should drop the
> whole prev_value optimization.
That's actually used for revert_on_failure as well not only the
optimization.
>
>> + ret = sbi_fwft_get(feature, &prev_value);
>> + if (ret)
>> + return ret;
>> +
>> + /* Feature might already be set to the value we want */
>> + if (prev_value == value)
>> + return 0;
>> +
>> + on_each_cpu_mask(&req.mask, cpu_sbi_fwft_set, &req, 1);
>> + if (cpumask_equal(&req.mask, cpu_online_mask))
>> + return 0;
>> +
>> + pr_err("Failed to set feature %x for all online cpus, reverting\n",
>> + feature);
>
> nit: I'd let the above line stick out. We have 100 chars.
>
>> +
>> + req.value = prev_value;
>> + cpumask_copy(&tmp, &req.mask);
>> + on_each_cpu_mask(&req.mask, cpu_sbi_fwft_set, &req, 1);
>> + if (cpumask_equal(&req.mask, &tmp))
>> + return 0;
>
> I'm not sure we want the revert_on_fail support either. What happens when
> the revert fails and we return -EINVAL below? Also returning zero when
> revert succeeds means the caller won't know if we successfully set what
> we wanted or just successfully reverted.
So that might actually be needed for features that needs to be enabled
on all hart or not enabled at all. If we fail to enable all of them,
them the hart will be in some non coherent state between the harts.
The returned error code though is wrong and I'm not sure we would have a
way to gracefully handle revertion failure (except maybe panicking ?).
Thanks,
Clément
>
>> +
>> + return -EINVAL;
>> +}
>> +
>> +/**
>> + * sbi_fwft_all_cpus_set() - Set a feature on all online cpus
>> + * @feature: The feature to be set
>> + * @value: The feature value to be set
>> + * @flags: FWFT feature set flags
>> + * @revert_on_fail: true if feature value should be restored to it's orignal
>
> its original
>
>> + * value on failure.
>
> Line 'value' up under 'true'
>
>> + *
>> + * Return: 0 on success, appropriate linux error code otherwise.
>> + */
>> +int sbi_fwft_all_cpus_set(u32 feature, unsigned long value, unsigned long flags,
>> + bool revert_on_fail)
>> +{
>> + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT)
>> + return sbi_fwft_set(feature, value, flags);
>> +
>> + return sbi_fwft_feature_local_set(feature, value, flags,
>> + revert_on_fail);
>> +}
>> +
>> /**
>> * sbi_set_timer() - Program the timer for next timer event.
>> * @stime_value: The value after which next timer event should fire.
>> --
>> 2.47.2
>
> Thanks,
> drew
next prev parent reply other threads:[~2025-03-14 11:33 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 15:12 [PATCH v3 00/17] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-03-10 15:12 ` [PATCH v3 01/17] riscv: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-03-13 12:24 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 02/17] riscv: sbi: add FWFT extension interface Clément Léger
2025-03-13 12:39 ` Andrew Jones
2025-03-14 11:33 ` Clément Léger [this message]
2025-03-14 12:02 ` Andrew Jones
2025-03-14 12:23 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 03/17] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-03-13 12:44 ` Andrew Jones
2025-03-14 11:21 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 04/17] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-03-13 12:52 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 05/17] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-03-13 12:57 ` Andrew Jones
2025-03-14 11:44 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 06/17] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-03-13 13:06 ` Andrew Jones
2025-03-14 11:47 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 07/17] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-03-13 13:07 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 08/17] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-03-13 13:19 ` Andrew Jones
2025-03-14 11:49 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 09/17] riscv: misaligned: factorize trap handling Clément Léger
2025-03-10 15:12 ` [PATCH v3 10/17] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-03-10 15:12 ` [PATCH v3 11/17] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-03-10 15:12 ` [PATCH v3 12/17] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-03-10 15:12 ` [PATCH v3 13/17] selftests: riscv: add misaligned access testing Clément Léger
2025-03-10 15:12 ` [PATCH v3 14/17] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-03-13 14:27 ` Andrew Jones
2025-03-14 13:53 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 15/17] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-03-13 14:29 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 16/17] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-03-13 15:18 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 17/17] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-03-13 15:23 ` Andrew Jones
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