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([2001:818:ea56:d000:56e0:ceba:7da4:6673]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301ba17csm2615035f8f.58.2025.04.03.12.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 12:55:50 -0700 (PDT) Message-ID: Subject: Re: [PATCH 3/5] iio: adc: ad7380: move internal reference voltage to chip_info From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-iio@vger.kernel.org Cc: Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Corbet , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Date: Thu, 03 Apr 2025 19:56:08 +0100 In-Reply-To: <20250401-iio-ad7380-add-ad7389-4-v1-3-23d2568aa24f@baylibre.com> References: <20250401-iio-ad7380-add-ad7389-4-v1-0-23d2568aa24f@baylibre.com> <20250401-iio-ad7380-add-ad7389-4-v1-3-23d2568aa24f@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-04-01 at 17:50 -0500, David Lechner wrote: > Move the internal reference voltage value to the chip_info structure. >=20 > Before this change, only ADAQ chips could be internal_ref_only and only > non-ADAQ chips could be external_ref_only. Now, this restriction is > removed. >=20 > Signed-off-by: David Lechner > --- Reviewed-by: Nuno S=C3=A1 > =C2=A0drivers/iio/adc/ad7380.c | 22 ++++++++++++++++++++-- > =C2=A01 file changed, 20 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c > index > 18ed07275be8e031e54f3595f70afe47514084cd..e5cd11fd7b1083af2082985f2c0226b= 1a97d600f > 100644 > --- a/drivers/iio/adc/ad7380.c > +++ b/drivers/iio/adc/ad7380.c > @@ -120,6 +120,7 @@ struct ad7380_chip_info { > =C2=A0 unsigned int num_supplies; > =C2=A0 bool external_ref_only; > =C2=A0 bool internal_ref_only; > + unsigned int internal_ref_mv; > =C2=A0 const char * const *vcm_supplies; > =C2=A0 unsigned int num_vcm_supplies; > =C2=A0 const unsigned long *available_scan_masks; > @@ -609,6 +610,7 @@ static const struct ad7380_chip_info ad7380_chip_info= =3D { > =C2=A0 .num_simult_channels =3D 2, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .available_scan_masks =3D ad7380_2_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_timing, > =C2=A0 .max_conversion_rate_hz =3D 4 * MEGA, > @@ -622,6 +624,7 @@ static const struct ad7380_chip_info ad7381_chip_info= =3D { > =C2=A0 .num_simult_channels =3D 2, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .available_scan_masks =3D ad7380_2_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_timing, > =C2=A0 .max_conversion_rate_hz =3D 4 * MEGA, > @@ -637,6 +640,7 @@ static const struct ad7380_chip_info ad7383_chip_info= =3D { > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > =C2=A0 .vcm_supplies =3D ad7380_2_channel_vcm_supplies, > =C2=A0 .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .available_scan_masks =3D ad7380_2_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_timing, > =C2=A0 .max_conversion_rate_hz =3D 4 * MEGA, > @@ -652,6 +656,7 @@ static const struct ad7380_chip_info ad7384_chip_info= =3D { > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > =C2=A0 .vcm_supplies =3D ad7380_2_channel_vcm_supplies, > =C2=A0 .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .available_scan_masks =3D ad7380_2_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_timing, > =C2=A0 .max_conversion_rate_hz =3D 4 * MEGA, > @@ -665,6 +670,7 @@ static const struct ad7380_chip_info ad7386_chip_info= =3D { > =C2=A0 .num_simult_channels =3D 2, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .has_mux =3D true, > =C2=A0 .available_scan_masks =3D ad7380_2x2_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_timing, > @@ -679,6 +685,7 @@ static const struct ad7380_chip_info ad7387_chip_info= =3D { > =C2=A0 .num_simult_channels =3D 2, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .has_mux =3D true, > =C2=A0 .available_scan_masks =3D ad7380_2x2_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_timing, > @@ -693,6 +700,7 @@ static const struct ad7380_chip_info ad7388_chip_info= =3D { > =C2=A0 .num_simult_channels =3D 2, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .has_mux =3D true, > =C2=A0 .available_scan_masks =3D ad7380_2x2_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_timing, > @@ -721,6 +729,7 @@ static const struct ad7380_chip_info ad7381_4_chip_in= fo =3D { > =C2=A0 .num_simult_channels =3D 4, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .available_scan_masks =3D ad7380_4_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_4_timing, > =C2=A0 .max_conversion_rate_hz =3D 4 * MEGA, > @@ -734,6 +743,7 @@ static const struct ad7380_chip_info ad7383_4_chip_in= fo =3D { > =C2=A0 .num_simult_channels =3D 4, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .vcm_supplies =3D ad7380_4_channel_vcm_supplies, > =C2=A0 .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), > =C2=A0 .available_scan_masks =3D ad7380_4_channel_scan_masks, > @@ -749,6 +759,7 @@ static const struct ad7380_chip_info ad7384_4_chip_in= fo =3D { > =C2=A0 .num_simult_channels =3D 4, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .vcm_supplies =3D ad7380_4_channel_vcm_supplies, > =C2=A0 .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), > =C2=A0 .available_scan_masks =3D ad7380_4_channel_scan_masks, > @@ -764,6 +775,7 @@ static const struct ad7380_chip_info ad7386_4_chip_in= fo =3D { > =C2=A0 .num_simult_channels =3D 4, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .has_mux =3D true, > =C2=A0 .available_scan_masks =3D ad7380_2x4_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_4_timing, > @@ -778,6 +790,7 @@ static const struct ad7380_chip_info ad7387_4_chip_in= fo =3D { > =C2=A0 .num_simult_channels =3D 4, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .has_mux =3D true, > =C2=A0 .available_scan_masks =3D ad7380_2x4_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_4_timing, > @@ -792,6 +805,7 @@ static const struct ad7380_chip_info ad7388_4_chip_in= fo =3D { > =C2=A0 .num_simult_channels =3D 4, > =C2=A0 .supplies =3D ad7380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(ad7380_supplies), > + .internal_ref_mv =3D AD7380_INTERNAL_REF_MV, > =C2=A0 .has_mux =3D true, > =C2=A0 .available_scan_masks =3D ad7380_2x4_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_4_timing, > @@ -807,6 +821,7 @@ static const struct ad7380_chip_info adaq4370_4_chip_= info =3D { > =C2=A0 .supplies =3D adaq4380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), > =C2=A0 .internal_ref_only =3D true, > + .internal_ref_mv =3D ADAQ4380_INTERNAL_REF_MV, > =C2=A0 .has_hardware_gain =3D true, > =C2=A0 .available_scan_masks =3D ad7380_4_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_4_timing, > @@ -822,6 +837,7 @@ static const struct ad7380_chip_info adaq4380_4_chip_= info =3D { > =C2=A0 .supplies =3D adaq4380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), > =C2=A0 .internal_ref_only =3D true, > + .internal_ref_mv =3D ADAQ4380_INTERNAL_REF_MV, > =C2=A0 .has_hardware_gain =3D true, > =C2=A0 .available_scan_masks =3D ad7380_4_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_4_timing, > @@ -837,6 +853,7 @@ static const struct ad7380_chip_info adaq4381_4_chip_= info =3D { > =C2=A0 .supplies =3D adaq4380_supplies, > =C2=A0 .num_supplies =3D ARRAY_SIZE(adaq4380_supplies), > =C2=A0 .internal_ref_only =3D true, > + .internal_ref_mv =3D ADAQ4380_INTERNAL_REF_MV, > =C2=A0 .has_hardware_gain =3D true, > =C2=A0 .available_scan_masks =3D ad7380_4_channel_scan_masks, > =C2=A0 .timing_specs =3D &ad7380_4_timing, > @@ -1855,7 +1872,7 @@ static int ad7380_probe(struct spi_device *spi) > =C2=A0 * in bulk_get_enable(). > =C2=A0 */ > =C2=A0 > - st->vref_mv =3D ADAQ4380_INTERNAL_REF_MV; > + st->vref_mv =3D st->chip_info->internal_ref_mv; > =C2=A0 > =C2=A0 /* these chips don't have a register bit for this */ > =C2=A0 external_ref_en =3D false; > @@ -1880,7 +1897,8 @@ static int ad7380_probe(struct spi_device *spi) > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0 "Failed to get refio regulator\n"); > =C2=A0 > =C2=A0 external_ref_en =3D ret !=3D -ENODEV; > - st->vref_mv =3D external_ref_en ? ret / 1000 : > AD7380_INTERNAL_REF_MV; > + st->vref_mv =3D external_ref_en ? ret / 1000 > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : st->chip_info->internal_ref_mv; > =C2=A0 } > =C2=A0 > =C2=A0 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) >=20