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([2001:818:ea8e:7f00:2575:914:eedd:620e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9d8fba4sm146425175e9.4.2025.01.13.06.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 06:35:01 -0800 (PST) Message-ID: Subject: Re: [PATCH v2 1/2] iio: adc: ad4695: add offload-based oversampling support From: Nuno =?ISO-8859-1?Q?S=E1?= To: Trevor Gamblin , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , David Lechner , Lars-Peter Clausen , Jonathan Cameron , Jonathan Corbet Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Date: Mon, 13 Jan 2025 14:35:00 +0000 In-Reply-To: <20250109-ad4695-oversampling-v2-1-a46ac487082c@baylibre.com> References: <20250109-ad4695-oversampling-v2-0-a46ac487082c@baylibre.com> <20250109-ad4695-oversampling-v2-1-a46ac487082c@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-01-09 at 13:47 -0500, Trevor Gamblin wrote: > Add support for the ad4695's oversampling feature when SPI offload is > available. This allows the ad4695 to set oversampling ratios on a > per-channel basis, raising the effective-number-of-bits from 16 > (OSR =3D=3D 1) to 17 (4), 18 (16), or 19 (64) for a given sample (i.e. on= e > full cycle through the auto-sequencer). The logic for reading and > writing sampling frequency for a given channel is also adjusted based on > the current oversampling ratio. >=20 > The non-offload case isn't supported as there isn't a good way to > trigger the CNV pin in this mode. Support could be added in the future > if a use-case arises. >=20 > Signed-off-by: Trevor Gamblin > --- LGTM, just one small thing inline... Either way: Reviewed-by: Nuno Sa > =C2=A0drivers/iio/adc/ad4695.c | 333 ++++++++++++++++++++++++++++++++++++= ++++++---- > - > =C2=A01 file changed, 303 insertions(+), 30 deletions(-) >=20 > diff --git a/drivers/iio/adc/ad4695.c b/drivers/iio/adc/ad4695.c > index c8cd73d19e86..0caaeaa310ed 100644 > --- a/drivers/iio/adc/ad4695.c > +++ b/drivers/iio/adc/ad4695.c > @@ -79,6 +79,7 @@ > =C2=A0#define=C2=A0=C2=A0 AD4695_REG_CONFIG_IN_MODE =C2=A0 BIT(6) > =C2=A0#define=C2=A0=C2=A0 AD4695_REG_CONFIG_IN_PAIR =C2=A0 GENMASK(5, 4= ) > =C2=A0#define=C2=A0=C2=A0 AD4695_REG_CONFIG_IN_AINHIGHZ_EN =C2=A0 BIT(3) > +#define=C2=A0=C2=A0 AD4695_REG_CONFIG_IN_OSR_SET =C2=A0 GENMASK(1, 0) > =C2=A0#define AD4695_REG_UPPER_IN(n) (0x0040 | (2 * (n))) > =C2=A0#define AD4695_REG_LOWER_IN(n) (0x0060 | (2 * (n))) > =C2=A0#define AD4695_REG_HYST_IN(n) (0x0080 | (2 * (n))) > @@ -127,6 +128,7 @@ struct ad4695_channel_config { > =C2=A0 bool bipolar; > =C2=A0 enum ad4695_in_pair pin_pairing; > =C2=A0 unsigned int common_mode_mv; > + unsigned int oversampling_ratio; > =C2=A0}; > =C2=A0 ... > + > +static unsigned int ad4695_get_calibbias(int val, int val2, int osr) > +{ > + int val_calc, scale; > + > + switch (osr) { > + case 4: > + scale =3D 4; > + break; > + case 16: > + scale =3D 2; > + break; > + case 64: > + scale =3D 1; > + break; > + default: > + scale =3D 8; > + break; > + } > + > + val =3D clamp_t(int, val, S32_MIN / 8, S32_MAX / 8); > + Why not clamp()? AFAICS, we have the same type on all the arguments. I also think clamp*() macros got the same improvements as min/max() ones which mea= ns that using the ones with explicit casts are not so often needed anymore. My understanding is also that those macros are not that encouraged as it's eas= y to go wrong with the casts. - Nuno S=C3=A1 >=20