From: Ivan Vecera <ivecera@redhat.com>
To: Jiri Pirko <jiri@resnulli.us>
Cc: netdev@vger.kernel.org,
Prathosh Satish <Prathosh.Satish@microchip.com>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Simon Horman <horms@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Jason Gunthorpe <jgg@ziepe.ca>,
Shannon Nelson <shannon.nelson@amd.com>,
Dave Jiang <dave.jiang@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, Michal Schmidt <mschmidt@redhat.com>,
Petr Oros <poros@redhat.com>
Subject: Re: [PATCH net-next v12 09/14] dpll: zl3073x: Register DPLL devices and pins
Date: Wed, 2 Jul 2025 14:16:53 +0200 [thread overview]
Message-ID: <e55caefa-2ea9-4d31-be76-48cdfd481b5c@redhat.com> (raw)
In-Reply-To: <k2osi2mzfmudh7q3av5raxj33smbdjgnrmaqjx2evjaaloddb3@vublvfldqlnm>
On 02. 07. 25 2:02 odp., Jiri Pirko wrote:
> Wed, Jul 02, 2025 at 01:49:22PM +0200, ivecera@redhat.com wrote:
>>
>>
>> On 02. 07. 25 12:57 odp., Jiri Pirko wrote:
>>> Sun, Jun 29, 2025 at 09:10:44PM +0200, ivecera@redhat.com wrote:
>>>
>>> [...]
>>>
>>>> +/**
>>>> + * zl3073x_dpll_device_register - register DPLL device
>>>> + * @zldpll: pointer to zl3073x_dpll structure
>>>> + *
>>>> + * Registers given DPLL device into DPLL sub-system.
>>>> + *
>>>> + * Return: 0 on success, <0 on error
>>>> + */
>>>> +static int
>>>> +zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll)
>>>> +{
>>>> + struct zl3073x_dev *zldev = zldpll->dev;
>>>> + u8 dpll_mode_refsel;
>>>> + int rc;
>>>> +
>>>> + /* Read DPLL mode and forcibly selected reference */
>>>> + rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id),
>>>> + &dpll_mode_refsel);
>>>> + if (rc)
>>>> + return rc;
>>>> +
>>>> + /* Extract mode and selected input reference */
>>>> + zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE,
>>>> + dpll_mode_refsel);
>>>
>>> Who sets this?
>>
>> WDYM? refsel_mode register? If so this register is populated from
>> configuration stored in flash inside the chip. And the configuration
>> is prepared by vendor/OEM.
>
> Okay. Any plan to implement on-fly change of this?
Do you mean switching between automatic and manual mode?
If so? Yes, later, need to extend DPLL API to allow this.
Ivan
>>
>>>> + zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF,
>>>> + dpll_mode_refsel);
>>>> +
>>>> + zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id,
>>>> + THIS_MODULE);
>>>> + if (IS_ERR(zldpll->dpll_dev)) {
>>>> + rc = PTR_ERR(zldpll->dpll_dev);
>>>> + zldpll->dpll_dev = NULL;
>>>> +
>>>> + return rc;
>>>> + }
>>>> +
>>>> + rc = dpll_device_register(zldpll->dpll_dev,
>>>> + zl3073x_prop_dpll_type_get(zldev, zldpll->id),
>>>> + &zl3073x_dpll_device_ops, zldpll);
>>>> + if (rc) {
>>>> + dpll_device_put(zldpll->dpll_dev);
>>>> + zldpll->dpll_dev = NULL;
>>>> + }
>>>> +
>>>> + return rc;
>>>> +}
>>>
>>> [...]
>>>
>>
>
next prev parent reply other threads:[~2025-07-02 12:17 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-29 19:10 [PATCH net-next v12 00/14] Add Microchip ZL3073x support (part 1) Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 01/14] dt-bindings: dpll: Add DPLL device and pin Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 02/14] dt-bindings: dpll: Add support for Microchip Azurite chip family Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 03/14] dpll: Add basic Microchip ZL3073x support Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 04/14] dpll: zl3073x: Add support for devlink device info Ivan Vecera
2025-07-02 10:25 ` Jiri Pirko
2025-07-02 11:38 ` Ivan Vecera
2025-07-02 11:41 ` Jiri Pirko
2025-07-02 11:52 ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 05/14] dpll: zl3073x: Protect operations requiring multiple register accesses Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 06/14] dpll: zl3073x: Fetch invariants during probe Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 07/14] dpll: zl3073x: Add clock_id field Ivan Vecera
2025-07-02 10:31 ` Jiri Pirko
2025-07-02 11:43 ` Ivan Vecera
2025-07-02 12:01 ` Jiri Pirko
2025-07-02 14:51 ` Ivan Vecera
2025-07-03 10:09 ` Jiri Pirko
2025-07-03 10:45 ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 08/14] dpll: zl3073x: Read DPLL types and pin properties from system firmware Ivan Vecera
2025-07-02 10:41 ` Jiri Pirko
2025-07-02 11:47 ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 09/14] dpll: zl3073x: Register DPLL devices and pins Ivan Vecera
2025-07-02 10:57 ` Jiri Pirko
2025-07-02 11:49 ` Ivan Vecera
2025-07-02 12:02 ` Jiri Pirko
2025-07-02 12:16 ` Ivan Vecera [this message]
2025-07-02 14:12 ` Jiri Pirko
2025-06-29 19:10 ` [PATCH net-next v12 10/14] dpll: zl3073x: Implement input pin selection in manual mode Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 11/14] dpll: zl3073x: Add support to get/set priority on input pins Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 12/14] dpll: zl3073x: Implement input pin state setting in automatic mode Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 13/14] dpll: zl3073x: Add support to get/set frequency on input pins Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 14/14] dpll: zl3073x: Add support to get/set frequency on output pins Ivan Vecera
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e55caefa-2ea9-4d31-be76-48cdfd481b5c@redhat.com \
--to=ivecera@redhat.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=Prathosh.Satish@microchip.com \
--cc=arkadiusz.kubalewski@intel.com \
--cc=conor+dt@kernel.org \
--cc=corbet@lwn.net \
--cc=dave.jiang@intel.com \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=edumazet@google.com \
--cc=horms@kernel.org \
--cc=jgg@ziepe.ca \
--cc=jiri@resnulli.us \
--cc=krzk+dt@kernel.org \
--cc=kuba@kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mschmidt@redhat.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=poros@redhat.com \
--cc=robh@kernel.org \
--cc=shannon.nelson@amd.com \
--cc=vadim.fedorenko@linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).