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Mon, 26 Jan 2026 10:18:14 +0800 (CST) Received: from kwepemr100010.china.huawei.com (unknown [7.202.195.125]) by mail.maildlp.com (Postfix) with ESMTPS id 26C574056A; Mon, 26 Jan 2026 10:21:43 +0800 (CST) Received: from [10.67.120.103] (10.67.120.103) by kwepemr100010.china.huawei.com (7.202.195.125) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Mon, 26 Jan 2026 10:21:42 +0800 Message-ID: Date: Mon, 26 Jan 2026 10:21:42 +0800 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] arm64/sysreg: Add HDBSS related register information To: Leonardo Bras , Marc Zyngier CC: Tian Zheng , , , , , , , , , , , , , , , , , References: <20251121092342.3393318-1-zhengtian10@huawei.com> <20251121092342.3393318-2-zhengtian10@huawei.com> <86wm3iqlz8.wl-maz@kernel.org> From: Tian Zheng In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemr100010.china.huawei.com (7.202.195.125) On 1/22/2026 11:12 PM, Leonardo Bras wrote: > On Sat, Nov 22, 2025 at 12:40:27PM +0000, Marc Zyngier wrote: >> On Fri, 21 Nov 2025 09:23:38 +0000, >> Tian Zheng wrote: >>> >>> From: eillon >>> >>> The ARM architecture added the HDBSS feature and descriptions of >>> related registers (HDBSSBR/HDBSSPROD) in the DDI0601(ID121123) version, >>> add them to Linux. >>> >>> Signed-off-by: eillon >>> Signed-off-by: Tian Zheng >>> --- >>> arch/arm64/include/asm/esr.h | 2 ++ >>> arch/arm64/include/asm/kvm_arm.h | 1 + >>> arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ >>> 3 files changed, 31 insertions(+) >>> >>> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h >>> index e1deed824464..a6f3cf0b9b86 100644 >>> --- a/arch/arm64/include/asm/esr.h >>> +++ b/arch/arm64/include/asm/esr.h >>> @@ -159,6 +159,8 @@ >>> #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) >>> >>> /* ISS2 field definitions for Data Aborts */ >>> +#define ESR_ELx_HDBSSF_SHIFT (11) >>> +#define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT) >>> #define ESR_ELx_TnD_SHIFT (10) >>> #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) >>> #define ESR_ELx_TagAccess_SHIFT (9) >>> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h >>> index 1da290aeedce..b71122680a03 100644 >>> --- a/arch/arm64/include/asm/kvm_arm.h >>> +++ b/arch/arm64/include/asm/kvm_arm.h >>> @@ -124,6 +124,7 @@ >>> TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) >>> >>> /* VTCR_EL2 Registers bits */ >>> +#define VTCR_EL2_HDBSS (1UL << 45) >> >> I think it is time to convert VTCR_EL2 to the sysreg infrastructure >> instead of adding extra bits here. > > > Hi Marc, Tian, > > Marc, IIUC the above was implemented by > https://lore.kernel.org/all/20251210173024.561160-1-maz@kernel.org > > Which was recently applied to next, and it its way to mainstream. > > Tian, I think it's worth rebasing this patchset on top of the above. > Indeed, I've been following Marc's VTCR_EL2 patch and will rebase my changes on top of it. > BTW, I am working on using the feature enabled by this patchset on a new > optimization, so please include me on any new release. Sure, I'll make sure you're on the Cc list for the next revision. > > Thanks! > Leo >