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Mon, 26 Oct 2026 02:47:25 -0700 (PDT) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3eb40733sm12061897f8f.0.2026.10.26.02.47.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Oct 2026 02:47:24 -0700 (PDT) Message-ID: Date: Mon, 26 Oct 2026 09:47:23 +0000 X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/7] perf: arm_pmuv3: Add pmuv3_event_implemented() To: Amir Ayupov Cc: Will Deacon , Mark Rutland , Greg Kroah-Hartman , Jonathan Corbet , Mathieu Poirier , Randy Dunlap , Shuah Khan , Daniel Pereira , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Leo Yan , Suzuki K Poulose , Mike Leach , Alexander Shishkin References: <23ffe461b8d7b04f78118154dfc9ea1d2a14978a.1792989860.git.aaupov@fb.com> Content-Language: en-US From: James Clark In-Reply-To: <23ffe461b8d7b04f78118154dfc9ea1d2a14978a.1792989860.git.aaupov@fb.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 26/10/2026 05:48, Amir Ayupov wrote: > Drivers outside the PMU driver may need to know whether the local CPU's > PMU implements a common event before relying on it, for example a trace > unit driver checking that the PMU counts its external outputs as > TRCEXTOUTn. > > Add pmuv3_event_implemented() to the arm64 asm/arm_pmuv3.h, next to > read_pmceid0() and read_pmceid1(). It reads PMCEID0/1 on the calling CPU: > events 0x0000-0x003f are reported in bits [31:0], and the common events > from ARMV8_PMUV3_EXT_COMMON_EVENT_BASE in bits [63:32] from PMUv3p1. Move > ARMV8_PMUV3_EXT_COMMON_EVENT_BASE next to the event numbers in > linux/perf/arm_pmuv3.h so it is available without CONFIG_ARM_PMU. > > Suggested-by: James Clark > Assisted-by: Devmate:Opus-5.5 > Signed-off-by: Amir Ayupov > --- > arch/arm64/include/asm/arm_pmuv3.h | 19 +++++++++++++++++++ > include/linux/perf/arm_pmu.h | 1 - > include/linux/perf/arm_pmuv3.h | 3 +++ > 3 files changed, 22 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h > index 8a777dec8d88a..acd62c4f16743 100644 > --- a/arch/arm64/include/asm/arm_pmuv3.h > +++ b/arch/arm64/include/asm/arm_pmuv3.h > @@ -173,6 +173,25 @@ static inline bool pmuv3_implemented(int pmuver) > pmuver == ID_AA64DFR0_EL1_PMUVer_NI); > } > > +/* > + * Whether this CPU's PMU implements a common event, as reported by > + * PMCEID{0,1}: events 0x0000-0x003f in bits [31:0], and from PMUv3p1 events > + * 0x4000-0x403f in bits [63:32], which read as zero before PMUv3p1. > + * Must run on the CPU whose PMU is queried. > + */ > +static inline bool pmuv3_event_implemented(u16 event) > +{ > + bool ext = event >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; > + u16 id = ext ? event - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE : event; > + u64 pmceid; > + > + if (id >= 64 || !pmuv3_implemented(read_pmuver())) > + return false; > + > + pmceid = id < 32 ? read_pmceid0() : read_pmceid1(); > + return pmceid & BIT_ULL(id % 32 + (ext ? 32 : 0)); > +} > + > static inline bool is_pmuv3p4(int pmuver) > { > return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4; > diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h > index 02d2c7f45b527..792283d29d7b5 100644 > --- a/include/linux/perf/arm_pmu.h > +++ b/include/linux/perf/arm_pmu.h > @@ -124,7 +124,6 @@ struct arm_pmu { > u64 reg_brbidr; > #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 > DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); > -#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000 > DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); > > /* Only to be used by ACPI probing code */ > diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h > index d698efba28a27..c21f185a283d6 100644 > --- a/include/linux/perf/arm_pmuv3.h > +++ b/include/linux/perf/arm_pmuv3.h > @@ -78,6 +78,9 @@ > #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x003E > #define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x003F > > +/* Base of the common events reported in PMCEID{0,1}[63:32] from PMUv3p1 */ > +#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000 > + > /* Statistical profiling extension microarchitectural events */ > #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000 > #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001 Reviewed-by: James Clark