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AFNElJ+ix25hM1IeOxtkcHjWOxmDX/St22tqRSBVLsTCw4KmN0aTqM0TvjlqUU5MmIp7ysy5JN8GyprouNw=@vger.kernel.org X-Gm-Message-State: AOJu0YzxiKtLA/oiv5NOWGPHt/ac++1mnAUeSAOl1Pw3eYwgtOYYnNrG YZGdUi0C4HDMX/846fC+f2KtRGvV1esY5drCPOaDl2ivFzfDIEmUnTRyPFYP10Uon5xUxaqF/NN xPxUEeq8iN73b92galqx8AjwLAA== X-Received: from jatn7.prod.google.com ([2002:a05:6638:2647:b0:5d1:d9e5:ccbd]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6820:4c02:b0:69b:56e5:cd6b with SMTP id 006d021491bc7-69b7a9d2905mr1848851eaf.11.1778690350606; Wed, 13 May 2026 09:39:10 -0700 (PDT) Date: Wed, 13 May 2026 16:38:46 +0000 In-Reply-To: (message from James Clark on Mon, 11 May 2026 15:49:37 +0100) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Message-ID: Subject: Re: [PATCH v7 10/20] KVM: arm64: Context swap Partitioned PMU guest registers From: Colton Lewis To: James Clark Cc: alexandru.elisei@arm.com, pbonzini@redhat.com, corbet@lwn.net, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, mizhang@google.com, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mark.rutland@arm.com, shuah@kernel.org, gankulkarni@os.amperecomputing.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org Content-Type: text/plain; charset="UTF-8"; format=flowed; delsp=yes James Clark writes: > On 04/05/2026 10:18 pm, Colton Lewis wrote: >> Save and restore newly untrapped registers that can be directly >> accessed by the guest when the PMU is partitioned. >> * PMEVCNTRn_EL0 >> * PMCCNTR_EL0 >> * PMSELR_EL0 >> * PMCR_EL0 >> * PMCNTEN_EL0 >> * PMINTEN_EL1 >> If we know we are not partitioned (that is, using the emulated vPMU), >> then return immediately. A later patch will make this lazy so the >> context swaps don't happen unless the guest has accessed the PMU. >> PMEVTYPER is handled in a following patch since we must apply the KVM >> event filter before writing values to hardware. >> PMOVS guest counters are cleared to avoid the possibility of >> generating spurious interrupts when PMINTEN is written. This is fine >> because the virtual register for PMOVS is always the canonical value. >> Signed-off-by: Colton Lewis >> --- >> arch/arm/include/asm/arm_pmuv3.h | 4 + >> arch/arm64/kvm/arm.c | 2 + >> arch/arm64/kvm/pmu-direct.c | 169 +++++++++++++++++++++++++++++++ >> include/kvm/arm_pmu.h | 16 +++ >> 4 files changed, 191 insertions(+) >> diff --git a/arch/arm/include/asm/arm_pmuv3.h >> b/arch/arm/include/asm/arm_pmuv3.h >> index 42d62aa48d0a6..eebc89bdab7a1 100644 >> --- a/arch/arm/include/asm/arm_pmuv3.h >> +++ b/arch/arm/include/asm/arm_pmuv3.h >> @@ -235,6 +235,10 @@ static inline bool kvm_pmu_is_partitioned(struct >> arm_pmu *pmu) >> { >> return false; >> } >> +static inline u64 kvm_pmu_host_counter_mask(struct arm_pmu *pmu) >> +{ >> + return ~0; >> +} >> /* PMU Version in DFR Register */ >> #define ARMV8_PMU_DFR_VER_NI 0 >> diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c >> index 410ffd41fd73a..a942f2bc13fc4 100644 >> --- a/arch/arm64/kvm/arm.c >> +++ b/arch/arm64/kvm/arm.c >> @@ -680,6 +680,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int >> cpu) >> kvm_vcpu_load_vhe(vcpu); >> kvm_arch_vcpu_load_fp(vcpu); >> kvm_vcpu_pmu_restore_guest(vcpu); >> + kvm_pmu_load(vcpu); >> if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) >> kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); >> @@ -721,6 +722,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) >> kvm_timer_vcpu_put(vcpu); >> kvm_vgic_put(vcpu); >> kvm_vcpu_pmu_restore_host(vcpu); >> + kvm_pmu_put(vcpu); >> if (vcpu_has_nv(vcpu)) >> kvm_vcpu_put_hw_mmu(vcpu); >> kvm_arm_vmid_clear_active(); >> diff --git a/arch/arm64/kvm/pmu-direct.c b/arch/arm64/kvm/pmu-direct.c >> index 63ac72910e4b5..360d022d918d5 100644 >> --- a/arch/arm64/kvm/pmu-direct.c >> +++ b/arch/arm64/kvm/pmu-direct.c >> @@ -9,6 +9,7 @@ >> #include >> #include >> +#include >> /** >> * has_host_pmu_partition_support() - Determine if partitioning is >> possible >> @@ -98,3 +99,171 @@ u8 kvm_pmu_hpmn(struct kvm_vcpu *vcpu) >> return *host_data_ptr(nr_event_counters); >> } >> + >> +/** >> + * kvm_pmu_host_counter_mask() - Compute bitmask of host-reserved >> counters >> + * @pmu: Pointer to arm_pmu struct >> + * >> + * Compute the bitmask that selects the host-reserved counters in the >> + * {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers. These are the counters >> + * in HPMN..N >> + * >> + * Return: Bitmask >> + */ >> +u64 kvm_pmu_host_counter_mask(struct arm_pmu *pmu) >> +{ >> + u8 nr_counters = *host_data_ptr(nr_event_counters); >> + >> + if (kvm_pmu_is_partitioned(pmu)) >> + return GENMASK(nr_counters - 1, pmu->max_guest_counters); >> + >> + return ARMV8_PMU_CNT_MASK_ALL; >> +} >> + >> +/** >> + * kvm_pmu_guest_counter_mask() - Compute bitmask of guest-reserved >> counters >> + * @pmu: Pointer to arm_pmu struct >> + * >> + * Compute the bitmask that selects the guest-reserved counters in the >> + * {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers. These are the counters >> + * in 0..HPMN and the cycle and instruction counters. >> + * >> + * Return: Bitmask >> + */ >> +u64 kvm_pmu_guest_counter_mask(struct arm_pmu *pmu) >> +{ >> + if (kvm_pmu_is_partitioned(pmu)) >> + return ARMV8_PMU_CNT_MASK_C | GENMASK(pmu->max_guest_counters - 1, 0); >> + >> + return 0; >> +} > Minor nit: slightly inconsistent use of types. Returns a u64 but doesn't > use GENMASK_ULL and is also usually saved into a long when it's called. Will fix