* Re: [PATCH 0/4] lib/vsprintf: Remove atomic-unsafe support for printk format %pCr
From: Linus Torvalds @ 2018-06-01 11:00 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: baijiaju1990, Jonathan Corbet, Michael Turquette, sboyd,
Zhang Rui, Eduardo Valentin, Eric Anholt, Stefan Wahren,
Greg Kroah-Hartman, Sergey Senozhatsky, Petr Mladek,
Steven Rostedt, open list:DOCUMENTATION, linux-clk, Linux PM,
linux-serial, linux-arm-kernel, Linux-Renesas,
Linux Kernel Mailing List
In-Reply-To: <1527845302-12159-1-git-send-email-geert+renesas@glider.be>
On Fri, Jun 1, 2018 at 4:29 AM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
>
> This patch series:
> - Changes all existing users of "%pCr" to print the result of
> clk_get_rate() directly, which is safe as they all do this in task
> context only,
> - Removes support for the "%pCr" printk format.
Looks good to me.
What tree will this go through? The normal printk one? Just checking
that this doesn't end up falling through the cracks because nobody
knows who would take it...
Linus
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* Re: [PATCH 0/4] lib/vsprintf: Remove atomic-unsafe support for printk format %pCr
From: Andy Shevchenko @ 2018-06-01 11:04 UTC (permalink / raw)
To: Linus Torvalds
Cc: Geert Uytterhoeven, Jia-Ju Bai, Jonathan Corbet,
Michael Turquette, Stephen Boyd, Zhang Rui, Eduardo Valentin,
Eric Anholt, Stefan Wahren, Greg Kroah-Hartman,
Sergey Senozhatsky, Petr Mladek, Steven Rostedt,
open list:DOCUMENTATION, linux-clk, Linux PM, linux-serial,
linux-arm-kernel, Linux-Renesas, Linux Kernel Mailing List
In-Reply-To: <CA+55aFxHHSRnDbbNGq6SwNAwEt0EhX15n_pNqon3MzGYJgMJmA@mail.gmail.com>
On Fri, Jun 1, 2018 at 2:00 PM, Linus Torvalds
<torvalds@linux-foundation.org> wrote:
> On Fri, Jun 1, 2018 at 4:29 AM Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
>>
>> This patch series:
>> - Changes all existing users of "%pCr" to print the result of
>> clk_get_rate() directly, which is safe as they all do this in task
>> context only,
>> - Removes support for the "%pCr" printk format.
>
> Looks good to me.
>
> What tree will this go through? The normal printk one? Just checking
> that this doesn't end up falling through the cracks because nobody
> knows who would take it...
We discussed few month before with Petr that he would take care of the
patches against vsprintf.c.
I think this is the case here.
--
With Best Regards,
Andy Shevchenko
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* Re: [PATCH v2 2/7] PCI: dwc: Add MSI-X callbacks handler
From: Gustavo Pimentel @ 2018-06-01 11:05 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Gustavo Pimentel, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com,
jingoohan1@gmail.com, adouglas@cadence.com,
jesper.nilsson@axis.com
Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <758acd51-a36a-ae68-2e28-5ce184707dda@ti.com>
On 31/05/2018 11:49, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 17 May 2018 10:39 PM, Gustavo Pimentel wrote:
>> Change pcie_raise_irq() signature, namely the interrupt_num variable type
>> from u8 to u16 to accommodate 2048 maximum MSI-X interrupts.
>>
>> Add PCIe config space capability search function.
>>
>> Add sysfs set/get interface to allow the change of EP MSI-X maximum number.
>>
>> Add EP MSI-X callback for triggering interruptions.
>>
>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>> ---
>> Change v1->v2:
>> - Nothing changed, just to follow the patch set version.
>>
>> drivers/pci/dwc/pci-dra7xx.c | 2 +-
>> drivers/pci/dwc/pcie-artpec6.c | 2 +-
>> drivers/pci/dwc/pcie-designware-ep.c | 146 ++++++++++++++++++++++++++++++++-
>> drivers/pci/dwc/pcie-designware-plat.c | 4 +-
>> drivers/pci/dwc/pcie-designware.h | 14 +++-
>> 5 files changed, 163 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
>> index f688204..bdf948b 100644
>> --- a/drivers/pci/dwc/pci-dra7xx.c
>> +++ b/drivers/pci/dwc/pci-dra7xx.c
>> @@ -370,7 +370,7 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
>> }
>>
>> static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>> - enum pci_epc_irq_type type, u8 interrupt_num)
>> + enum pci_epc_irq_type type, u16 interrupt_num)
>> {
>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
>> diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
>> index 321b56c..9a2474b 100644
>> --- a/drivers/pci/dwc/pcie-artpec6.c
>> +++ b/drivers/pci/dwc/pcie-artpec6.c
>> @@ -428,7 +428,7 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
>> }
>>
>> static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>> - enum pci_epc_irq_type type, u8 interrupt_num)
>> + enum pci_epc_irq_type type, u16 interrupt_num)
>> {
>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> I think you should change pci_epc_raise_irq (in previous patch) and the above
> two changes in a separate patch. You can also include pcie-cadence-ep.c along
> with that.
Ok.
>>
>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
>> index 1eec441..e5f2377 100644
>> --- a/drivers/pci/dwc/pcie-designware-ep.c
>> +++ b/drivers/pci/dwc/pcie-designware-ep.c
>> @@ -40,6 +40,39 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
>> __dw_pcie_ep_reset_bar(pci, bar, 0);
>> }
>>
>> +u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
>> + u8 cap)
>> +{
>> + u8 cap_id, next_cap_ptr;
>> + u16 reg;
>> +
>> + reg = dw_pcie_readw_dbi(pci, cap_ptr);
>> + next_cap_ptr = (reg & 0xff00) >> 8;
>> + cap_id = (reg & 0x00ff);
>> +
>> + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
>> + return 0;
>> +
>> + if (cap_id == cap)
>> + return cap_ptr;
>> +
>> + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
>> +}
>> +
>> +u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
>> +{
>> + u8 next_cap_ptr;
>> + u16 reg;
>> +
>> + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
>> + next_cap_ptr = (reg & 0x00ff);
>> +
>> + if (!next_cap_ptr)
>> + return 0;
>> +
>> + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
>> +}
>> +
>> static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
>> struct pci_epf_header *hdr)
>> {
>> @@ -241,8 +274,47 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
>> return 0;
>> }
>>
>> +static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
>> +{
>> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> + u32 val, reg;
>> +
>> + if (!ep->msix_cap)
>> + return 0;
>
> return -EINVAL?
Definitely yes. Well spotted!
>
> or pci_epc_get_msix() will return 1.
>> +
>> + reg = ep->msix_cap + PCI_MSIX_FLAGS;
>> + val = dw_pcie_readw_dbi(pci, reg);
>> + if (!(val & PCI_MSIX_FLAGS_ENABLE))
>> + return -EINVAL;
>> +
>> + val &= PCI_MSIX_FLAGS_QSIZE;
>> +
>> + return val;
>> +}
>> +
>> +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
>> +{
>> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> + u32 val, reg;
>> +
>> + if (!ep->msix_cap)
>> + return 0;
>
> here too return -EINVAL.
A copy & paste bug :)
>> +
>> + reg = ep->msix_cap + PCI_MSIX_FLAGS;
>> + val = dw_pcie_readw_dbi(pci, reg);
>> + val &= ~PCI_MSIX_FLAGS_QSIZE;
>> + val |= interrupts;
>> + dw_pcie_dbi_ro_wr_en(pci);
>> + dw_pcie_writew_dbi(pci, reg, val);
>> + dw_pcie_dbi_ro_wr_dis(pci);
>> +
>> + return 0;
>> +}
>> +
>> static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
>> - enum pci_epc_irq_type type, u8 interrupt_num)
>> + enum pci_epc_irq_type type, u16 interrupt_num)
>> {
>> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>>
>> @@ -282,6 +354,8 @@ static const struct pci_epc_ops epc_ops = {
>> .unmap_addr = dw_pcie_ep_unmap_addr,
>> .set_msi = dw_pcie_ep_set_msi,
>> .get_msi = dw_pcie_ep_get_msi,
>> + .set_msix = dw_pcie_ep_set_msix,
>> + .get_msix = dw_pcie_ep_get_msix,
>> .raise_irq = dw_pcie_ep_raise_irq,
>> .start = dw_pcie_ep_start,
>> .stop = dw_pcie_ep_stop,
>> @@ -322,6 +396,64 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
>> return 0;
>> }
>>
>> +int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
>> + u16 interrupt_num)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> + struct pci_epc *epc = ep->epc;
>> + u16 tbl_offset, bir;
>> + u32 bar_addr_upper, bar_addr_lower;
>> + u32 msg_addr_upper, msg_addr_lower;
>> + u32 reg, msg_data, vec_ctrl;
>> + u64 tbl_addr, msg_addr, reg_u64;
>> + void __iomem *msix_tbl;
>> + int ret;
>> +
>> + reg = ep->msix_cap + PCI_MSIX_TABLE;
>> + tbl_offset = dw_pcie_readl_dbi(pci, reg);
>> + bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
>> + tbl_offset &= PCI_MSIX_TABLE_OFFSET;
>> + tbl_offset >>= 3;
>> +
>> + reg = PCI_BASE_ADDRESS_0 + (4 * bir);
>> + bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
>> + reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
>> + if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
>> + bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
>> + else
>> + bar_addr_upper = 0;
>
> You can skip else if you can use something like below>
> bar_addr_upper = 0
> bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
> reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
> if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
> bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
Sure.
>> +
>> + tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
>> + tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
>> + tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
>> +
>> + msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr, ep->addr_size);
>
> Why do you want to ioremap the entire address region?
Hum, this was from my initial tests...
I guess, I could limit it to the MSIX entry size (PCI_MSIX_ENTRY_SIZE).
>> + if (!msix_tbl)
>> + return -EINVAL;
>> +
>> + msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
>> + msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
>> + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
>> + msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
>> + vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
>> +
>> + if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)
>> + return -EPERM;
>> +
>> + iounmap(msix_tbl);
I noticed now this bug... The ioumap should be above the if.
>> +
>> + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msix_mem_phys, msg_addr,
>> + epc->mem->page_size);
>> + if (ret)
>> + return ret;
>> +
>> + writel(msg_data, ep->msix_mem);
>> +
>> + dw_pcie_ep_unmap_addr(epc, func_no, ep->msix_mem_phys);
>> +
>> + return 0;
>> +}
>> +
>> void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
>> {
>> struct pci_epc *epc = ep->epc;
>> @@ -329,6 +461,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
>> pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
>> epc->mem->page_size);
>>
>> + pci_epc_mem_free_addr(epc, ep->msix_mem_phys, ep->msix_mem,
>> + epc->mem->page_size);
>> +
>> pci_epc_mem_exit(epc);
>> }
>>
>> @@ -410,6 +545,15 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>> dev_err(dev, "Failed to reserve memory for MSI\n");
>> return -ENOMEM;
>> }
>> + ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
>
> msi_cap is not used anywhere else.
>
> Thanks
> Kishon
>
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* Re: [PATCH v2 4/7] PCI: dwc: Rework MSI callbacks handler
From: Gustavo Pimentel @ 2018-06-01 11:05 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Gustavo Pimentel, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, Joao.Pinto@synopsys.com,
jingoohan1@gmail.com, adouglas@cadence.com,
jesper.nilsson@axis.com
Cc: linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <ba3df388-9ec1-fe87-e575-0eddc5a565b7@ti.com>
On 31/05/2018 11:54, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 17 May 2018 10:39 PM, Gustavo Pimentel wrote:
>> Remove duplicate defines located on pcie-designware.h file already
>> available on /include/uapi/linux/pci-regs.h file.
>>
>> Add pci_epc_set_msi() maximum 32 interrupts validation.
>>
>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>> ---
>> Change v1->v2:
>> - Nothing changed, just to follow the patch set version.
>>
>> drivers/pci/dwc/pcie-designware-ep.c | 49 ++++++++++++++++++++++++------------
>> drivers/pci/dwc/pcie-designware.h | 11 --------
>> drivers/pci/endpoint/pci-epc-core.c | 3 ++-
>> 3 files changed, 35 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
>> index e5f2377..a4baa0d 100644
>> --- a/drivers/pci/dwc/pcie-designware-ep.c
>> +++ b/drivers/pci/dwc/pcie-designware-ep.c
>> @@ -246,29 +246,38 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
>>
>> static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
>> {
>> - int val;
>> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> + u32 val, reg;
>> +
>> + if (!ep->msi_cap)
>
> Ah, msi_cap is used here.
>> + return 0;
>
> return -EINVAL.
Another copy & paste issue :)
>>
>> - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
>> - if (!(val & MSI_CAP_MSI_EN_MASK))
>> + reg = ep->msi_cap + PCI_MSI_FLAGS;
>> + val = dw_pcie_readw_dbi(pci, reg);
>> + if (!(val & PCI_MSI_FLAGS_ENABLE))
>> return -EINVAL;
>>
>> - val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
>> + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
>> +
>> return val;
>> }
>>
>> -static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
>> +static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
>> {
>> - int val;
>> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> + u32 val, reg;
>>
>> - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
>> - val &= ~MSI_CAP_MMC_MASK;
>> - val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
>> + if (!ep->msi_cap)
>> + return 0;
>
> return -EINVAL.
Another copy & paste issue :)
>> +
>> + reg = ep->msi_cap + PCI_MSI_FLAGS;
>> + val = dw_pcie_readw_dbi(pci, reg);
>> + val &= ~PCI_MSI_FLAGS_QMASK;
>> + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
>> dw_pcie_dbi_ro_wr_en(pci);
>> - dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
>> + dw_pcie_writew_dbi(pci, reg, val);
>> dw_pcie_dbi_ro_wr_dis(pci);
>>
>> return 0;
>> @@ -367,21 +376,29 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> struct pci_epc *epc = ep->epc;
>> u16 msg_ctrl, msg_data;
>> - u32 msg_addr_lower, msg_addr_upper;
>> + u32 msg_addr_lower, msg_addr_upper, reg;
>> u64 msg_addr;
>> bool has_upper;
>> int ret;
>>
>> + if (!ep->msi_cap)
>> + return 0;
>
> return -EINVAL.
Another copy & paste issue :)
>
> Thanks
> Kishon
>
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* Re: [PATCH 0/4] lib/vsprintf: Remove atomic-unsafe support for printk format %pCr
From: Petr Mladek @ 2018-06-01 11:47 UTC (permalink / raw)
To: Linus Torvalds
Cc: Geert Uytterhoeven, baijiaju1990, Jonathan Corbet,
Michael Turquette, sboyd, Zhang Rui, Eduardo Valentin,
Eric Anholt, Stefan Wahren, Greg Kroah-Hartman,
Sergey Senozhatsky, Steven Rostedt, open list:DOCUMENTATION,
linux-clk, Linux PM, linux-serial, linux-arm-kernel,
Linux-Renesas, Linux Kernel Mailing List
In-Reply-To: <CA+55aFxHHSRnDbbNGq6SwNAwEt0EhX15n_pNqon3MzGYJgMJmA@mail.gmail.com>
On Fri 2018-06-01 06:00:47, Linus Torvalds wrote:
> On Fri, Jun 1, 2018 at 4:29 AM Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
> >
> > This patch series:
> > - Changes all existing users of "%pCr" to print the result of
> > clk_get_rate() directly, which is safe as they all do this in task
> > context only,
> > - Removes support for the "%pCr" printk format.
>
> Looks good to me.
>
> What tree will this go through? The normal printk one? Just checking
> that this doesn't end up falling through the cracks because nobody
> knows who would take it...
I will take it via printk.git. There already is bunch of vsprintf
changes for-4.18.
Best Regards,
Petr
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^ permalink raw reply
* Re: [PATCH 3/3] drm/amdgpu: Add documentation for PRIME related code
From: Alex Deucher @ 2018-06-01 12:58 UTC (permalink / raw)
To: Michel Dänzer
Cc: amd-gfx list, linux-doc, LKML, Maling list - DRI developers,
Jonathan Corbet
In-Reply-To: <20180531161708.5894-3-michel@daenzer.net>
On Thu, May 31, 2018 at 12:17 PM, Michel Dänzer <michel@daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
>
> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> Documentation/gpu/amdgpu.rst | 14 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 119 ++++++++++++++++++++++
> 2 files changed, 133 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
> index 41a14e4aa4ac..f557866f6788 100644
> --- a/Documentation/gpu/amdgpu.rst
> +++ b/Documentation/gpu/amdgpu.rst
> @@ -4,3 +4,17 @@
>
> The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
> Next (GCN) architecture.
> +
> +Core Driver Infrastructure
> +==========================
> +
> +This section covers core driver infrastructure.
> +
> +PRIME Buffer Sharing
> +--------------------
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> + :doc: PRIME Buffer Sharing
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> + :internal:
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> index 4683626b065f..d1f05489595b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> @@ -23,6 +23,14 @@
> *
> * Authors: Alex Deucher
> */
> +
> +/**
> + * DOC: PRIME Buffer Sharing
> + *
> + * The following callback implementations are used for :ref:`sharing GEM buffer
> + * objects between different devices via PRIME <prime_buffer_sharing>`.
> + */
> +
> #include <drm/drmP.h>
>
> #include "amdgpu.h"
> @@ -32,6 +40,14 @@
>
> static const struct dma_buf_ops amdgpu_dmabuf_ops;
>
> +/**
> + * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table
> + * implementation
> + * @obj: GEM buffer object
> + *
> + * Returns:
> + * A scatter/gather table for the pinned pages of the buffer object's memory.
> + */
> struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
> {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
> @@ -40,6 +56,15 @@ struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
> return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
> }
>
> +/**
> + * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation
> + * @obj: GEM buffer object
> + *
> + * Sets up an in-kernel virtual mapping of the buffer object's memory.
> + *
> + * Returns:
> + * The virtual address of the mapping or an error pointer.
> + */
> void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
> {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
> @@ -53,6 +78,13 @@ void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
> return bo->dma_buf_vmap.virtual;
> }
>
> +/**
> + * amdgpu_gem_prime_vunmap - &dma_buf_ops.vunmap implementation
> + * @obj: GEM buffer object
> + * @vaddr: virtual address (unused)
> + *
> + * Tears down the in-kernel virtual mapping of the buffer object's memory.
> + */
> void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
> {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
> @@ -60,6 +92,17 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
> ttm_bo_kunmap(&bo->dma_buf_vmap);
> }
>
> +/**
> + * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
> + * @obj: GEM buffer object
> + * @vma: virtual memory area
> + *
> + * Sets up a userspace mapping of the buffer object's memory in the given
> + * virtual memory area.
> + *
> + * Returns:
> + * 0 on success or negative error code.
> + */
> int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
> {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
> @@ -94,6 +137,19 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma
> return ret;
> }
>
> +/**
> + * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table
> + * implementation
> + * @dev: DRM device
> + * @attach: DMA-buf attachment
> + * @sg: Scatter/gather table
> + *
> + * Import shared DMA buffer memory exported by another device.
> + *
> + * Returns:
> + * A new GEM buffer object of the given DRM device, representing the memory
> + * described by the given DMA-buf attachment and scatter/gather table.
> + */
> struct drm_gem_object *
> amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
> struct dma_buf_attachment *attach,
> @@ -132,6 +188,19 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
> return ERR_PTR(ret);
> }
>
> +/**
> + * amdgpu_gem_map_attach - &dma_buf_ops.attach implementation
> + * @dma_buf: shared DMA buffer
> + * @target_dev: target device
> + * @attach: DMA-buf attachment
> + *
> + * Makes sure that the shared DMA buffer can be accessed by the target device.
> + * For now, simply pins it to the GTT domain, where it should be accessible by
> + * all DMA devices.
> + *
> + * Returns:
> + * 0 on success or negative error code.
> + */
> static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
> struct device *target_dev,
> struct dma_buf_attachment *attach)
> @@ -181,6 +250,14 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
> return r;
> }
>
> +/**
> + * amdgpu_gem_map_detach - &dma_buf_ops.detach implementation
> + * @dma_buf: shared DMA buffer
> + * @attach: DMA-buf attachment
> + *
> + * This is called when a shared DMA buffer no longer needs to be accessible by
> + * the other device. For now, simply unpins the buffer from GTT.
> + */
> static void amdgpu_gem_map_detach(struct dma_buf *dma_buf,
> struct dma_buf_attachment *attach)
> {
> @@ -202,6 +279,13 @@ static void amdgpu_gem_map_detach(struct dma_buf *dma_buf,
> drm_gem_map_detach(dma_buf, attach);
> }
>
> +/**
> + * amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation
> + * @obj: GEM buffer object
> + *
> + * Returns:
> + * The buffer object's reservation object.
> + */
> struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
> {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
> @@ -209,6 +293,18 @@ struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
> return bo->tbo.resv;
> }
>
> +/**
> + * amdgpu_gem_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
> + * @dma_buf: shared DMA buffer
> + * @direction: direction of DMA transfer
> + *
> + * This is called before CPU access to the shared DMA buffer's memory. If it's
> + * a read access, the buffer is moved to the GTT domain if possible, for optimal
> + * CPU read performance.
> + *
> + * Returns:
> + * 0 on success or negative error code.
> + */
> static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf,
> enum dma_data_direction direction)
> {
> @@ -253,6 +349,18 @@ static const struct dma_buf_ops amdgpu_dmabuf_ops = {
> .vunmap = drm_gem_dmabuf_vunmap,
> };
>
> +/**
> + * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
> + * @dev: DRM device
> + * @gobj: GEM buffer object
> + * @flags: flags like DRM_CLOEXEC and DRM_RDWR
> + *
> + * The main work is done by the &drm_gem_prime_export helper, which in turn
> + * uses &amdgpu_gem_prime_res_obj.
> + *
> + * Returns:
> + * Shared DMA buffer representing the GEM buffer object from the given device.
> + */
> struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
> struct drm_gem_object *gobj,
> int flags)
> @@ -273,6 +381,17 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
> return buf;
> }
>
> +/**
> + * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
> + * @dev: DRM device
> + * @dma_buf: Shared DMA buffer
> + *
> + * The main work is done by the &drm_gem_prime_import helper, which in turn
> + * uses &amdgpu_gem_prime_import_sg_table.
> + *
> + * Returns:
> + * GEM buffer object representing the shared DMA buffer for the given device.
> + */
> struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
> struct dma_buf *dma_buf)
> {
> --
> 2.17.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply
* Re: [PATCH 3/3] drm/amdgpu: Add documentation for PRIME related code
From: Michel Dänzer @ 2018-06-01 13:40 UTC (permalink / raw)
To: Alex Deucher
Cc: Maling list - DRI developers, Jonathan Corbet, LKML, amd-gfx list,
linux-doc
In-Reply-To: <CADnq5_O5-m_=xqszq41eOAVaLTytHUHmtDaSc1MeEorZML6T5g@mail.gmail.com>
On 2018-06-01 02:58 PM, Alex Deucher wrote:
> On Thu, May 31, 2018 at 12:17 PM, Michel Dänzer <michel@daenzer.net> wrote:
>> From: Michel Dänzer <michel.daenzer@amd.com>
>>
>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
>
> Series is:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Thanks. Is it okay to merge all of these via the amdgpu tree, or should
I wait for an ack from Jon and/or core DRM maintainers for that?
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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* Re: [PATCH 3/3] drm/amdgpu: Add documentation for PRIME related code
From: Alex Deucher @ 2018-06-01 13:44 UTC (permalink / raw)
To: Michel Dänzer
Cc: Maling list - DRI developers, Jonathan Corbet, LKML, amd-gfx list,
linux-doc
In-Reply-To: <b458561f-b4e5-58bb-eee0-e3451312ae41@daenzer.net>
On Fri, Jun 1, 2018 at 9:40 AM, Michel Dänzer <michel@daenzer.net> wrote:
> On 2018-06-01 02:58 PM, Alex Deucher wrote:
>> On Thu, May 31, 2018 at 12:17 PM, Michel Dänzer <michel@daenzer.net> wrote:
>>> From: Michel Dänzer <michel.daenzer@amd.com>
>>>
>>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
>>
>> Series is:
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> Thanks. Is it okay to merge all of these via the amdgpu tree, or should
> I wait for an ack from Jon and/or core DRM maintainers for that?
GPU documentation usually goes through the drm trees. You might want
to push patch 1 (drm_mm.rst fix) via drm_misc, but the rest are can go
in via the amdgpu tree since they are amdgpu specific.
Alex
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* Re: [PATCH 3/3] drm/amdgpu: Add documentation for PRIME related code
From: Michel Dänzer @ 2018-06-01 13:56 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx list, linux-doc, LKML, Maling list - DRI developers,
Jonathan Corbet
In-Reply-To: <CADnq5_M-kS58ScgOBVQG7Mxxepae9b9gqUdMdFgaPaaxQ4NkjQ@mail.gmail.com>
On 2018-06-01 03:44 PM, Alex Deucher wrote:
> On Fri, Jun 1, 2018 at 9:40 AM, Michel Dänzer <michel@daenzer.net> wrote:
>> On 2018-06-01 02:58 PM, Alex Deucher wrote:
>>> On Thu, May 31, 2018 at 12:17 PM, Michel Dänzer <michel@daenzer.net> wrote:
>>>> From: Michel Dänzer <michel.daenzer@amd.com>
>>>>
>>>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
>>>
>>> Series is:
>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>
>> Thanks. Is it okay to merge all of these via the amdgpu tree, or should
>> I wait for an ack from Jon and/or core DRM maintainers for that?
>
> GPU documentation usually goes through the drm trees. You might want
> to push patch 1 (drm_mm.rst fix) via drm_misc, but the rest are can go
> in via the amdgpu tree since they are amdgpu specific.
I'd prefer merging all three patches together, since without patch 1,
patch 3 generates the warning below while generating documentation, and
the reference to the PRIME Buffer Sharing section doesn't work.
.../linux/Documentation/gpu/amdgpu.rst:2: WARNING: undefined label:
prime_buffer_sharing (if the link has no caption the label must precede
a section header)
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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^ permalink raw reply
* Ltd.
From: Skotwb @ 2018-06-01 14:09 UTC (permalink / raw)
To: dongfang100_1, linux-doc, wph177
[-- Attachment #1: Type: text/plain, Size: 78 bytes --]
山东凌邦天翔电子科技（北京凌邦山东营销中心）优势。在这一步中，企业通过研究以上
[-- Attachment #2: 人本集团设备采购部.gif --]
[-- Type: image/gif, Size: 4154 bytes --]
^ permalink raw reply
* Re: [PATCH 3/3] drm/amdgpu: Add documentation for PRIME related code
From: Jonathan Corbet @ 2018-06-01 14:12 UTC (permalink / raw)
To: Michel Dänzer
Cc: Alex Deucher, Maling list - DRI developers, LKML, amd-gfx list,
linux-doc
In-Reply-To: <b458561f-b4e5-58bb-eee0-e3451312ae41@daenzer.net>
On Fri, 1 Jun 2018 15:40:44 +0200
Michel Dänzer <michel@daenzer.net> wrote:
> Thanks. Is it okay to merge all of these via the amdgpu tree, or should
> I wait for an ack from Jon and/or core DRM maintainers for that?
I've been assuming they would go through a DRM tree, no need to wait for
me.
Thanks,
jon
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* [PATCH v3 04/10] PCI: dwc: Rework MSI callbacks handler
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Remove duplicate defines located on pcie-designware.h file already
available on /include/uapi/linux/pci-regs.h file.
Add pci_epc_set_msi() maximum 32 interrupts validation.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Replaced wrong return value 0 to -EINVAL.
drivers/pci/dwc/pcie-designware-ep.c | 49 ++++++++++++++++++++++++------------
drivers/pci/dwc/pcie-designware.h | 11 --------
drivers/pci/endpoint/pci-epc-core.c | 3 ++-
3 files changed, 35 insertions(+), 28 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index c7f2fa9..3ba7059 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -246,29 +246,38 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
{
- int val;
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msi_cap)
+ return -EINVAL;
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
- if (!(val & MSI_CAP_MSI_EN_MASK))
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSI_FLAGS_ENABLE))
return -EINVAL;
- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
+ val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
+
return val;
}
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
{
- int val;
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
- val &= ~MSI_CAP_MMC_MASK;
- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
+ if (!ep->msi_cap)
+ return -EINVAL;
+
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSI_FLAGS_QMASK;
+ val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
+ dw_pcie_writew_dbi(pci, reg, val);
dw_pcie_dbi_ro_wr_dis(pci);
return 0;
@@ -367,21 +376,29 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct pci_epc *epc = ep->epc;
u16 msg_ctrl, msg_data;
- u32 msg_addr_lower, msg_addr_upper;
+ u32 msg_addr_lower, msg_addr_upper, reg;
u64 msg_addr;
bool has_upper;
int ret;
+ if (!ep->msi_cap)
+ return -EINVAL;
+
/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
- msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
+ msg_ctrl = dw_pcie_readw_dbi(pci, reg);
has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
- msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
+ reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
+ msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
if (has_upper) {
- msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
- msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
+ reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
+ msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
+ reg = ep->msi_cap + PCI_MSI_DATA_64;
+ msg_data = dw_pcie_readw_dbi(pci, reg);
} else {
msg_addr_upper = 0;
- msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
+ reg = ep->msi_cap + PCI_MSI_DATA_32;
+ msg_data = dw_pcie_readw_dbi(pci, reg);
}
msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index b22c5bb..a0ab12f 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -96,17 +96,6 @@
#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
((0x3 << 20) | ((region) << 9) | (0x1 << 8))
-#define MSI_MESSAGE_CONTROL 0x52
-#define MSI_CAP_MMC_SHIFT 1
-#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
-#define MSI_CAP_MME_SHIFT 4
-#define MSI_CAP_MSI_EN_MASK 0x1
-#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
-#define MSI_MESSAGE_ADDR_L32 0x54
-#define MSI_MESSAGE_ADDR_U32 0x58
-#define MSI_MESSAGE_DATA_32 0x58
-#define MSI_MESSAGE_DATA_64 0x5C
-
#define MAX_MSI_IRQS 256
#define MAX_MSI_IRQS_PER_CTRL 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index c72e656..094dcc3 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -201,7 +201,8 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
u8 encode_int;
unsigned long flags;
- if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
+ if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
+ interrupts > 32)
return -EINVAL;
if (!epc->ops->set_msi)
--
2.7.4
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* [PATCH v3 03/10] PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Change {cdns, dra7xx, artpec6}_pcie_ep_raise_irq() and pci_epc_raise_irq()
signature, namely the interrupt_num variable type from u8 to u16 to
accommodate 2048 maximum MSI-X interrupts.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Acked-by: Alan Douglas <adouglas@cadence.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Move into here the pci_epc_raise_irq() signature change from patch
file #1.
- Move into here the {dra7xx, artpec6}_pcie_ep_raise_irq() signature
changes from patch file #2.
drivers/pci/cadence/pcie-cadence-ep.c | 3 ++-
drivers/pci/dwc/pci-dra7xx.c | 2 +-
drivers/pci/dwc/pcie-artpec6.c | 2 +-
drivers/pci/endpoint/pci-epc-core.c | 8 ++++----
include/linux/pci-epc.h | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/cadence/pcie-cadence-ep.c b/drivers/pci/cadence/pcie-cadence-ep.c
index 3d8283e..6b713ca 100644
--- a/drivers/pci/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/cadence/pcie-cadence-ep.c
@@ -363,7 +363,8 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
}
static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
- enum pci_epc_irq_type type, u8 interrupt_num)
+ enum pci_epc_irq_type type,
+ u16 interrupt_num)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index f688204..bdf948b 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -370,7 +370,7 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
}
static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u8 interrupt_num)
+ enum pci_epc_irq_type type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 321b56c..9a2474b 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -428,7 +428,7 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
}
static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u8 interrupt_num)
+ enum pci_epc_irq_type type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 7d77bd0..c72e656 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -131,13 +131,13 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
* pci_epc_raise_irq() - interrupt the host system
* @epc: the EPC device which has to interrupt the host
* @func_no: the endpoint function number in the EPC device
- * @type: specify the type of interrupt; legacy or MSI
- * @interrupt_num: the MSI interrupt number
+ * @type: specify the type of interrupt; legacy, MSI or MSI-X
+ * @interrupt_num: the MSI or MSI-X interrupt number
*
- * Invoke to raise an MSI or legacy interrupt
+ * Invoke to raise an legacy, MSI or MSI-X interrupt
*/
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
- enum pci_epc_irq_type type, u8 interrupt_num)
+ enum pci_epc_irq_type type, u16 interrupt_num)
{
int ret;
unsigned long flags;
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 89f079f..bb2395b 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -35,7 +35,7 @@ enum pci_epc_irq_type {
* MSI-X capability register
* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
* from the MSI-X capability register
- * @raise_irq: ops to raise a legacy or MSI interrupt
+ * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
* @start: ops to start the PCI link
* @stop: ops to stop the PCI link
* @owner: the module owner containing the ops
@@ -56,7 +56,7 @@ struct pci_epc_ops {
int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
int (*get_msix)(struct pci_epc *epc, u8 func_no);
int (*raise_irq)(struct pci_epc *epc, u8 func_no,
- enum pci_epc_irq_type type, u8 interrupt_num);
+ enum pci_epc_irq_type type, u16 interrupt_num);
int (*start)(struct pci_epc *epc);
void (*stop)(struct pci_epc *epc);
struct module *owner;
@@ -154,7 +154,7 @@ int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
- enum pci_epc_irq_type type, u8 interrupt_num);
+ enum pci_epc_irq_type type, u16 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
struct pci_epc *pci_epc_get(const char *epc_name);
--
2.7.4
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* [PATCH v3 02/10] PCI: dwc: Add MSI-X callbacks handler
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Add PCIe config space capability search function.
Add sysfs set/get interface to allow the change of EP MSI-X maximum number.
Add EP MSI-X callback for triggering interruptions.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Moved dra7xx_pcie_raise_irq() signature change to patch file #3.
- Moved artpec6_pcie_raise_irq() signature change to patch file #3.
- Replaced wrong return value 0 to -EINVAL.
- Removed an else if by code refactoring.
- Reduced the size of ioremap_nocache mapping from ep->addr_size to
PCI_MSIX_ENTRY_SIZE.
- Fixed a small bug. If the MSI-X vector bit has been set, the function
would return without executing the proper unmap.
drivers/pci/dwc/pcie-designware-ep.c | 146 ++++++++++++++++++++++++++++++++-
drivers/pci/dwc/pcie-designware-plat.c | 4 +-
drivers/pci/dwc/pcie-designware.h | 14 +++-
3 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index 1eec441..c7f2fa9 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -40,6 +40,39 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
__dw_pcie_ep_reset_bar(pci, bar, 0);
}
+u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
+ u8 cap)
+{
+ u8 cap_id, next_cap_ptr;
+ u16 reg;
+
+ reg = dw_pcie_readw_dbi(pci, cap_ptr);
+ next_cap_ptr = (reg & 0xff00) >> 8;
+ cap_id = (reg & 0x00ff);
+
+ if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
+ return 0;
+
+ if (cap_id == cap)
+ return cap_ptr;
+
+ return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
+}
+
+u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
+{
+ u8 next_cap_ptr;
+ u16 reg;
+
+ reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
+ next_cap_ptr = (reg & 0x00ff);
+
+ if (!next_cap_ptr)
+ return 0;
+
+ return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
+}
+
static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
struct pci_epf_header *hdr)
{
@@ -241,8 +274,47 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
return 0;
}
+static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msix_cap)
+ return -EINVAL;
+
+ reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSIX_FLAGS_ENABLE))
+ return -EINVAL;
+
+ val &= PCI_MSIX_FLAGS_QSIZE;
+
+ return val;
+}
+
+static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
+{
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msix_cap)
+ return -EINVAL;
+
+ reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSIX_FLAGS_QSIZE;
+ val |= interrupts;
+ dw_pcie_dbi_ro_wr_en(pci);
+ dw_pcie_writew_dbi(pci, reg, val);
+ dw_pcie_dbi_ro_wr_dis(pci);
+
+ return 0;
+}
+
static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
- enum pci_epc_irq_type type, u8 interrupt_num)
+ enum pci_epc_irq_type type, u16 interrupt_num)
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
@@ -282,6 +354,8 @@ static const struct pci_epc_ops epc_ops = {
.unmap_addr = dw_pcie_ep_unmap_addr,
.set_msi = dw_pcie_ep_set_msi,
.get_msi = dw_pcie_ep_get_msi,
+ .set_msix = dw_pcie_ep_set_msix,
+ .get_msix = dw_pcie_ep_get_msix,
.raise_irq = dw_pcie_ep_raise_irq,
.start = dw_pcie_ep_start,
.stop = dw_pcie_ep_stop,
@@ -322,6 +396,64 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
+ u16 interrupt_num)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct pci_epc *epc = ep->epc;
+ u16 tbl_offset, bir;
+ u32 bar_addr_upper, bar_addr_lower;
+ u32 msg_addr_upper, msg_addr_lower;
+ u32 reg, msg_data, vec_ctrl;
+ u64 tbl_addr, msg_addr, reg_u64;
+ void __iomem *msix_tbl;
+ int ret;
+
+ reg = ep->msix_cap + PCI_MSIX_TABLE;
+ tbl_offset = dw_pcie_readl_dbi(pci, reg);
+ bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
+ tbl_offset &= PCI_MSIX_TABLE_OFFSET;
+ tbl_offset >>= 3;
+
+ reg = PCI_BASE_ADDRESS_0 + (4 * bir);
+ bar_addr_upper = 0;
+ bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
+ reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
+ if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
+ bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
+
+ tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
+ tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
+ tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
+
+ msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr,
+ PCI_MSIX_ENTRY_SIZE);
+ if (!msix_tbl)
+ return -EINVAL;
+
+ msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
+ msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
+ msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+ msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
+ vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
+
+ iounmap(msix_tbl);
+
+ if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)
+ return -EPERM;
+
+ ret = dw_pcie_ep_map_addr(epc, func_no, ep->msix_mem_phys, msg_addr,
+ epc->mem->page_size);
+ if (ret)
+ return ret;
+
+ writel(msg_data, ep->msix_mem);
+
+ dw_pcie_ep_unmap_addr(epc, func_no, ep->msix_mem_phys);
+
+ return 0;
+}
+
void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{
struct pci_epc *epc = ep->epc;
@@ -329,6 +461,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
epc->mem->page_size);
+ pci_epc_mem_free_addr(epc, ep->msix_mem_phys, ep->msix_mem,
+ epc->mem->page_size);
+
pci_epc_mem_exit(epc);
}
@@ -410,6 +545,15 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
dev_err(dev, "Failed to reserve memory for MSI\n");
return -ENOMEM;
}
+ ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
+
+ ep->msix_mem = pci_epc_mem_alloc_addr(epc, &ep->msix_mem_phys,
+ epc->mem->page_size);
+ if (!ep->msix_mem) {
+ dev_err(dev, "Failed to reserve memory for MSI-X\n");
+ return -ENOMEM;
+ }
+ ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER;
EPC_FEATURE_SET_BAR(epc->features, BAR_0);
diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index 5937fed..654dcb5 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -78,7 +78,7 @@ static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
enum pci_epc_irq_type type,
- u8 interrupt_num)
+ u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -88,6 +88,8 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
return -EINVAL;
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+ case PCI_EPC_IRQ_MSIX:
+ return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
default:
dev_err(pci->dev, "UNKNOWN IRQ type\n");
}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index bee4e25..b22c5bb 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -191,7 +191,7 @@ enum dw_pcie_as_type {
struct dw_pcie_ep_ops {
void (*ep_init)(struct dw_pcie_ep *ep);
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u8 interrupt_num);
+ enum pci_epc_irq_type type, u16 interrupt_num);
};
struct dw_pcie_ep {
@@ -208,6 +208,10 @@ struct dw_pcie_ep {
u32 num_ob_windows;
void __iomem *msi_mem;
phys_addr_t msi_mem_phys;
+ void __iomem *msix_mem;
+ phys_addr_t msix_mem_phys;
+ u8 msi_cap; /* MSI capability offset */
+ u8 msix_cap; /* MSI-X capability offset */
};
struct dw_pcie_ops {
@@ -359,6 +363,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep);
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num);
+int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
+ u16 interrupt_num);
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
#else
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
@@ -380,6 +386,12 @@ static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
+ u16 interrupt_num)
+{
+ return 0;
+}
+
static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
{
}
--
2.7.4
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* [PATCH v3 07/10] pci-epf-test/pci_endpoint_test: Use irq_type module parameter
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Add new driver parameter to allow interruption type selection.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v2->v3:
- New patch file created base on the previous patch
"misc: pci_endpoint_test: Add MSI-X support" patch file following
Kishon's suggestion.
drivers/misc/pci_endpoint_test.c | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 56be808..8f2061a 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -81,6 +81,10 @@ static bool no_msi;
module_param(no_msi, bool, 0444);
MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
+static int irq_type = IRQ_TYPE_MSI;
+module_param(irq_type, int, 0444);
+MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI)");
+
enum pci_barno {
BAR_0,
BAR_1,
@@ -107,7 +111,7 @@ struct pci_endpoint_test {
struct pci_endpoint_test_data {
enum pci_barno test_reg_bar;
size_t alignment;
- bool no_msi;
+ int irq_type;
};
static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
@@ -290,8 +294,7 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
size);
- pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
- no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
COMMAND_COPY);
@@ -360,8 +363,7 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
- pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
- no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
COMMAND_READ);
@@ -418,8 +420,7 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
- pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
- no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
COMMAND_WRITE);
@@ -504,11 +505,14 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
test->alignment = 0;
test->pdev = pdev;
+ if (no_msi)
+ irq_type = IRQ_TYPE_LEGACY;
+
data = (struct pci_endpoint_test_data *)ent->driver_data;
if (data) {
test_reg_bar = data->test_reg_bar;
test->alignment = data->alignment;
- no_msi = data->no_msi;
+ irq_type = data->irq_type;
}
init_completion(&test->irq_raised);
@@ -528,13 +532,21 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
pci_set_master(pdev);
- if (!no_msi) {
+ switch (irq_type) {
+ case IRQ_TYPE_LEGACY:
+ irq = 0;
+ break;
+ case IRQ_TYPE_MSI:
irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
if (irq < 0)
dev_err(dev, "Failed to get MSI interrupts\n");
test->num_irqs = irq;
+ break;
+ default:
+ dev_err(dev, "Invalid IRQ type selected\n");
}
+
err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
IRQF_SHARED, DRV_MODULE_NAME, test);
if (err) {
--
2.7.4
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* [PATCH v3 09/10] pci_endpoint_test: Add 2 ioctl commands
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Add MSI-X support and update driver documentation accordingly.
Add 2 new IOCTL commands:
- Allow to reconfigure driver IRQ type in runtime.
- Allow to retrieve current driver IRQ type configured.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v2->v3:
- New patch file created base on the previous patch
"misc: pci_endpoint_test: Add MSI-X support" patch file following
Kishon's suggestion.
Documentation/misc-devices/pci-endpoint-test.txt | 3 +
drivers/misc/pci_endpoint_test.c | 177 +++++++++++++++++------
2 files changed, 132 insertions(+), 48 deletions(-)
diff --git a/Documentation/misc-devices/pci-endpoint-test.txt b/Documentation/misc-devices/pci-endpoint-test.txt
index fdfa0f6..58ccca4 100644
--- a/Documentation/misc-devices/pci-endpoint-test.txt
+++ b/Documentation/misc-devices/pci-endpoint-test.txt
@@ -28,6 +28,9 @@ ioctl
to be tested should be passed as argument.
PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
to be tested should be passed as argument.
+ PCITEST_SET_IRQTYPE: Changes driver IRQ type configuration. The IRQ type
+ should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
+ PCITEST_GET_IRQTYPE: Gets driver IRQ type configuration.
PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
as argument.
PCITEST_READ: Perform read tests. The size of the buffer should be passed
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 8d15dbe..df2017f 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -157,6 +157,87 @@ static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
+{
+ int i;
+ struct pci_dev *pdev = test->pdev;
+ struct device *dev = &pdev->dev;
+
+ for (i = 0; i < test->num_irqs; i++)
+ devm_free_irq(dev, pci_irq_vector(pdev, i), test);
+
+ test->num_irqs = 0;
+}
+
+static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test)
+{
+ int irq = -1;
+ struct pci_dev *pdev = test->pdev;
+ struct device *dev = &pdev->dev;
+ bool res = true;
+
+ switch (irq_type) {
+ case IRQ_TYPE_LEGACY:
+ irq = 0;
+ break;
+ case IRQ_TYPE_MSI:
+ irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
+ if (irq < 0)
+ dev_err(dev, "Failed to get MSI interrupts\n");
+ break;
+ case IRQ_TYPE_MSIX:
+ irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
+ if (irq < 0)
+ dev_err(dev, "Failed to get MSI-X interrupts\n");
+ break;
+ default:
+ dev_err(dev, "Invalid IRQ type selected\n");
+ }
+
+ if (irq < 0) {
+ irq = 0;
+ res = false;
+ }
+ test->num_irqs = irq;
+
+ return res;
+}
+
+static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
+{
+ struct pci_dev *pdev = test->pdev;
+
+ pci_disable_msi(pdev);
+ pci_disable_msix(pdev);
+}
+
+static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
+{
+ int i;
+ int err;
+ struct pci_dev *pdev = test->pdev;
+ struct device *dev = &pdev->dev;
+
+ err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
+ IRQF_SHARED, DRV_MODULE_NAME, test);
+ if (err) {
+ dev_err(dev, "Failed to request IRQ %d\n", pdev->irq);
+ return false;
+ }
+
+ for (i = 1; i < test->num_irqs; i++) {
+ err = devm_request_irq(dev, pci_irq_vector(pdev, i),
+ pci_endpoint_test_irqhandler,
+ IRQF_SHARED, DRV_MODULE_NAME, test);
+ if (err)
+ dev_err(dev, "Failed to request IRQ %d for MSI%s %d\n",
+ pci_irq_vector(pdev, i),
+ irq_type == IRQ_TYPE_MSIX ? "-X" : "", i + 1);
+ }
+
+ return true;
+}
+
static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
enum pci_barno barno)
{
@@ -440,6 +521,38 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
return ret;
}
+static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
+ int req_irq_type)
+{
+ struct pci_dev *pdev = test->pdev;
+ struct device *dev = &pdev->dev;
+
+ if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
+ dev_err(dev, "Invalid IRQ type option\n");
+ return false;
+ }
+
+ if (irq_type == req_irq_type)
+ return true;
+
+ irq_type = req_irq_type;
+
+ pci_endpoint_test_free_irq_vectors(test);
+ pci_endpoint_test_release_irq(test);
+
+ if (!pci_endpoint_test_alloc_irq_vectors(test)) {
+ pci_endpoint_test_release_irq(test);
+ return false;
+ }
+
+ if (!pci_endpoint_test_request_irq(test)) {
+ pci_endpoint_test_release_irq(test);
+ return false;
+ }
+
+ return true;
+}
+
static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
@@ -471,6 +584,12 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
case PCITEST_COPY:
ret = pci_endpoint_test_copy(test, arg);
break;
+ case PCITEST_SET_IRQTYPE:
+ ret = pci_endpoint_test_set_irq(test, arg);
+ break;
+ case PCITEST_GET_IRQTYPE:
+ ret = irq_type;
+ break;
}
ret:
@@ -486,9 +605,7 @@ static const struct file_operations pci_endpoint_test_fops = {
static int pci_endpoint_test_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
- int i;
int err;
- int irq = 0;
int id;
char name[20];
enum pci_barno bar;
@@ -537,43 +654,11 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
pci_set_master(pdev);
- switch (irq_type) {
- case IRQ_TYPE_LEGACY:
- irq = 0;
- break;
- case IRQ_TYPE_MSI:
- irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
- if (irq < 0)
- dev_err(dev, "Failed to get MSI interrupts\n");
- test->num_irqs = irq;
- break;
- case IRQ_TYPE_MSIX:
- irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
- if (irq < 0)
- dev_err(dev, "Failed to get MSI-X interrupts\n");
- test->num_irqs = irq;
- break;
- default:
- dev_err(dev, "Invalid IRQ type selected\n");
- }
-
-
- err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
- IRQF_SHARED, DRV_MODULE_NAME, test);
- if (err) {
- dev_err(dev, "Failed to request IRQ %d\n", pdev->irq);
- goto err_disable_msi;
- }
+ if (!pci_endpoint_test_alloc_irq_vectors(test))
+ goto err_disable_irq;
- for (i = 1; i < irq; i++) {
- err = devm_request_irq(dev, pci_irq_vector(pdev, i),
- pci_endpoint_test_irqhandler,
- IRQF_SHARED, DRV_MODULE_NAME, test);
- if (err)
- dev_err(dev, "Failed to request IRQ %d for MSI%s %d\n",
- pci_irq_vector(pdev, i),
- irq_type == IRQ_TYPE_MSIX ? "-X" : "", i + 1);
- }
+ if (!pci_endpoint_test_request_irq(test))
+ goto err_disable_irq;
for (bar = BAR_0; bar <= BAR_5; bar++) {
if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
@@ -633,12 +718,10 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
pci_iounmap(pdev, test->bar[bar]);
}
- for (i = 0; i < irq; i++)
- devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), test);
+ pci_endpoint_test_free_irq_vectors(test);
-err_disable_msi:
- pci_disable_msi(pdev);
- pci_disable_msix(pdev);
+err_disable_irq:
+ pci_endpoint_test_release_irq(test);
pci_release_regions(pdev);
err_disable_pdev:
@@ -650,7 +733,6 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
static void pci_endpoint_test_remove(struct pci_dev *pdev)
{
int id;
- int i;
enum pci_barno bar;
struct pci_endpoint_test *test = pci_get_drvdata(pdev);
struct miscdevice *misc_device = &test->miscdev;
@@ -667,10 +749,9 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
if (test->bar[bar])
pci_iounmap(pdev, test->bar[bar]);
}
- for (i = 0; i < test->num_irqs; i++)
- devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), test);
- pci_disable_msi(pdev);
- pci_disable_msix(pdev);
+ pci_endpoint_test_free_irq_vectors(test);
+
+ pci_endpoint_test_release_irq(test);
pci_release_regions(pdev);
pci_disable_device(pdev);
}
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v3 10/10] tools: PCI: Add MSI-X support
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Add MSI-X support to pcitest tool.
Add 2 new IOCTL commands:
- Allow to reconfigure driver IRQ type in runtime.
- Allow to retrieve current driver IRQ type configured.
Modify pcitest.sh script to accommodate MSI-X interrupt tests.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Allow IRQ type driver reconfiguring in runtime, follwing Kishon's
suggestion.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
include/uapi/linux/pcitest.h | 3 +++
tools/pci/pcitest.c | 51 +++++++++++++++++++++++++++++++++++++++++++-
tools/pci/pcitest.sh | 15 +++++++++++++
3 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pcitest.h b/include/uapi/linux/pcitest.h
index 953cf03..cbf422e 100644
--- a/include/uapi/linux/pcitest.h
+++ b/include/uapi/linux/pcitest.h
@@ -16,5 +16,8 @@
#define PCITEST_WRITE _IOW('P', 0x4, unsigned long)
#define PCITEST_READ _IOW('P', 0x5, unsigned long)
#define PCITEST_COPY _IOW('P', 0x6, unsigned long)
+#define PCITEST_MSIX _IOW('P', 0x7, int)
+#define PCITEST_SET_IRQTYPE _IOW('P', 0x8, int)
+#define PCITEST_GET_IRQTYPE _IO('P', 0x9)
#endif /* __UAPI_LINUX_PCITEST_H */
diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
index 9074b47..af146bb 100644
--- a/tools/pci/pcitest.c
+++ b/tools/pci/pcitest.c
@@ -31,12 +31,17 @@
#define BILLION 1E9
static char *result[] = { "NOT OKAY", "OKAY" };
+static char *irq[] = { "LEGACY", "MSI", "MSI-X" };
struct pci_test {
char *device;
char barnum;
bool legacyirq;
unsigned int msinum;
+ unsigned int msixnum;
+ int irqtype;
+ bool set_irqtype;
+ bool get_irqtype;
bool read;
bool write;
bool copy;
@@ -65,6 +70,24 @@ static int run_test(struct pci_test *test)
fprintf(stdout, "%s\n", result[ret]);
}
+ if (test->set_irqtype) {
+ ret = ioctl(fd, PCITEST_SET_IRQTYPE, test->irqtype);
+ fprintf(stdout, "SET IRQ TYPE TO %s:\t\t", irq[test->irqtype]);
+ if (ret < 0)
+ fprintf(stdout, "FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->get_irqtype) {
+ ret = ioctl(fd, PCITEST_GET_IRQTYPE);
+ fprintf(stdout, "GET IRQ TYPE:\t\t");
+ if (ret < 0)
+ fprintf(stdout, "FAILED\n");
+ else
+ fprintf(stdout, "%s\n", irq[ret]);
+ }
+
if (test->legacyirq) {
ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
fprintf(stdout, "LEGACY IRQ:\t");
@@ -83,6 +106,15 @@ static int run_test(struct pci_test *test)
fprintf(stdout, "%s\n", result[ret]);
}
+ if (test->msixnum > 0 && test->msixnum <= 2048) {
+ ret = ioctl(fd, PCITEST_MSIX, test->msixnum);
+ fprintf(stdout, "MSI-X%d:\t\t", test->msixnum);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
if (test->write) {
ret = ioctl(fd, PCITEST_WRITE, test->size);
fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
@@ -133,7 +165,7 @@ int main(int argc, char **argv)
/* set default endpoint device */
test->device = "/dev/pci-endpoint-test.0";
- while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
+ while ((c = getopt(argc, argv, "D:b:m:x:i:Ilrwcs:")) != EOF)
switch (c) {
case 'D':
test->device = optarg;
@@ -151,6 +183,20 @@ int main(int argc, char **argv)
if (test->msinum < 1 || test->msinum > 32)
goto usage;
continue;
+ case 'x':
+ test->msixnum = atoi(optarg);
+ if (test->msixnum < 1 || test->msixnum > 2048)
+ goto usage;
+ continue;
+ case 'i':
+ test->irqtype = atoi(optarg);
+ if (test->irqtype < 0 || test->irqtype > 2)
+ goto usage;
+ test->set_irqtype = true;
+ continue;
+ case 'I':
+ test->get_irqtype = true;
+ continue;
case 'r':
test->read = true;
continue;
@@ -173,6 +219,9 @@ int main(int argc, char **argv)
"\t-D <dev> PCI endpoint test device {default: /dev/pci-endpoint-test.0}\n"
"\t-b <bar num> BAR test (bar number between 0..5)\n"
"\t-m <msi num> MSI test (msi number between 1..32)\n"
+ "\t-x <msix num> \tMSI-X test (msix number between 1..2048)\n"
+ "\t-i <irq type> \tSet IRQ type (0 - Legacy, 1 - MSI, 2 - MSI-X)\n"
+ "\t-I Get current IRQ type configured\n"
"\t-l Legacy IRQ test\n"
"\t-r Read buffer test\n"
"\t-w Write buffer test\n"
diff --git a/tools/pci/pcitest.sh b/tools/pci/pcitest.sh
index 77e8c85..75ed48f 100644
--- a/tools/pci/pcitest.sh
+++ b/tools/pci/pcitest.sh
@@ -16,7 +16,10 @@ echo
echo "Interrupt tests"
echo
+pcitest -i 0
pcitest -l
+
+pcitest -i 1
msi=1
while [ $msi -lt 33 ]
@@ -26,9 +29,21 @@ do
done
echo
+pcitest -i 2
+msix=1
+
+while [ $msix -lt 2049 ]
+do
+ pcitest -x $msix
+ msix=`expr $msix + 1`
+done
+echo
+
echo "Read Tests"
echo
+pcitest -i 1
+
pcitest -r -s 1
pcitest -r -s 1024
pcitest -r -s 1025
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 06/10] pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Cleanup PCI_ENDPOINT_TEST memspace (by moving the interrupt number away
from command section).
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v2->v3:
- New patch file created base on the previous patch
"misc: pci_endpoint_test: Add MSI-X support" patch file following
Kishon's suggestion.
drivers/misc/pci_endpoint_test.c | 84 ++++++++++++++++-----------
drivers/pci/endpoint/functions/pci-epf-test.c | 60 ++++++++++++-------
2 files changed, 91 insertions(+), 53 deletions(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 7b37046..56be808 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -35,38 +35,42 @@
#include <uapi/linux/pcitest.h>
-#define DRV_MODULE_NAME "pci-endpoint-test"
-
-#define PCI_ENDPOINT_TEST_MAGIC 0x0
-
-#define PCI_ENDPOINT_TEST_COMMAND 0x4
-#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
-#define COMMAND_RAISE_MSI_IRQ BIT(1)
-#define MSI_NUMBER_SHIFT 2
-/* 6 bits for MSI number */
-#define COMMAND_READ BIT(8)
-#define COMMAND_WRITE BIT(9)
-#define COMMAND_COPY BIT(10)
-
-#define PCI_ENDPOINT_TEST_STATUS 0x8
-#define STATUS_READ_SUCCESS BIT(0)
-#define STATUS_READ_FAIL BIT(1)
-#define STATUS_WRITE_SUCCESS BIT(2)
-#define STATUS_WRITE_FAIL BIT(3)
-#define STATUS_COPY_SUCCESS BIT(4)
-#define STATUS_COPY_FAIL BIT(5)
-#define STATUS_IRQ_RAISED BIT(6)
-#define STATUS_SRC_ADDR_INVALID BIT(7)
-#define STATUS_DST_ADDR_INVALID BIT(8)
-
-#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
+#define DRV_MODULE_NAME "pci-endpoint-test"
+
+#define IRQ_TYPE_LEGACY 0
+#define IRQ_TYPE_MSI 1
+
+#define PCI_ENDPOINT_TEST_MAGIC 0x0
+
+#define PCI_ENDPOINT_TEST_COMMAND 0x4
+#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
+#define COMMAND_RAISE_MSI_IRQ BIT(1)
+#define COMMAND_READ BIT(3)
+#define COMMAND_WRITE BIT(4)
+#define COMMAND_COPY BIT(5)
+
+#define PCI_ENDPOINT_TEST_STATUS 0x8
+#define STATUS_READ_SUCCESS BIT(0)
+#define STATUS_READ_FAIL BIT(1)
+#define STATUS_WRITE_SUCCESS BIT(2)
+#define STATUS_WRITE_FAIL BIT(3)
+#define STATUS_COPY_SUCCESS BIT(4)
+#define STATUS_COPY_FAIL BIT(5)
+#define STATUS_IRQ_RAISED BIT(6)
+#define STATUS_SRC_ADDR_INVALID BIT(7)
+#define STATUS_DST_ADDR_INVALID BIT(8)
+
+#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
-#define PCI_ENDPOINT_TEST_SIZE 0x1c
-#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
+#define PCI_ENDPOINT_TEST_SIZE 0x1c
+#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
+
+#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
+#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
static DEFINE_IDA(pci_endpoint_test_ida);
@@ -179,6 +183,9 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
{
u32 val;
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
+ IRQ_TYPE_LEGACY);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
COMMAND_RAISE_LEGACY_IRQ);
val = wait_for_completion_timeout(&test->irq_raised,
@@ -190,20 +197,22 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
}
static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
- u8 msi_num)
+ u8 irq_num)
{
u32 val;
struct pci_dev *pdev = test->pdev;
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
+ IRQ_TYPE_MSI);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, irq_num);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
- msi_num << MSI_NUMBER_SHIFT |
COMMAND_RAISE_MSI_IRQ);
val = wait_for_completion_timeout(&test->irq_raised,
msecs_to_jiffies(1000));
if (!val)
return false;
- if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
+ if (pci_irq_vector(pdev, irq_num - 1) == test->last_irq)
return true;
return false;
@@ -281,8 +290,11 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
size);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
+ no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
- 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
+ COMMAND_COPY);
wait_for_completion(&test->irq_raised);
@@ -348,8 +360,11 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
+ no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
- 1 << MSI_NUMBER_SHIFT | COMMAND_READ);
+ COMMAND_READ);
wait_for_completion(&test->irq_raised);
@@ -403,8 +418,11 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
+ no_msi ? IRQ_TYPE_LEGACY : IRQ_TYPE_MSI);
+ pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
- 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
+ COMMAND_WRITE);
wait_for_completion(&test->irq_raised);
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 63ed706..ff92524 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -18,13 +18,14 @@
#include <linux/pci-epf.h>
#include <linux/pci_regs.h>
+#define IRQ_TYPE_LEGACY 0
+#define IRQ_TYPE_MSI 1
+
#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
#define COMMAND_RAISE_MSI_IRQ BIT(1)
-#define MSI_NUMBER_SHIFT 2
-#define MSI_NUMBER_MASK (0x3f << MSI_NUMBER_SHIFT)
-#define COMMAND_READ BIT(8)
-#define COMMAND_WRITE BIT(9)
-#define COMMAND_COPY BIT(10)
+#define COMMAND_READ BIT(3)
+#define COMMAND_WRITE BIT(4)
+#define COMMAND_COPY BIT(5)
#define STATUS_READ_SUCCESS BIT(0)
#define STATUS_READ_FAIL BIT(1)
@@ -56,6 +57,8 @@ struct pci_epf_test_reg {
u64 dst_addr;
u32 size;
u32 checksum;
+ u32 irq_type;
+ u32 irq_number;
} __packed;
static struct pci_epf_header test_header = {
@@ -244,31 +247,39 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
return ret;
}
-static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq)
+static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type,
+ u16 irq)
{
- u8 msi_count;
struct pci_epf *epf = epf_test->epf;
+ struct device *dev = &epf->dev;
struct pci_epc *epc = epf->epc;
enum pci_barno test_reg_bar = epf_test->test_reg_bar;
struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
reg->status |= STATUS_IRQ_RAISED;
- msi_count = pci_epc_get_msi(epc, epf->func_no);
- if (irq > msi_count || msi_count <= 0)
+
+ switch (irq_type) {
+ case IRQ_TYPE_LEGACY:
pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
- else
+ break;
+ case IRQ_TYPE_MSI:
pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
+ break;
+ default:
+ dev_err(dev, "Failed to raise IRQ, unknown type\n");
+ break;
+ }
}
static void pci_epf_test_cmd_handler(struct work_struct *work)
{
int ret;
- u8 irq;
- u8 msi_count;
+ u16 count;
u32 command;
struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
cmd_handler.work);
struct pci_epf *epf = epf_test->epf;
+ struct device *dev = &epf->dev;
struct pci_epc *epc = epf->epc;
enum pci_barno test_reg_bar = epf_test->test_reg_bar;
struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
@@ -280,7 +291,10 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
reg->command = 0;
reg->status = 0;
- irq = (command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
+ if (reg->irq_type > IRQ_TYPE_MSI) {
+ dev_err(dev, "Failed to detect IRQ type\n");
+ goto reset_handler;
+ }
if (command & COMMAND_RAISE_LEGACY_IRQ) {
reg->status = STATUS_IRQ_RAISED;
@@ -294,7 +308,8 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
reg->status |= STATUS_WRITE_FAIL;
else
reg->status |= STATUS_WRITE_SUCCESS;
- pci_epf_test_raise_irq(epf_test, irq);
+ pci_epf_test_raise_irq(epf_test, reg->irq_type,
+ reg->irq_number);
goto reset_handler;
}
@@ -304,7 +319,8 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
reg->status |= STATUS_READ_SUCCESS;
else
reg->status |= STATUS_READ_FAIL;
- pci_epf_test_raise_irq(epf_test, irq);
+ pci_epf_test_raise_irq(epf_test, reg->irq_type,
+ reg->irq_number);
goto reset_handler;
}
@@ -314,16 +330,18 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
reg->status |= STATUS_COPY_SUCCESS;
else
reg->status |= STATUS_COPY_FAIL;
- pci_epf_test_raise_irq(epf_test, irq);
+ pci_epf_test_raise_irq(epf_test, reg->irq_type,
+ reg->irq_number);
goto reset_handler;
}
if (command & COMMAND_RAISE_MSI_IRQ) {
- msi_count = pci_epc_get_msi(epc, epf->func_no);
- if (irq > msi_count || msi_count <= 0)
+ count = pci_epc_get_msi(epc, epf->func_no);
+ if (reg->irq_number > count || count <= 0)
goto reset_handler;
reg->status = STATUS_IRQ_RAISED;
- pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
+ pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI,
+ reg->irq_number);
goto reset_handler;
}
@@ -457,8 +475,10 @@ static int pci_epf_test_bind(struct pci_epf *epf)
return ret;
ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
- if (ret)
+ if (ret) {
+ dev_err(dev, "MSI configuration failed\n");
return ret;
+ }
if (!epf_test->linkup_notifier)
queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
--
2.7.4
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* [PATCH v3 08/10] pci-epf-test/pci_endpoint_test: Add MSI-X support
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Add MSI-X support and update driver documentation accordingly.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v2->v3:
- New patch file created base on the previous patch
"misc: pci_endpoint_test: Add MSI-X support" patch file following
Kishon's suggestion.
Documentation/misc-devices/pci-endpoint-test.txt | 3 +++
drivers/misc/pci_endpoint_test.c | 28 ++++++++++++++++++------
drivers/pci/endpoint/functions/pci-epf-test.c | 23 ++++++++++++++++++-
3 files changed, 46 insertions(+), 8 deletions(-)
diff --git a/Documentation/misc-devices/pci-endpoint-test.txt b/Documentation/misc-devices/pci-endpoint-test.txt
index 4ebc359..fdfa0f6 100644
--- a/Documentation/misc-devices/pci-endpoint-test.txt
+++ b/Documentation/misc-devices/pci-endpoint-test.txt
@@ -10,6 +10,7 @@ The PCI driver for the test device performs the following tests
*) verifying addresses programmed in BAR
*) raise legacy IRQ
*) raise MSI IRQ
+ *) raise MSI-X IRQ
*) read data
*) write data
*) copy data
@@ -25,6 +26,8 @@ ioctl
PCITEST_LEGACY_IRQ: Tests legacy IRQ
PCITEST_MSI: Tests message signalled interrupts. The MSI number
to be tested should be passed as argument.
+ PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
+ to be tested should be passed as argument.
PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
as argument.
PCITEST_READ: Perform read tests. The size of the buffer should be passed
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 8f2061a..8d15dbe 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -39,12 +39,14 @@
#define IRQ_TYPE_LEGACY 0
#define IRQ_TYPE_MSI 1
+#define IRQ_TYPE_MSIX 2
#define PCI_ENDPOINT_TEST_MAGIC 0x0
#define PCI_ENDPOINT_TEST_COMMAND 0x4
#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
#define COMMAND_RAISE_MSI_IRQ BIT(1)
+#define COMMAND_RAISE_MSIX_IRQ BIT(2)
#define COMMAND_READ BIT(3)
#define COMMAND_WRITE BIT(4)
#define COMMAND_COPY BIT(5)
@@ -83,7 +85,7 @@ MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
static int irq_type = IRQ_TYPE_MSI;
module_param(irq_type, int, 0444);
-MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI)");
+MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
enum pci_barno {
BAR_0,
@@ -201,16 +203,18 @@ static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
}
static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
- u8 irq_num)
+ u16 irq_num, bool msix)
{
u32 val;
struct pci_dev *pdev = test->pdev;
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
- IRQ_TYPE_MSI);
+ msix == false ? IRQ_TYPE_MSI :
+ IRQ_TYPE_MSIX);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, irq_num);
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
- COMMAND_RAISE_MSI_IRQ);
+ msix == false ? COMMAND_RAISE_MSI_IRQ :
+ COMMAND_RAISE_MSIX_IRQ);
val = wait_for_completion_timeout(&test->irq_raised,
msecs_to_jiffies(1000));
if (!val)
@@ -455,7 +459,8 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
ret = pci_endpoint_test_legacy_irq(test);
break;
case PCITEST_MSI:
- ret = pci_endpoint_test_msi_irq(test, arg);
+ case PCITEST_MSIX:
+ ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
break;
case PCITEST_WRITE:
ret = pci_endpoint_test_write(test, arg);
@@ -542,6 +547,12 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
dev_err(dev, "Failed to get MSI interrupts\n");
test->num_irqs = irq;
break;
+ case IRQ_TYPE_MSIX:
+ irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
+ if (irq < 0)
+ dev_err(dev, "Failed to get MSI-X interrupts\n");
+ test->num_irqs = irq;
+ break;
default:
dev_err(dev, "Invalid IRQ type selected\n");
}
@@ -559,8 +570,9 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
pci_endpoint_test_irqhandler,
IRQF_SHARED, DRV_MODULE_NAME, test);
if (err)
- dev_err(dev, "failed to request IRQ %d for MSI %d\n",
- pci_irq_vector(pdev, i), i + 1);
+ dev_err(dev, "Failed to request IRQ %d for MSI%s %d\n",
+ pci_irq_vector(pdev, i),
+ irq_type == IRQ_TYPE_MSIX ? "-X" : "", i + 1);
}
for (bar = BAR_0; bar <= BAR_5; bar++) {
@@ -626,6 +638,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
err_disable_msi:
pci_disable_msi(pdev);
+ pci_disable_msix(pdev);
pci_release_regions(pdev);
err_disable_pdev:
@@ -657,6 +670,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
for (i = 0; i < test->num_irqs; i++)
devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), test);
pci_disable_msi(pdev);
+ pci_disable_msix(pdev);
pci_release_regions(pdev);
pci_disable_device(pdev);
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index ff92524..bfef6d1 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -20,9 +20,11 @@
#define IRQ_TYPE_LEGACY 0
#define IRQ_TYPE_MSI 1
+#define IRQ_TYPE_MSIX 2
#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
#define COMMAND_RAISE_MSI_IRQ BIT(1)
+#define COMMAND_RAISE_MSIX_IRQ BIT(2)
#define COMMAND_READ BIT(3)
#define COMMAND_WRITE BIT(4)
#define COMMAND_COPY BIT(5)
@@ -265,6 +267,9 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type,
case IRQ_TYPE_MSI:
pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
break;
+ case IRQ_TYPE_MSIX:
+ pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX, irq);
+ break;
default:
dev_err(dev, "Failed to raise IRQ, unknown type\n");
break;
@@ -291,7 +296,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
reg->command = 0;
reg->status = 0;
- if (reg->irq_type > IRQ_TYPE_MSI) {
+ if (reg->irq_type > IRQ_TYPE_MSIX) {
dev_err(dev, "Failed to detect IRQ type\n");
goto reset_handler;
}
@@ -345,6 +350,16 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
goto reset_handler;
}
+ if (command & COMMAND_RAISE_MSIX_IRQ) {
+ count = pci_epc_get_msix(epc, epf->func_no);
+ if (reg->irq_number > count || count <= 0)
+ goto reset_handler;
+ reg->status = STATUS_IRQ_RAISED;
+ pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX,
+ reg->irq_number);
+ goto reset_handler;
+ }
+
reset_handler:
queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
msecs_to_jiffies(1));
@@ -480,6 +495,12 @@ static int pci_epf_test_bind(struct pci_epf *epf)
return ret;
}
+ ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
+ if (ret) {
+ dev_err(dev, "MSI-X configuration failed\n");
+ return ret;
+ }
+
if (!epf_test->linkup_notifier)
queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
--
2.7.4
--
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* [PATCH v3 00/10] Add MSI-X support on pcitest tool
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
Patch series made against Lorenzo's branches and also depends of:
- pci/dwc
- pci/endpoint
Add MSI-X support on pcitest tool.
Add new callbacks methods and handlers to trigger the MSI-X interrupts
on the EP DesignWare IP driver.
Allow to set/get MSI-X EP maximum capability number.
Rework on set/get and triggering MSI methods on EP DesignWare IP driver.
Add a new input parameter (msix) to pcitest tool to test MSI-X feature.
Update the pcitest.sh script to support MSI-X feature tests.
Gustavo Pimentel (10):
PCI: endpoint: Add MSI-X interfaces
PCI: dwc: Add MSI-X callbacks handler
PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures
PCI: dwc: Rework MSI callbacks handler
PCI: dwc: Add legacy interrupt callback handler
pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace
pci-epf-test/pci_endpoint_test: Use irq_type module parameter
pci-epf-test/pci_endpoint_test: Add MSI-X support
pci_endpoint_test: Add 2 ioctl commands
tools: PCI: Add MSI-X support
Documentation/misc-devices/pci-endpoint-test.txt | 6 +
drivers/misc/pci_endpoint_test.c | 261 +++++++++++++++++------
drivers/pci/cadence/pcie-cadence-ep.c | 3 +-
drivers/pci/dwc/pci-dra7xx.c | 2 +-
drivers/pci/dwc/pcie-artpec6.c | 2 +-
drivers/pci/dwc/pcie-designware-ep.c | 205 ++++++++++++++++--
drivers/pci/dwc/pcie-designware-plat.c | 7 +-
drivers/pci/dwc/pcie-designware.h | 31 +--
drivers/pci/endpoint/functions/pci-epf-test.c | 81 +++++--
drivers/pci/endpoint/pci-ep-cfs.c | 24 +++
drivers/pci/endpoint/pci-epc-core.c | 68 +++++-
include/linux/pci-epc.h | 15 +-
include/linux/pci-epf.h | 1 +
include/uapi/linux/pcitest.h | 3 +
tools/pci/pcitest.c | 51 ++++-
tools/pci/pcitest.sh | 15 ++
16 files changed, 643 insertions(+), 132 deletions(-)
--
2.7.4
--
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* [PATCH v3 05/10] PCI: dwc: Add legacy interrupt callback handler
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Add a legacy interrupt callback handler. Currently DesignWare IP don't
allow trigger legacy interrupts.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-ep.c | 10 ++++++++++
drivers/pci/dwc/pcie-designware-plat.c | 3 +--
drivers/pci/dwc/pcie-designware.h | 6 ++++++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index 3ba7059..6fa363c 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -370,6 +370,16 @@ static const struct pci_epc_ops epc_ops = {
.stop = dw_pcie_ep_stop,
};
+int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct device *dev = pci->dev;
+
+ dev_err(dev, "EP cannot trigger legacy IRQs\n");
+
+ return -EINVAL;
+}
+
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num)
{
diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index 654dcb5..90a8c95 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -84,8 +84,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
switch (type) {
case PCI_EPC_IRQ_LEGACY:
- dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
- return -EINVAL;
+ return dw_pcie_ep_raise_legacy_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
case PCI_EPC_IRQ_MSIX:
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index a0ab12f..69e6e17 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -350,6 +350,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
+int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num);
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -369,6 +370,11 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{
}
+static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
+{
+ return 0;
+}
+
static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num)
{
--
2.7.4
--
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* [PATCH v3 01/10] PCI: endpoint: Add MSI-X interfaces
From: Gustavo Pimentel @ 2018-06-01 14:24 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, Joao.Pinto, jingoohan1, kishon,
adouglas, jesper.nilsson
Cc: linux-pci, linux-doc, linux-kernel, Gustavo Pimentel
In-Reply-To: <cover.1527862777.git.gustavo.pimentel@synopsys.com>
Add PCI_EPC_IRQ_MSIX type.
Add MSI-X callbacks signatures to the ops structure.
Add sysfs interface for set/get MSI-X capability maximum number.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Moved pci_epc_raise_irq() signature changes to patch file #3.
drivers/pci/endpoint/pci-ep-cfs.c | 24 ++++++++++++++++
drivers/pci/endpoint/pci-epc-core.c | 57 +++++++++++++++++++++++++++++++++++++
include/linux/pci-epc.h | 9 ++++++
include/linux/pci-epf.h | 1 +
4 files changed, 91 insertions(+)
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
index 018ea34..d1288a0 100644
--- a/drivers/pci/endpoint/pci-ep-cfs.c
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -286,6 +286,28 @@ static ssize_t pci_epf_msi_interrupts_show(struct config_item *item,
to_pci_epf_group(item)->epf->msi_interrupts);
}
+static ssize_t pci_epf_msix_interrupts_store(struct config_item *item,
+ const char *page, size_t len)
+{
+ u16 val;
+ int ret;
+
+ ret = kstrtou16(page, 0, &val);
+ if (ret)
+ return ret;
+
+ to_pci_epf_group(item)->epf->msix_interrupts = val;
+
+ return len;
+}
+
+static ssize_t pci_epf_msix_interrupts_show(struct config_item *item,
+ char *page)
+{
+ return sprintf(page, "%d\n",
+ to_pci_epf_group(item)->epf->msix_interrupts);
+}
+
PCI_EPF_HEADER_R(vendorid)
PCI_EPF_HEADER_W_u16(vendorid)
@@ -327,6 +349,7 @@ CONFIGFS_ATTR(pci_epf_, subsys_vendor_id);
CONFIGFS_ATTR(pci_epf_, subsys_id);
CONFIGFS_ATTR(pci_epf_, interrupt_pin);
CONFIGFS_ATTR(pci_epf_, msi_interrupts);
+CONFIGFS_ATTR(pci_epf_, msix_interrupts);
static struct configfs_attribute *pci_epf_attrs[] = {
&pci_epf_attr_vendorid,
@@ -340,6 +363,7 @@ static struct configfs_attribute *pci_epf_attrs[] = {
&pci_epf_attr_subsys_id,
&pci_epf_attr_interrupt_pin,
&pci_epf_attr_msi_interrupts,
+ &pci_epf_attr_msix_interrupts,
NULL,
};
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index b0ee427..7d77bd0 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -218,6 +218,63 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
EXPORT_SYMBOL_GPL(pci_epc_set_msi);
/**
+ * pci_epc_get_msix() - get the number of MSI-X interrupt numbers allocated
+ * @epc: the EPC device to which MSI-X interrupts was requested
+ * @func_no: the endpoint function number in the EPC device
+ *
+ * Invoke to get the number of MSI-X interrupts allocated by the RC
+ */
+int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
+{
+ int interrupt;
+ unsigned long flags;
+
+ if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
+ return 0;
+
+ if (!epc->ops->get_msix)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ interrupt = epc->ops->get_msix(epc, func_no);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ if (interrupt < 0)
+ return 0;
+
+ return interrupt + 1;
+}
+EXPORT_SYMBOL_GPL(pci_epc_get_msix);
+
+/**
+ * pci_epc_set_msix() - set the number of MSI-X interrupt numbers required
+ * @epc: the EPC device on which MSI-X has to be configured
+ * @func_no: the endpoint function number in the EPC device
+ * @interrupts: number of MSI-X interrupts required by the EPF
+ *
+ * Invoke to set the required number of MSI-X interrupts.
+ */
+int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
+{
+ int ret;
+ unsigned long flags;
+
+ if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
+ interrupts < 1 || interrupts > 2048)
+ return -EINVAL;
+
+ if (!epc->ops->set_msix)
+ return 0;
+
+ spin_lock_irqsave(&epc->lock, flags);
+ ret = epc->ops->set_msix(epc, func_no, interrupts - 1);
+ spin_unlock_irqrestore(&epc->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_set_msix);
+
+/**
* pci_epc_unmap_addr() - unmap CPU address from PCI address
* @epc: the EPC device on which address is allocated
* @func_no: the endpoint function number in the EPC device
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 243eaa5..89f079f 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -17,6 +17,7 @@ enum pci_epc_irq_type {
PCI_EPC_IRQ_UNKNOWN,
PCI_EPC_IRQ_LEGACY,
PCI_EPC_IRQ_MSI,
+ PCI_EPC_IRQ_MSIX,
};
/**
@@ -30,6 +31,10 @@ enum pci_epc_irq_type {
* capability register
* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
* the MSI capability register
+ * @set_msix: ops to set the requested number of MSI-X interrupts in the
+ * MSI-X capability register
+ * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
+ * from the MSI-X capability register
* @raise_irq: ops to raise a legacy or MSI interrupt
* @start: ops to start the PCI link
* @stop: ops to stop the PCI link
@@ -48,6 +53,8 @@ struct pci_epc_ops {
phys_addr_t addr);
int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
int (*get_msi)(struct pci_epc *epc, u8 func_no);
+ int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
+ int (*get_msix)(struct pci_epc *epc, u8 func_no);
int (*raise_irq)(struct pci_epc *epc, u8 func_no,
enum pci_epc_irq_type type, u8 interrupt_num);
int (*start)(struct pci_epc *epc);
@@ -144,6 +151,8 @@ void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
phys_addr_t phys_addr);
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
+int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
+int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
enum pci_epc_irq_type type, u8 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index f7d6f48..9bb1f31 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -119,6 +119,7 @@ struct pci_epf {
struct pci_epf_header *header;
struct pci_epf_bar bar[6];
u8 msi_interrupts;
+ u16 msix_interrupts;
u8 func_no;
struct pci_epc *epc;
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH 3/3] drm/amdgpu: Add documentation for PRIME related code
From: Alex Deucher @ 2018-06-01 14:29 UTC (permalink / raw)
To: Michel Dänzer
Cc: Maling list - DRI developers, Jonathan Corbet, LKML, amd-gfx list,
linux-doc
In-Reply-To: <494c2768-4ac8-7282-80dd-122add15b2bb@daenzer.net>
On Fri, Jun 1, 2018 at 9:56 AM, Michel Dänzer <michel@daenzer.net> wrote:
> On 2018-06-01 03:44 PM, Alex Deucher wrote:
>> On Fri, Jun 1, 2018 at 9:40 AM, Michel Dänzer <michel@daenzer.net> wrote:
>>> On 2018-06-01 02:58 PM, Alex Deucher wrote:
>>>> On Thu, May 31, 2018 at 12:17 PM, Michel Dänzer <michel@daenzer.net> wrote:
>>>>> From: Michel Dänzer <michel.daenzer@amd.com>
>>>>>
>>>>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
>>>>
>>>> Series is:
>>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>>
>>> Thanks. Is it okay to merge all of these via the amdgpu tree, or should
>>> I wait for an ack from Jon and/or core DRM maintainers for that?
>>
>> GPU documentation usually goes through the drm trees. You might want
>> to push patch 1 (drm_mm.rst fix) via drm_misc, but the rest are can go
>> in via the amdgpu tree since they are amdgpu specific.
>
> I'd prefer merging all three patches together, since without patch 1,
> patch 3 generates the warning below while generating documentation, and
> the reference to the PRIME Buffer Sharing section doesn't work.
>
> .../linux/Documentation/gpu/amdgpu.rst:2: WARNING: undefined label:
> prime_buffer_sharing (if the link has no caption the label must precede
> a section header)
That's fine. I'll take them all through the amdgpu tree.
Alex
>
>
> --
> Earthling Michel Dänzer | http://www.amd.com
> Libre software enthusiast | Mesa and X developer
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply
* Re: [PATCH v2 2/3] PCI: Allow specifying devices using a base bus and path of devfns
From: Alex Williamson @ 2018-06-01 14:30 UTC (permalink / raw)
To: Logan Gunthorpe
Cc: linux-kernel, linux-pci, linux-doc, Stephen Bates,
Christoph Hellwig, Bjorn Helgaas, Jonathan Corbet, Ingo Molnar,
Thomas Gleixner, Paul E. McKenney, Marc Zyngier, Kai-Heng Feng,
Frederic Weisbecker, Dan Williams, Jérôme Glisse,
Benjamin Herrenschmidt, Christian König
In-Reply-To: <20180531235010.5279-3-logang@deltatee.com>
On Thu, 31 May 2018 17:50:09 -0600
Logan Gunthorpe <logang@deltatee.com> wrote:
> When specifying PCI devices on the kernel command line using a
> BDF, the bus numbers can change when adding or replacing a device,
> changing motherboard firmware, or applying kernel parameters like
> pci=assign-buses. When this happens, it is usually undesirable to
> apply whatever command line tweak to the wrong device.
>
> Therefore, it is useful to be able to specify devices with a base
> bus number and the path of devfns needed to get to it. (Similar to
> the "device scope" structure in the Intel VT-d spec, Section 8.3.1.)
>
> Thus, we add an option to specify devices in the following format:
>
> path:[<domain>:]<bus>:<slot>.<func>/<slot>.<func>[/ ...]
>
> The path can be any segment within the PCI hierarchy of any length and
> determined through the use of 'lspci -t'. When specified this way, it is
> less likely that a renumbered bus will result in a valid device specification
> and the tweak won't be applied to the wrong device.
>
> Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
> Reviewed-by: Stephen Bates <sbates@raithlin.com>
> Acked-by: Christian König <christian.koenig@amd.com>
> ---
> Documentation/admin-guide/kernel-parameters.txt | 12 ++-
> drivers/pci/pci.c | 101 +++++++++++++++++++++++-
> 2 files changed, 107 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index e58cc671ff92..bc51b316f485 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -2989,9 +2989,10 @@
>
> Some options herein operate on a specific device
> or a set of devices (<pci_dev>). These are
> - specified in one of two formats:
> + specified in one of three formats:
>
> [<domain>:]<bus>:<slot>.<func>
> + path:[<domain>:]<bus>:<slot>.<func>/<slot>.<func>[/ ...]
> pci:<vendor>:<device>[:<subvendor>:<subdevice>]
>
> Note: the first format specifies a PCI
> @@ -2999,9 +3000,12 @@
> if new hardware is inserted, if motherboard
> firmware changes, or due to changes caused
> by other kernel parameters. The second format
> - selects devices using IDs from the
> - configuration space which may match multiple
> - devices in the system.
> + specifies a path from a device through
> + a path of multiple slot/function addresses
> + (this is more robust against renumbering
> + issues). The third format selects devices using
> + IDs from the configuration space which may match
> + multiple devices in the system.
>
> earlydump [X86] dump PCI config space before the kernel
> changes anything
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 85fec5e2640b..39f11bd0ee03 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -184,22 +184,111 @@ EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
> #endif
>
> /**
> + * pci_dev_str_match_path - test if a path string matches a device
> + * @dev: the PCI device to test
> + * @p: string to match the device against
> + * @endptr: pointer to the string after the match
> + *
> + * Test if a string (typically from a kernel parameter) formated as a
> + * path of slot/function addresses matches a PCI device. The string must
> + * be of the form:
> + *
> + * [<domain>:]<bus>:<slot>.<func>/<slot>.<func>[/ ...]
> + *
> + * A path for a device can be obtained using 'lspci -t'. Using a path
> + * is more robust against renumbering of devices than using only
> + * a single bus, slot and function address.
> + *
> + * Returns 1 if the string matches the device, 0 if it does not and
> + * a negative error code if it fails to parse the string.
> + */
> +static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
> + const char **endptr)
> +{
> + int ret;
> + int seg, bus, slot, func;
> + char *wpath, *p;
> + char end;
> +
> + *endptr = strchrnul(path, ';');
> +
> + wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
> + if (!wpath)
> + return -ENOMEM;
> +
> + while (1) {
> + p = strrchr(wpath, '/');
> + if (!p)
> + break;
> + ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
> + if (ret != 2) {
> + ret = -EINVAL;
> + goto free_and_exit;
> + }
> +
> + if (dev->devfn != PCI_DEVFN(slot, func)) {
> + ret = 0;
> + goto free_and_exit;
> + }
> +
> + /*
> + * Note: we don't need to get a reference to the upstream
> + * bridge because we hold a reference to the top level
> + * device which should hold a reference to the bridge,
> + * and so on.
> + */
> + dev = pci_upstream_bridge(dev);
> + if (!dev) {
> + ret = 0;
> + goto free_and_exit;
> + }
> +
> + *p = 0;
> + }
> +
> + ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
> + &func, &end);
> + if (ret != 4) {
> + seg = 0;
> + ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
> + if (ret != 3) {
> + ret = -EINVAL;
> + goto free_and_exit;
> + }
> + }
> +
> + ret = (seg == pci_domain_nr(dev->bus) &&
> + bus == dev->bus->number &&
> + dev->devfn == PCI_DEVFN(slot, func));
> +
> +free_and_exit:
> + kfree(wpath);
> + return ret;
> +}
Cool, I'm glad this worked. I note though that there's really not much
difference between:
[domain:]bus:slot.fn
and
[domain:]bus:slot.fn[/slot.fn[/slot.fn[/...]]]
IOW, what's defined here as the "path:" specification doesn't require
that we start at a root bus device, it can really specify a path
starting anywhere, including the target device directly. So can we
simply extend domain:bus:slot.fn to support paths without a separate
identifier? Thanks,
Alex
> +
> +/**
> * pci_dev_str_match - test if a string matches a device
> * @dev: the PCI device to test
> * @p: string to match the device against
> * @endptr: pointer to the string after the match
> *
> * Test if a string (typically from a kernel parameter) matches a
> - * specified. The string may be of one of two forms formats:
> + * specified. The string may be of one of three formats:
> *
> * [<domain>:]<bus>:<slot>.<func>
> + * path:[<domain>:]<bus>:<slot>.<func>/<slot>.<func>[/ ...]
> * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> *
> * The first format specifies a PCI bus/slot/function address which
> * may change if new hardware is inserted, if motherboard firmware changes,
> * or due to changes caused in kernel parameters.
> *
> - * The second format matches devices using IDs in the configuration
> + * The second format specifies a PCI bus/slot/function root address and
> + * a path of slot/function addresses to the specific device from the root.
> + * The path for a device can be determined through the use of 'lspci -t'.
> + * This format is more robust against renumbering issues than the first format.
> +
> + * The third format matches devices using IDs in the configuration
> * space which may match multiple devices in the system. A value of 0
> * for any field will match all devices.
> *
> @@ -236,7 +325,15 @@ static int pci_dev_str_match(struct pci_dev *dev, const char *p,
> (!subsystem_device ||
> subsystem_device == dev->subsystem_device))
> goto found;
> + } else if (strncmp(p, "path:", 5) == 0) {
> + /* PCI Root Bus and a path of Slot,Function IDs */
> + p += 5;
>
> + ret = pci_dev_str_match_path(dev, p, &p);
> + if (ret < 0)
> + return ret;
> + else if (ret)
> + goto found;
> } else {
> /* PCI Bus,Slot,Function ids are specified */
> ret = sscanf(p, "%x:%x:%x.%x%n", &seg, &bus, &slot,
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^ permalink raw reply
* Re: [PATCH] PCI: move early dump functionality from x86 arch into the common code
From: Sinan Kaya @ 2018-06-01 14:45 UTC (permalink / raw)
To: linux-pci, timur
Cc: linux-arm-msm, linux-arm-kernel, Jonathan Corbet, Thomas Gleixner,
Ingo Molnar, H. Peter Anvin,
maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), Bjorn Helgaas,
Christoffer Dall, Paul E. McKenney, Marc Zyngier, Kai-Heng Feng,
Thymo van Beers, Frederic Weisbecker, Konrad Rzeszutek Wilk,
Greg Kroah-Hartman, David Rientjes, Kate Stewart,
Philippe Ombredanne, Tom Lendacky, Juergen Gross, Borislav Petkov,
Mikulas Patocka, Petr Tesarik, Andy Lutomirski, Dou Liyang,
Ram Pai, Boris Ostrovsky, open list:DOCUMENTATION, open list
In-Reply-To: <1527654876-26716-1-git-send-email-okaya@codeaurora.org>
On 5/30/2018 12:34 AM, Sinan Kaya wrote:
> Move early dump functionality into common code so that it is available for
> all archtiectures. No need to carry arch specific reads around as the read
> hooks are already initialized by the time pci_setup_device() is getting
> called during scan.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> Documentation/admin-guide/kernel-parameters.txt | 2 +-
> arch/x86/include/asm/pci-direct.h | 5 ---
> arch/x86/kernel/setup.c | 5 ---
> arch/x86/pci/common.c | 4 --
> arch/x86/pci/early.c | 50 -------------------------
> drivers/pci/pci.c | 4 ++
> drivers/pci/pci.h | 2 +-
> drivers/pci/probe.c | 19 ++++++++++
> 8 files changed, 25 insertions(+), 66 deletions(-)
Any feedback on the direction?
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
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