* Re: [PATCH 0/3] Clean up crypto documentation
From: Joe Perches @ 2019-06-24 22:37 UTC (permalink / raw)
To: Jonathan Corbet
Cc: Gary R Hook, Hook, Gary, herbert@gondor.apana.org.au,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-crypto@vger.kernel.org, davem@davemloft.net
In-Reply-To: <20190624143748.7fcfe623@lwn.net>
On Mon, 2019-06-24 at 14:37 -0600, Jonathan Corbet wrote:
> On Mon, 24 Jun 2019 13:29:42 -0700
> Joe Perches <joe@perches.com> wrote:
>
> > > Finally, would you prefer a v2 of the patch set? Happy to do
> > > whatever is preferred, of course.
> >
> > Whatever Jonathan decides is fine with me.
> > Mine was just a plea to avoid unnecessarily
> > making the source text harder to read as
> > that's what I mostly use.
>
> Usually Herbert seems to take crypto docs, so it's not necessarily up to
> me :)
>
> I don't see much that's objectionable here. But...
>
> > I don't know if this extension is valid yet, but
> > I believe just using <function_name>() is more
> > readable as text than ``<function_name>`` or
> > :c:func:`<function_name>`
>
> It's been "valid" since I wrote it...it's just not upstream yet :) I
> expect it to be in 5.3, though. So the best way to refer to a kernel
> function, going forward, is just function() with no markup needed.
When that's actually "valid" I suggest doing:
$ git ls-files -- 'Documentation/*.rst' | \
xargs perl -pi -e 's/:c:func:`(\w+)(?:\(\))?`/\1()/g; s/``(\w+)\(\)``/\1()/g'
so function designations in Documentation are simpler to read.
Right now that's:
$ git diff --shortstat Documentation/
125 files changed, 1680 insertions(+), 1680 deletions(-)
^ permalink raw reply
* [PATCH v13 00/13] Ingenic Timer/Counter Unit patchset v13
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk
Hi,
This is the version 13 of my patchset to support the Timer/Counter Unit
(TCU) present in JZ47xx SoCs from Ingenic.
Changelog:
Patch [03/13]:
- Revert back to v11. Turns out it was okay.
- Remove 'interrupt-parent' of the list of required properties.
Patch [05/13]:
- Don't enable/disable the TCU clock on demand. Enable it in the probe
and call it a day.
- Register suspend callbacks to gate/ungate the TCU clock on
suspend/resume.
- Use pr_fmt and pr_crit instead of custom TCU_ERR() macro
- Remove useless dependency on COMMON_CLK in Kconfig
- Remove registration of clkdev
All the other patches have not been modified.
The patchset was rebased on 5.2-rc6.
Cheers,
-Paul
^ permalink raw reply
* [PATCH v13 02/13] doc: Add doc for the Ingenic TCU hardware
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
Add a documentation file about the Timer/Counter Unit (TCU) present in
the Ingenic JZ47xx SoCs.
The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
hardware block. It features up to to eight channels, that can be used as
counters, timers, or PWM.
- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
have eight channels.
- JZ4725B introduced a separate channel, called Operating System Timer
(OST). It is a 32-bit programmable timer. On JZ4770 and above, it is
64-bit.
- Each one of the TCU channels has its own clock, which can be reparented
to three different clocks (pclk, ext, rtc), gated, and reclocked, through
their TCSR register.
* The watchdog and OST hardware blocks also feature a TCSR register with
the same format in their register space.
* The TCU registers used to gate/ungate can also gate/ungate the watchdog
and OST clocks.
- Each TCU channel works in one of two modes:
* mode TCU1: channels cannot work in sleep mode, but are easier to
operate.
* mode TCU2: channels can work in sleep mode, but the operation is a bit
more complicated than with TCU1 channels.
- The mode of each TCU channel depends on the SoC used:
* On the oldest SoCs (up to JZ4740), all of the eight channels operate in
TCU1 mode.
* On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
* On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
others operate as TCU1.
- Each channel can generate an interrupt. Some channels share an interrupt
line, some don't, and this changes between SoC versions:
* on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
own interrupt line; channels 2-7 share the last interrupt line.
* On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
interrupt line; the OST uses the last interrupt line.
* on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
the OST uses the last interrupt line.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v4: New patch in this series
v5: Added information about number of channels, and improved
documentation about channel modes
v6: Add info about OST (can be 32-bit on older SoCs)
v7-v11: No change
v12: Add details about new implementation
v13: No change
Documentation/mips/ingenic-tcu.txt | 63 ++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/mips/ingenic-tcu.txt
diff --git a/Documentation/mips/ingenic-tcu.txt b/Documentation/mips/ingenic-tcu.txt
new file mode 100644
index 000000000000..1a753805779c
--- /dev/null
+++ b/Documentation/mips/ingenic-tcu.txt
@@ -0,0 +1,63 @@
+Ingenic JZ47xx SoCs Timer/Counter Unit hardware
+-----------------------------------------------
+
+The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
+hardware block. It features up to to eight channels, that can be used as
+counters, timers, or PWM.
+
+- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
+ have eight channels.
+
+- JZ4725B introduced a separate channel, called Operating System Timer
+ (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
+ 64-bit.
+
+- Each one of the TCU channels has its own clock, which can be reparented
+ to three different clocks (pclk, ext, rtc), gated, and reclocked, through
+ their TCSR register.
+ * The watchdog and OST hardware blocks also feature a TCSR register with
+ the same format in their register space.
+ * The TCU registers used to gate/ungate can also gate/ungate the watchdog
+ and OST clocks.
+
+- Each TCU channel works in one of two modes:
+ * mode TCU1: channels cannot work in sleep mode, but are easier to
+ operate.
+ * mode TCU2: channels can work in sleep mode, but the operation is a bit
+ more complicated than with TCU1 channels.
+
+- The mode of each TCU channel depends on the SoC used:
+ * On the oldest SoCs (up to JZ4740), all of the eight channels operate in
+ TCU1 mode.
+ * On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
+ * On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
+ others operate as TCU1.
+
+- Each channel can generate an interrupt. Some channels share an interrupt
+ line, some don't, and this changes between SoC versions:
+ * on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
+ own interrupt line; channels 2-7 share the last interrupt line.
+ * On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
+ interrupt line; the OST uses the last interrupt line.
+ * on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
+ channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
+ the OST uses the last interrupt line.
+
+Implementation
+--------------
+
+The functionalities of the TCU hardware are spread across multiple drivers:
+- boilerplate: drivers/mfd/ingenic-tcu.c
+- clocks: drivers/clk/ingenic/tcu.c
+- interrupts: drivers/irqchip/irq-ingenic-tcu.c
+- timers: drivers/clocksource/ingenic-timer.c
+- PWM: drivers/pwm/pwm-jz4740.c
+- watchdog: drivers/watchdog/jz4740_wdt.c
+- OST: drivers/clocksource/ingenic-ost.c
+
+Because various functionalities of the TCU that belong to different drivers
+and frameworks can be controlled from the same registers, all of these
+drivers access their registers through the same regmap.
+
+For more information regarding the devicetree bindings of the TCU drivers,
+have a look at Documentation/devicetree/bindings/mfd/ingenic,tcu.txt.
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 06/13] irqchip: Add irq-ingenic-tcu driver
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
This driver handles the interrupt controller built in the Timer/Counter
Unit (TCU) of the JZ47xx SoCs from Ingenic.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v12: New patch
v13: No change
drivers/irqchip/Kconfig | 11 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ingenic-tcu.c | 182 ++++++++++++++++++++++++++++++
3 files changed, 194 insertions(+)
create mode 100644 drivers/irqchip/irq-ingenic-tcu.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 659c5e0fb835..edc67268f777 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -294,6 +294,17 @@ config INGENIC_IRQ
depends on MACH_INGENIC
default y
+config INGENIC_TCU_IRQ
+ bool "Ingenic JZ47xx TCU interrupt controller"
+ default MACH_INGENIC
+ depends on MIPS || COMPILE_TEST
+ select INGENIC_TCU
+ help
+ Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
+ JZ47xx SoCs.
+
+ If unsure, say N.
+
config RENESAS_H8300H_INTC
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 606a003a0000..f403b2c221e4 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o
obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
+obj-$(CONFIG_INGENIC_TCU_IRQ) += irq-ingenic-tcu.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
obj-$(CONFIG_MSCC_OCELOT_IRQ) += irq-mscc-ocelot.o
diff --git a/drivers/irqchip/irq-ingenic-tcu.c b/drivers/irqchip/irq-ingenic-tcu.c
new file mode 100644
index 000000000000..738ed06c983f
--- /dev/null
+++ b/drivers/irqchip/irq-ingenic-tcu.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * JZ47xx SoCs TCU IRQ driver
+ * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/mfd/ingenic-tcu.h>
+#include <linux/of_irq.h>
+#include <linux/regmap.h>
+
+struct ingenic_tcu {
+ struct regmap *map;
+ struct clk *clk;
+
+ struct irq_domain *domain;
+ unsigned int nb_parent_irqs;
+ u32 parent_irqs[3];
+};
+
+static void ingenic_tcu_intc_cascade(struct irq_desc *desc)
+{
+ struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
+ struct irq_domain *domain = irq_desc_get_handler_data(desc);
+ struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
+ struct regmap *map = gc->private;
+ uint32_t irq_reg, irq_mask;
+ unsigned int i;
+
+ regmap_read(map, TCU_REG_TFR, &irq_reg);
+ regmap_read(map, TCU_REG_TMR, &irq_mask);
+
+ chained_irq_enter(irq_chip, desc);
+
+ irq_reg &= ~irq_mask;
+
+ for_each_set_bit(i, (unsigned long *)&irq_reg, 32)
+ generic_handle_irq(irq_linear_revmap(domain, i));
+
+ chained_irq_exit(irq_chip, desc);
+}
+
+static void ingenic_tcu_gc_unmask_enable_reg(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct irq_chip_type *ct = irq_data_get_chip_type(d);
+ struct regmap *map = gc->private;
+ u32 mask = d->mask;
+
+ irq_gc_lock(gc);
+ regmap_write(map, ct->regs.ack, mask);
+ regmap_write(map, ct->regs.enable, mask);
+ *ct->mask_cache |= mask;
+ irq_gc_unlock(gc);
+}
+
+static void ingenic_tcu_gc_mask_disable_reg(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct irq_chip_type *ct = irq_data_get_chip_type(d);
+ struct regmap *map = gc->private;
+ u32 mask = d->mask;
+
+ irq_gc_lock(gc);
+ regmap_write(map, ct->regs.disable, mask);
+ *ct->mask_cache &= ~mask;
+ irq_gc_unlock(gc);
+}
+
+static void ingenic_tcu_gc_mask_disable_reg_and_ack(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct irq_chip_type *ct = irq_data_get_chip_type(d);
+ struct regmap *map = gc->private;
+ u32 mask = d->mask;
+
+ irq_gc_lock(gc);
+ regmap_write(map, ct->regs.ack, mask);
+ regmap_write(map, ct->regs.disable, mask);
+ irq_gc_unlock(gc);
+}
+
+static int __init ingenic_tcu_irq_init(struct device_node *np,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+ struct ingenic_tcu *tcu;
+ struct regmap *map;
+ unsigned int i;
+ int ret, irqs;
+
+ map = ingenic_tcu_get_regmap(np);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
+ if (!tcu)
+ return -ENOMEM;
+
+ tcu->map = map;
+
+ irqs = of_property_count_elems_of_size(np, "interrupts", sizeof(u32));
+ if (irqs < 0 || irqs > ARRAY_SIZE(tcu->parent_irqs)) {
+ pr_crit("%s: Invalid 'interrupts' property\n", __func__);
+ ret = -EINVAL;
+ goto err_free_tcu;
+ }
+
+ tcu->nb_parent_irqs = irqs;
+
+ tcu->domain = irq_domain_add_linear(np, 32, &irq_generic_chip_ops,
+ NULL);
+ if (!tcu->domain) {
+ ret = -ENOMEM;
+ goto err_free_tcu;
+ }
+
+ ret = irq_alloc_domain_generic_chips(tcu->domain, 32, 1, "TCU",
+ handle_level_irq, 0,
+ IRQ_NOPROBE | IRQ_LEVEL, 0);
+ if (ret) {
+ pr_crit("%s: Invalid 'interrupts' property\n", __func__);
+ goto out_domain_remove;
+ }
+
+ gc = irq_get_domain_generic_chip(tcu->domain, 0);
+ ct = gc->chip_types;
+
+ gc->wake_enabled = IRQ_MSK(32);
+ gc->private = tcu->map;
+
+ ct->regs.disable = TCU_REG_TMSR;
+ ct->regs.enable = TCU_REG_TMCR;
+ ct->regs.ack = TCU_REG_TFCR;
+ ct->chip.irq_unmask = ingenic_tcu_gc_unmask_enable_reg;
+ ct->chip.irq_mask = ingenic_tcu_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = ingenic_tcu_gc_mask_disable_reg_and_ack;
+ ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
+
+ /* Mask all IRQs by default */
+ regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32));
+
+ /*
+ * On JZ4740, timer 0 and timer 1 have their own interrupt line;
+ * timers 2-7 share one interrupt.
+ * On SoCs >= JZ4770, timer 5 has its own interrupt line;
+ * timers 0-4 and 6-7 share one single interrupt.
+ *
+ * To keep things simple, we just register the same handler to
+ * all parent interrupts. The handler will properly detect which
+ * channel fired the interrupt.
+ */
+ for (i = 0; i < irqs; i++) {
+ tcu->parent_irqs[i] = irq_of_parse_and_map(np, i);
+ if (!tcu->parent_irqs[i]) {
+ ret = -EINVAL;
+ goto out_unmap_irqs;
+ }
+
+ irq_set_chained_handler_and_data(tcu->parent_irqs[i],
+ ingenic_tcu_intc_cascade,
+ tcu->domain);
+ }
+
+ return 0;
+
+out_unmap_irqs:
+ for (; i > 0; i--)
+ irq_dispose_mapping(tcu->parent_irqs[i - 1]);
+out_domain_remove:
+ irq_domain_remove(tcu->domain);
+err_free_tcu:
+ kfree(tcu);
+ return ret;
+}
+IRQCHIP_DECLARE(jz4740_tcu_irq, "ingenic,jz4740-tcu", ingenic_tcu_irq_init);
+IRQCHIP_DECLARE(jz4725b_tcu_irq, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init);
+IRQCHIP_DECLARE(jz4770_tcu_irq, "ingenic,jz4770-tcu", ingenic_tcu_irq_init);
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 11/13] MIPS: CI20: Reduce system timer and clocksource to 3 MHz
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
The default clock (48 MHz) is too fast for the system timer.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v5: New patch
v6: Set also the rate for the clocksource channel's clock
v7: No change
v8: No change
v9: Don't configure clock timer1, as the OS Timer is used as
clocksource on this SoC
v10: Revert back to v8 bahaviour. Let the user choose what
clocksource should be used.
v11-v13: No change
arch/mips/boot/dts/ingenic/ci20.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 4f7b1fa31cf5..2e9952311ecd 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "jz4780.dtsi"
+#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -238,3 +239,9 @@
bias-disable;
};
};
+
+&tcu {
+ /* 3 MHz for the system timer and clocksource */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
+ assigned-clock-rates = <3000000>, <3000000>;
+};
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 13/13] MIPS: jz4740: Drop obsolete code
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
The old clocksource/timer platform code is now obsoleted by the newly
introduced TCU drivers.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v5: New patch
v6-v11: No change
v12: Only remove clocksource code. The rest will eventually be
removed in a future patchset when the PWM/watchdog drivers
are updated.
v13: No change
arch/mips/jz4740/time.c | 154 +---------------------------------------
1 file changed, 2 insertions(+), 152 deletions(-)
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index a3260c754e65..5476899f0882 100644
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -4,164 +4,14 @@
* JZ4740 platform time support
*/
-#include <linux/clk.h>
#include <linux/clk-provider.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
+#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/sched_clock.h>
-
-#include <asm/mach-jz4740/clock.h>
-#include <asm/mach-jz4740/irq.h>
#include <asm/mach-jz4740/timer.h>
-#include <asm/time.h>
-
-#include "clock.h"
-
-#define TIMER_CLOCKEVENT 0
-#define TIMER_CLOCKSOURCE 1
-
-static uint16_t jz4740_jiffies_per_tick;
-
-static u64 jz4740_clocksource_read(struct clocksource *cs)
-{
- return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
-}
-
-static struct clocksource jz4740_clocksource = {
- .name = "jz4740-timer",
- .rating = 200,
- .read = jz4740_clocksource_read,
- .mask = CLOCKSOURCE_MASK(16),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static u64 notrace jz4740_read_sched_clock(void)
-{
- return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
-}
-
-static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
-{
- struct clock_event_device *cd = devid;
-
- jz4740_timer_ack_full(TIMER_CLOCKEVENT);
-
- if (!clockevent_state_periodic(cd))
- jz4740_timer_disable(TIMER_CLOCKEVENT);
-
- cd->event_handler(cd);
-
- return IRQ_HANDLED;
-}
-
-static int jz4740_clockevent_set_periodic(struct clock_event_device *evt)
-{
- jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
- jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
- jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
- jz4740_timer_enable(TIMER_CLOCKEVENT);
-
- return 0;
-}
-
-static int jz4740_clockevent_resume(struct clock_event_device *evt)
-{
- jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
- jz4740_timer_enable(TIMER_CLOCKEVENT);
-
- return 0;
-}
-
-static int jz4740_clockevent_shutdown(struct clock_event_device *evt)
-{
- jz4740_timer_disable(TIMER_CLOCKEVENT);
-
- return 0;
-}
-
-static int jz4740_clockevent_set_next(unsigned long evt,
- struct clock_event_device *cd)
-{
- jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
- jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
- jz4740_timer_enable(TIMER_CLOCKEVENT);
-
- return 0;
-}
-
-static struct clock_event_device jz4740_clockevent = {
- .name = "jz4740-timer",
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = jz4740_clockevent_set_next,
- .set_state_shutdown = jz4740_clockevent_shutdown,
- .set_state_periodic = jz4740_clockevent_set_periodic,
- .set_state_oneshot = jz4740_clockevent_shutdown,
- .tick_resume = jz4740_clockevent_resume,
- .rating = 200,
-#ifdef CONFIG_MACH_JZ4740
- .irq = JZ4740_IRQ_TCU0,
-#endif
-#if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780)
- .irq = JZ4780_IRQ_TCU2,
-#endif
-};
-
-static struct irqaction timer_irqaction = {
- .handler = jz4740_clockevent_irq,
- .flags = IRQF_PERCPU | IRQF_TIMER,
- .name = "jz4740-timerirq",
- .dev_id = &jz4740_clockevent,
-};
void __init plat_time_init(void)
{
- int ret;
- uint32_t clk_rate;
- uint16_t ctrl;
- struct clk *ext_clk;
-
of_clk_init(NULL);
jz4740_timer_init();
-
- ext_clk = clk_get(NULL, "ext");
- if (IS_ERR(ext_clk))
- panic("unable to get ext clock");
- clk_rate = clk_get_rate(ext_clk) >> 4;
- clk_put(ext_clk);
-
- jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
-
- clockevent_set_clock(&jz4740_clockevent, clk_rate);
- jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
- jz4740_clockevent.min_delta_ticks = 100;
- jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
- jz4740_clockevent.max_delta_ticks = 0xffff;
- jz4740_clockevent.cpumask = cpumask_of(0);
-
- clockevents_register_device(&jz4740_clockevent);
-
- ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
-
- if (ret)
- printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
-
- sched_clock_register(jz4740_read_sched_clock, 16, clk_rate);
-
- setup_irq(jz4740_clockevent.irq, &timer_irqaction);
-
- ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
-
- jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
- jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
-
- jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
- jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
-
- jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
-
- jz4740_timer_enable(TIMER_CLOCKEVENT);
- jz4740_timer_enable(TIMER_CLOCKSOURCE);
+ timer_probe();
}
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 09/13] MIPS: jz4740: Add DTS nodes for the TCU drivers
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
Add DTS nodes for the JZ4780, JZ4770 and JZ4740 devicetree files.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v5: New patch
v6: Fix register lengths in watchdog/pwm nodes
v7: No change
v8: - Fix wrong start address for PWM node
- Add system timer and clocksource sub-nodes
v9: Drop timer and clocksource sub-nodes
v10-v11: No change
v12: Drop PWM/watchdog/OST sub-nodes, for now.
v13: No change
arch/mips/boot/dts/ingenic/jz4740.dtsi | 22 ++++++++++++++++++++++
arch/mips/boot/dts/ingenic/jz4770.dtsi | 21 +++++++++++++++++++++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 21 +++++++++++++++++++++
3 files changed, 64 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 2beb78a62b7d..807d9702d4cf 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -53,6 +53,28 @@
clock-names = "rtc";
};
+ tcu: timer@10002000 {
+ compatible = "ingenic,jz4740-tcu";
+ reg = <0x10002000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10002000 0x1000>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu JZ4740_CLK_RTC
+ &cgu JZ4740_CLK_EXT
+ &cgu JZ4740_CLK_PCLK
+ &cgu JZ4740_CLK_TCU>;
+ clock-names = "rtc", "ext", "pclk", "tcu";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <23 22 21>;
+ };
+
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4740-rtc";
reg = <0x10003000 0x40>;
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index 49ede6c14ff3..70932fd90902 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -46,6 +46,27 @@
#clock-cells = <1>;
};
+ tcu: timer@10002000 {
+ compatible = "ingenic,jz4770-tcu";
+ reg = <0x10002000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10002000 0x1000>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu JZ4770_CLK_RTC
+ &cgu JZ4770_CLK_EXT
+ &cgu JZ4770_CLK_PCLK>;
+ clock-names = "rtc", "ext", "pclk";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27 26 25>;
+ };
+
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4770-pinctrl";
reg = <0x10010000 0x600>;
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b03cdec56de9..495082ce7fc5 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -46,6 +46,27 @@
#clock-cells = <1>;
};
+ tcu: timer@10002000 {
+ compatible = "ingenic,jz4770-tcu";
+ reg = <0x10002000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10002000 0x1000>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu JZ4780_CLK_RTCLK
+ &cgu JZ4780_CLK_EXCLK
+ &cgu JZ4780_CLK_PCLK>;
+ clock-names = "rtc", "ext", "pclk";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27 26 25>;
+ };
+
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4780-rtc";
reg = <0x10003000 0x4c>;
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 10/13] MIPS: qi_lb60: Reduce system timer and clocksource to 750 kHz
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
The default clock (12 MHz) is too fast for the system timer, which fails
to report time accurately.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v5: New patch
v6: Remove ingenic,clocksource-channel property
v7-v13: No change
arch/mips/boot/dts/ingenic/qi_lb60.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/qi_lb60.dts b/arch/mips/boot/dts/ingenic/qi_lb60.dts
index 76aaf8982554..01b8c917cb33 100644
--- a/arch/mips/boot/dts/ingenic/qi_lb60.dts
+++ b/arch/mips/boot/dts/ingenic/qi_lb60.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "jz4740.dtsi"
+#include <dt-bindings/clock/ingenic,tcu.h>
/ {
compatible = "qi,lb60", "ingenic,jz4740";
@@ -31,3 +32,9 @@
bias-disable;
};
};
+
+&tcu {
+ /* 750 kHz for the system timer and clocksource */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
+ assigned-clock-rates = <750000>, <750000>;
+};
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 12/13] MIPS: GCW0: Reduce system timer and clocksource to 750 kHz
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
The default clock (12 MHz) is too fast for the system timer.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v8: New patch
v9: Don't configure clock timer1, as the OS Timer is used as
clocksource on this SoC
v10: Revert back to v8 bahaviour. Let the user choose what
clocksource should be used.
v11: No change
v12: Move clocksource to channel 2, as channel 1 is used as PWM
for the backlight.
v13: No change
arch/mips/boot/dts/ingenic/gcw0.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts
index 35f0291e8d38..f58d239c2058 100644
--- a/arch/mips/boot/dts/ingenic/gcw0.dts
+++ b/arch/mips/boot/dts/ingenic/gcw0.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "jz4770.dtsi"
+#include <dt-bindings/clock/ingenic,tcu.h>
/ {
compatible = "gcw,zero", "ingenic,jz4770";
@@ -60,3 +61,12 @@
/* The WiFi module is connected to the UHC. */
status = "okay";
};
+
+&tcu {
+ /* 750 kHz for the system timer and clocksource */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
+ assigned-clock-rates = <750000>, <750000>;
+
+ /* PWM1 is in use, so reserve channel #2 for the clocksource */
+ ingenic,pwm-channels-mask = <0xfa>;
+};
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 08/13] clk: jz4740: Add TCU clock
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek, Rob Herring
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
Add the missing TCU clock to the list of clocks supplied by the CGU for
the JZ4740 SoC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
v5: New patch
v6-v13: No change
drivers/clk/ingenic/jz4740-cgu.c | 6 ++++++
include/dt-bindings/clock/jz4740-cgu.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index c77f4e1506dc..176d911b5839 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -203,6 +203,12 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 5 },
},
+
+ [JZ4740_CLK_TCU] = {
+ "tcu", CGU_CLK_GATE,
+ .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 1 },
+ },
};
static void __init jz4740_cgu_init(struct device_node *np)
diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/jz4740-cgu.h
index 6ed83f926ae7..e82d77028581 100644
--- a/include/dt-bindings/clock/jz4740-cgu.h
+++ b/include/dt-bindings/clock/jz4740-cgu.h
@@ -34,5 +34,6 @@
#define JZ4740_CLK_ADC 19
#define JZ4740_CLK_I2C 20
#define JZ4740_CLK_AIC 21
+#define JZ4740_CLK_TCU 22
#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 05/13] clk: ingenic: Add driver for the TCU clocks
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
Add driver to support the clocks provided by the Timer/Counter Unit
(TCU) of the JZ47xx SoCs from Ingenic.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v12: New patch
v13:
- Don't enable/disable the TCU clock on demand. Enable it in the probe
and call it a day.
- Register suspend callbacks to gate/ungate the TCU clock on
suspend/resume.
- Use pr_fmt and pr_crit instead of custom TCU_ERR() macro
- Remove useless dependency on COMMON_CLK in Kconfig
- Remove registration of clkdev
drivers/clk/ingenic/Kconfig | 10 +-
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/tcu.c | 473 +++++++++++++++++++++++++++++++++++
3 files changed, 483 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ingenic/tcu.c
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index fe8db93cf21a..0f39c038670f 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
-menu "Ingenic JZ47xx CGU drivers"
+menu "Ingenic JZ47xx drivers"
depends on MIPS
config INGENIC_CGU_COMMON
@@ -45,4 +45,12 @@ config INGENIC_CGU_JZ4780
If building for a JZ4780 SoC, you want to say Y here.
+config INGENIC_TCU_CLK
+ bool "Ingenic JZ47xx TCU clocks driver"
+ default MACH_INGENIC
+ select INGENIC_TCU
+ help
+ Support the clocks of the Timer/Counter Unit (TCU) of the Ingenic
+ JZ47xx SoCs.
+
endmenu
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index ab58a6a862a5..d25a5801bd8a 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
+obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o
diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c
new file mode 100644
index 000000000000..6d667c4a2bd5
--- /dev/null
+++ b/drivers/clk/ingenic/tcu.c
@@ -0,0 +1,473 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * JZ47xx SoCs TCU clocks driver
+ * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clockchips.h>
+#include <linux/mfd/ingenic-tcu.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+/* 8 channels max + watchdog + OST */
+#define TCU_CLK_COUNT 10
+
+#undef pr_fmt
+#define pr_fmt(fmt) "ingenic-tcu-clk: " fmt
+
+enum tcu_clk_parent {
+ TCU_PARENT_PCLK,
+ TCU_PARENT_RTC,
+ TCU_PARENT_EXT,
+};
+
+struct ingenic_soc_info {
+ unsigned int num_channels;
+ bool has_ost;
+ bool has_tcu_clk;
+};
+
+struct ingenic_tcu_clk_info {
+ struct clk_init_data init_data;
+ u8 gate_bit;
+ u8 tcsr_reg;
+};
+
+struct ingenic_tcu_clk {
+ struct clk_hw hw;
+ unsigned int idx;
+ struct ingenic_tcu *tcu;
+ const struct ingenic_tcu_clk_info *info;
+};
+
+struct ingenic_tcu {
+ const struct ingenic_soc_info *soc_info;
+ struct regmap *map;
+ struct clk *clk;
+
+ struct clk_hw_onecell_data *clocks;
+};
+
+static struct ingenic_tcu *ingenic_tcu;
+
+static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw)
+{
+ return container_of(hw, struct ingenic_tcu_clk, hw);
+}
+
+static int ingenic_tcu_enable(struct clk_hw *hw)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ struct ingenic_tcu *tcu = tcu_clk->tcu;
+
+ regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
+
+ return 0;
+}
+
+static void ingenic_tcu_disable(struct clk_hw *hw)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ struct ingenic_tcu *tcu = tcu_clk->tcu;
+
+ regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
+}
+
+static int ingenic_tcu_is_enabled(struct clk_hw *hw)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ unsigned int value;
+
+ regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value);
+
+ return !(value & BIT(info->gate_bit));
+}
+
+static bool ingenic_tcu_enable_regs(struct clk_hw *hw)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ struct ingenic_tcu *tcu = tcu_clk->tcu;
+ bool enabled = false;
+
+ /*
+ * If the SoC has no global TCU clock, we must ungate the channel's
+ * clock to be able to access its registers.
+ * If we have a TCU clock, it will be enabled automatically as it has
+ * been attached to the regmap.
+ */
+ if (!tcu->clk) {
+ enabled = !!ingenic_tcu_is_enabled(hw);
+ regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
+ }
+
+ return enabled;
+}
+
+static void ingenic_tcu_disable_regs(struct clk_hw *hw)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ struct ingenic_tcu *tcu = tcu_clk->tcu;
+
+ if (!tcu->clk)
+ regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
+}
+
+static u8 ingenic_tcu_get_parent(struct clk_hw *hw)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ unsigned int val = 0;
+ int ret;
+
+ ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val);
+ WARN_ONCE(ret < 0, "Unable to read TCSR %i", tcu_clk->idx);
+
+ return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1;
+}
+
+static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ bool was_enabled;
+ int ret;
+
+ was_enabled = ingenic_tcu_enable_regs(hw);
+
+ ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
+ TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx));
+ WARN_ONCE(ret < 0, "Unable to update TCSR %i", tcu_clk->idx);
+
+ if (!was_enabled)
+ ingenic_tcu_disable_regs(hw);
+
+ return 0;
+}
+
+static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ unsigned int prescale;
+ int ret;
+
+ ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale);
+ WARN_ONCE(ret < 0, "Unable to read TCSR %i", tcu_clk->idx);
+
+ prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB;
+
+ return parent_rate >> (prescale * 2);
+}
+
+static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
+{
+ u8 prescale;
+
+ for (prescale = 0; prescale < 5; prescale++)
+ if ((rate >> (prescale * 2)) <= req_rate)
+ return prescale;
+
+ return 5; /* /1024 divider */
+}
+
+static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
+ unsigned long *parent_rate)
+{
+ unsigned long rate = *parent_rate;
+ u8 prescale;
+
+ if (req_rate > rate)
+ return -EINVAL;
+
+ prescale = ingenic_tcu_get_prescale(rate, req_rate);
+
+ return rate >> (prescale * 2);
+}
+
+static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
+ unsigned long parent_rate)
+{
+ struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
+ const struct ingenic_tcu_clk_info *info = tcu_clk->info;
+ u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate);
+ bool was_enabled;
+ int ret;
+
+ was_enabled = ingenic_tcu_enable_regs(hw);
+
+ ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
+ TCU_TCSR_PRESCALE_MASK,
+ prescale << TCU_TCSR_PRESCALE_LSB);
+ WARN_ONCE(ret < 0, "Unable to update TCSR %i", tcu_clk->idx);
+
+ if (!was_enabled)
+ ingenic_tcu_disable_regs(hw);
+
+ return 0;
+}
+
+static const struct clk_ops ingenic_tcu_clk_ops = {
+ .get_parent = ingenic_tcu_get_parent,
+ .set_parent = ingenic_tcu_set_parent,
+
+ .recalc_rate = ingenic_tcu_recalc_rate,
+ .round_rate = ingenic_tcu_round_rate,
+ .set_rate = ingenic_tcu_set_rate,
+
+ .enable = ingenic_tcu_enable,
+ .disable = ingenic_tcu_disable,
+ .is_enabled = ingenic_tcu_is_enabled,
+};
+
+static const char * const ingenic_tcu_timer_parents[] = {
+ [TCU_PARENT_PCLK] = "pclk",
+ [TCU_PARENT_RTC] = "rtc",
+ [TCU_PARENT_EXT] = "ext",
+};
+
+#define DEF_TIMER(_name, _gate_bit, _tcsr) \
+ { \
+ .init_data = { \
+ .name = _name, \
+ .parent_names = ingenic_tcu_timer_parents, \
+ .num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\
+ .ops = &ingenic_tcu_clk_ops, \
+ .flags = CLK_SET_RATE_UNGATE, \
+ }, \
+ .gate_bit = _gate_bit, \
+ .tcsr_reg = _tcsr, \
+ }
+static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = {
+ [TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)),
+ [TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)),
+ [TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)),
+ [TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)),
+ [TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)),
+ [TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)),
+ [TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)),
+ [TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)),
+};
+
+static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info =
+ DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR);
+static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info =
+ DEF_TIMER("ost", 15, TCU_REG_OST_TCSR);
+#undef DEF_TIMER
+
+static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
+ unsigned int idx, enum tcu_clk_parent parent,
+ const struct ingenic_tcu_clk_info *info,
+ struct clk_hw_onecell_data *clocks)
+{
+ struct ingenic_tcu_clk *tcu_clk;
+ int err;
+
+ tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
+ if (!tcu_clk)
+ return -ENOMEM;
+
+ tcu_clk->hw.init = &info->init_data;
+ tcu_clk->idx = idx;
+ tcu_clk->info = info;
+ tcu_clk->tcu = tcu;
+
+ /* Reset channel and clock divider, set default parent */
+ ingenic_tcu_enable_regs(&tcu_clk->hw);
+ regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
+ ingenic_tcu_disable_regs(&tcu_clk->hw);
+
+ err = clk_hw_register(NULL, &tcu_clk->hw);
+ if (err) {
+ kfree(tcu_clk);
+ return err;
+ }
+
+ clocks->hws[idx] = &tcu_clk->hw;
+
+ return 0;
+}
+
+static const struct ingenic_soc_info jz4740_soc_info = {
+ .num_channels = 8,
+ .has_ost = false,
+ .has_tcu_clk = true,
+};
+
+static const struct ingenic_soc_info jz4725b_soc_info = {
+ .num_channels = 6,
+ .has_ost = true,
+ .has_tcu_clk = true,
+};
+
+static const struct ingenic_soc_info jz4770_soc_info = {
+ .num_channels = 8,
+ .has_ost = true,
+ .has_tcu_clk = false,
+};
+
+static const struct of_device_id ingenic_tcu_of_match[] __initconst = {
+ { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
+ { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
+ { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
+ { }
+};
+
+static int __init ingenic_tcu_probe(struct device_node *np)
+{
+ const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
+ struct ingenic_tcu *tcu;
+ struct regmap *map;
+ unsigned int i;
+ int ret;
+
+ map = ingenic_tcu_get_regmap(np);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
+ if (!tcu)
+ return -ENOMEM;
+
+ tcu->map = map;
+ tcu->soc_info = id->data;
+
+ if (tcu->soc_info->has_tcu_clk) {
+ tcu->clk = of_clk_get_by_name(np, "tcu");
+ if (IS_ERR(tcu->clk)) {
+ ret = PTR_ERR(tcu->clk);
+ pr_crit("Cannot get TCU clock\n");
+ goto err_free_tcu;
+ }
+
+ ret = clk_prepare_enable(tcu->clk);
+ if (ret) {
+ pr_crit("Unable to enable TCU clock\n");
+ goto err_put_clk;
+ }
+ }
+
+ tcu->clocks = kzalloc(sizeof(*tcu->clocks) +
+ sizeof(*tcu->clocks->hws) * TCU_CLK_COUNT,
+ GFP_KERNEL);
+ if (!tcu->clocks) {
+ ret = -ENOMEM;
+ goto err_clk_disable;
+ }
+
+ tcu->clocks->num = TCU_CLK_COUNT;
+
+ for (i = 0; i < tcu->soc_info->num_channels; i++) {
+ ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT,
+ &ingenic_tcu_clk_info[i],
+ tcu->clocks);
+ if (ret) {
+ pr_crit("cannot register clock %i\n", i);
+ goto err_unregister_timer_clocks;
+ }
+ }
+
+ /*
+ * We set EXT as the default parent clock for all the TCU clocks
+ * except for the watchdog one, where we set the RTC clock as the
+ * parent. Since the EXT and PCLK are much faster than the RTC clock,
+ * the watchdog would kick after a maximum time of 5s, and we might
+ * want a slower kicking time.
+ */
+ ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC,
+ &ingenic_tcu_watchdog_clk_info,
+ tcu->clocks);
+ if (ret) {
+ pr_crit("cannot register watchdog clock\n");
+ goto err_unregister_timer_clocks;
+ }
+
+ if (tcu->soc_info->has_ost) {
+ ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST,
+ TCU_PARENT_EXT,
+ &ingenic_tcu_ost_clk_info,
+ tcu->clocks);
+ if (ret) {
+ pr_crit("cannot register ost clock\n");
+ goto err_unregister_watchdog_clock;
+ }
+ }
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks);
+ if (ret) {
+ pr_crit("cannot add OF clock provider\n");
+ goto err_unregister_ost_clock;
+ }
+
+ ingenic_tcu = tcu;
+
+ return 0;
+
+err_unregister_ost_clock:
+ if (tcu->soc_info->has_ost)
+ clk_hw_unregister(tcu->clocks->hws[i + 1]);
+err_unregister_watchdog_clock:
+ clk_hw_unregister(tcu->clocks->hws[i]);
+err_unregister_timer_clocks:
+ for (i = 0; i < tcu->clocks->num; i++)
+ if (tcu->clocks->hws[i])
+ clk_hw_unregister(tcu->clocks->hws[i]);
+ kfree(tcu->clocks);
+err_clk_disable:
+ if (tcu->soc_info->has_tcu_clk)
+ clk_disable_unprepare(tcu->clk);
+err_put_clk:
+ if (tcu->soc_info->has_tcu_clk)
+ clk_put(tcu->clk);
+err_free_tcu:
+ kfree(tcu);
+ return ret;
+}
+
+static int __maybe_unused tcu_pm_suspend(void)
+{
+ struct ingenic_tcu *tcu = ingenic_tcu;
+
+ if (tcu->clk)
+ clk_disable(tcu->clk);
+
+ return 0;
+}
+
+static void __maybe_unused tcu_pm_resume(void)
+{
+ struct ingenic_tcu *tcu = ingenic_tcu;
+
+ if (tcu->clk)
+ clk_enable(tcu->clk);
+}
+
+static struct syscore_ops __maybe_unused tcu_pm_ops = {
+ .suspend = tcu_pm_suspend,
+ .resume = tcu_pm_resume,
+};
+
+static void __init ingenic_tcu_init(struct device_node *np)
+{
+ int ret = ingenic_tcu_probe(np);
+
+ if (ret)
+ pr_crit("Failed to initialize TCU clocks: %i\n", ret);
+
+ if (IS_ENABLED(CONFIG_PM_SLEEP))
+ register_syscore_ops(&tcu_pm_ops);
+}
+
+CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
+CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
+CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 07/13] clocksource: Add a new timer-ingenic driver
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
This driver handles the TCU (Timer Counter Unit) present on the Ingenic
JZ47xx SoCs, and provides the kernel with a system timer, a clocksource
and a sched_clock.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v2: Use SPDX identifier for the license
v3: - Move documentation to its own patch
- Search the devicetree for PWM clients, and use all the TCU
channels that won't be used for PWM
v4: - Add documentation about why we search for PWM clients
- Verify that the PWM clients are for the TCU PWM driver
v5: Major overhaul. Too many changes to list. Consider it's a new
patch.
v6: - Add two API functions ingenic_tcu_request_channel and
ingenic_tcu_release_channel. To be used by the PWM driver to
request the use of a TCU channel. The driver will now dynamically
move away the system timer or clocksource to a new TCU channel.
- The system timer now defaults to channel 0, the clocksource now
defaults to channel 1 and is no more optional. The
ingenic,timer-channel and ingenic,clocksource-channel devicetree
properties are now gone.
- Fix round_rate / set_rate not calculating the prescale divider
the same way. This caused problems when (parent_rate / div) would
give a non-integer result. The behaviour is correct now.
- The clocksource clock is turned off on suspend now.
v7: Fix section mismatch by using builtin_platform_driver_probe()
v8: - Removed ingenic_tcu_[request,release]_channel, and the mechanism
to dynamically change the TCU channel of the system timer or
the clocksource.
- The driver's devicetree node can now have two more children
nodes, that correspond to the system timer and clocksource.
For these two, the driver will use the TCU timer that
correspond to the memory resource supplied in their
respective node.
v9: - Removed support for clocksource / timer children devicetree
nodes. Now, we use a property "ingenic,pwm-channels-mask" to
know which PWM channels are reserved for PWM use and should
not be used as OS timers.
v10: - Use CLK_SET_RATE_UNGATE instead of CLK_SET_RATE_GATE + manually
un-gating the clock before changing rate. Same for re-parenting.
- Unconditionally create the clocksource and sched_clock even if
the SoC possesses a OS Timer. That gives the choice back to the
user which clocksource should be selected.
- Use subsys_initcall() instead of builtin_platform_driver_probe().
The OS Timer driver calls builtin_platform_driver_probe, which
requires the device to be created before that.
- Cosmetic cleanups
v11: - Change prototype of exported function
ingenic_tcu_pwm_can_use_chn(), use a struct device * as first
argument.
- Read clocksource using the regmap instead of bypassing it.
Bypassing the regmap makes sense only for the sched_clock where
the read operation must be as fast as possible.
- Fix incorrect format in pr_crit() macro
v12: - Clock handling and IRQ handling are gone, and are now handled
in their own driver.
- Obtain regmap from the ingenic-tcu MFD driver. As a result, we
cannot bypass the regmap anymore for the sched_clock.
v13: No change
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/ingenic-timer.c | 357 ++++++++++++++++++++++++++++
3 files changed, 369 insertions(+)
create mode 100644 drivers/clocksource/ingenic-timer.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3300739edce4..2d911c15db70 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -673,4 +673,15 @@ config MILBEAUT_TIMER
help
Enables the support for Milbeaut timer driver.
+config INGENIC_TIMER
+ bool "Clocksource/timer using the TCU in Ingenic JZ SoCs"
+ default MACH_INGENIC
+ depends on MIPS || COMPILE_TEST
+ depends on COMMON_CLK
+ select INGENIC_TCU
+ select TIMER_OF
+ select IRQ_DOMAIN
+ help
+ Support for the timer/counter unit of the Ingenic JZ SoCs.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 236858fa7fbf..553f3c61717a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o
obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
obj-$(CONFIG_H8300_TPU) += h8300_tpu.o
+obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
diff --git a/drivers/clocksource/ingenic-timer.c b/drivers/clocksource/ingenic-timer.c
new file mode 100644
index 000000000000..9f4df64390f4
--- /dev/null
+++ b/drivers/clocksource/ingenic-timer.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * JZ47xx SoCs TCU IRQ driver
+ * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/ingenic-tcu.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/sched_clock.h>
+
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+struct ingenic_soc_info {
+ unsigned int num_channels;
+};
+
+struct ingenic_tcu {
+ struct regmap *map;
+ struct clk *timer_clk, *cs_clk;
+
+ unsigned int timer_channel, cs_channel;
+ struct clock_event_device cevt;
+ struct clocksource cs;
+ char name[4];
+
+ unsigned long pwm_channels_mask;
+};
+
+static struct ingenic_tcu *ingenic_tcu;
+
+static u64 notrace ingenic_tcu_timer_read(void)
+{
+ struct ingenic_tcu *tcu = ingenic_tcu;
+ unsigned int count;
+
+ regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count);
+
+ return count;
+}
+
+static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs)
+{
+ return ingenic_tcu_timer_read();
+}
+
+static inline struct ingenic_tcu *to_ingenic_tcu(struct clock_event_device *evt)
+{
+ return container_of(evt, struct ingenic_tcu, cevt);
+}
+
+static int ingenic_tcu_cevt_set_state_shutdown(struct clock_event_device *evt)
+{
+ struct ingenic_tcu *tcu = to_ingenic_tcu(evt);
+
+ regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel));
+
+ return 0;
+}
+
+static int ingenic_tcu_cevt_set_next(unsigned long next,
+ struct clock_event_device *evt)
+{
+ struct ingenic_tcu *tcu = to_ingenic_tcu(evt);
+
+ if (next > 0xffff)
+ return -EINVAL;
+
+ regmap_write(tcu->map, TCU_REG_TDFRc(tcu->timer_channel), next);
+ regmap_write(tcu->map, TCU_REG_TCNTc(tcu->timer_channel), 0);
+ regmap_write(tcu->map, TCU_REG_TESR, BIT(tcu->timer_channel));
+
+ return 0;
+}
+
+static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = dev_id;
+ struct ingenic_tcu *tcu = to_ingenic_tcu(evt);
+
+ regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel));
+
+ if (evt->event_handler)
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct clk * __init ingenic_tcu_get_clock(struct device_node *np, int id)
+{
+ struct of_phandle_args args;
+
+ args.np = np;
+ args.args_count = 1;
+ args.args[0] = id;
+
+ return of_clk_get_from_provider(&args);
+}
+
+static int __init ingenic_tcu_timer_init(struct device_node *np,
+ struct ingenic_tcu *tcu)
+{
+ unsigned int timer_virq, channel = tcu->timer_channel;
+ struct irq_domain *domain;
+ unsigned long rate;
+ int err;
+
+ tcu->timer_clk = ingenic_tcu_get_clock(np, channel);
+ if (IS_ERR(tcu->timer_clk))
+ return PTR_ERR(tcu->timer_clk);
+
+ err = clk_prepare_enable(tcu->timer_clk);
+ if (err)
+ goto err_clk_put;
+
+ rate = clk_get_rate(tcu->timer_clk);
+ if (!rate) {
+ err = -EINVAL;
+ goto err_clk_disable;
+ }
+
+ domain = irq_find_host(np);
+ if (!domain) {
+ err = -ENODEV;
+ goto err_clk_disable;
+ }
+
+ timer_virq = irq_create_mapping(domain, channel);
+ if (!timer_virq) {
+ err = -EINVAL;
+ goto err_clk_disable;
+ }
+
+ snprintf(tcu->name, sizeof(tcu->name), "TCU");
+
+ err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER,
+ tcu->name, &tcu->cevt);
+ if (err)
+ goto err_irq_dispose_mapping;
+
+ tcu->cevt.cpumask = cpumask_of(smp_processor_id());
+ tcu->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
+ tcu->cevt.name = tcu->name;
+ tcu->cevt.rating = 200;
+ tcu->cevt.set_state_shutdown = ingenic_tcu_cevt_set_state_shutdown;
+ tcu->cevt.set_next_event = ingenic_tcu_cevt_set_next;
+
+ clockevents_config_and_register(&tcu->cevt, rate, 10, 0xffff);
+
+ return 0;
+
+err_irq_dispose_mapping:
+ irq_dispose_mapping(timer_virq);
+err_clk_disable:
+ clk_disable_unprepare(tcu->timer_clk);
+err_clk_put:
+ clk_put(tcu->timer_clk);
+ return err;
+}
+
+static int __init ingenic_tcu_clocksource_init(struct device_node *np,
+ struct ingenic_tcu *tcu)
+{
+ unsigned int channel = tcu->cs_channel;
+ struct clocksource *cs = &tcu->cs;
+ unsigned long rate;
+ int err;
+
+ tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
+ if (IS_ERR(tcu->cs_clk))
+ return PTR_ERR(tcu->cs_clk);
+
+ err = clk_prepare_enable(tcu->cs_clk);
+ if (err)
+ goto err_clk_put;
+
+ rate = clk_get_rate(tcu->cs_clk);
+ if (!rate) {
+ err = -EINVAL;
+ goto err_clk_disable;
+ }
+
+ /* Reset channel */
+ regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
+ 0xffff & ~TCU_TCSR_RESERVED_BITS, 0);
+
+ /* Reset counter */
+ regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
+ regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);
+
+ /* Enable channel */
+ regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));
+
+ cs->name = "ingenic-timer";
+ cs->rating = 200;
+ cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
+ cs->mask = CLOCKSOURCE_MASK(16);
+ cs->read = ingenic_tcu_timer_cs_read;
+
+ err = clocksource_register_hz(cs, rate);
+ if (err)
+ goto err_clk_disable;
+
+ return 0;
+
+err_clk_disable:
+ clk_disable_unprepare(tcu->cs_clk);
+err_clk_put:
+ clk_put(tcu->cs_clk);
+ return err;
+}
+
+static const struct ingenic_soc_info jz4740_soc_info = {
+ .num_channels = 8,
+};
+
+static const struct ingenic_soc_info jz4725b_soc_info = {
+ .num_channels = 6,
+};
+
+static const struct of_device_id ingenic_tcu_of_match[] = {
+ { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
+ { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
+ { .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
+ { }
+};
+
+static int __init ingenic_tcu_init(struct device_node *np)
+{
+ const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
+ const struct ingenic_soc_info *soc_info = id->data;
+ struct ingenic_tcu *tcu;
+ struct regmap *map;
+ long rate;
+ int ret;
+
+ of_node_clear_flag(np, OF_POPULATED);
+
+ map = ingenic_tcu_get_regmap(np);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
+ if (!tcu)
+ return -ENOMEM;
+
+ /* Enable all TCU channels for PWM use by default except channels 0/1 */
+ tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, 2);
+ of_property_read_u32(np, "ingenic,pwm-channels-mask",
+ (u32 *)&tcu->pwm_channels_mask);
+
+ /* Verify that we have at least two free channels */
+ if (hweight8(tcu->pwm_channels_mask) > soc_info->num_channels - 2) {
+ pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
+ tcu->pwm_channels_mask);
+ ret = -EINVAL;
+ goto err_free_ingenic_tcu;
+ }
+
+ tcu->map = map;
+ ingenic_tcu = tcu;
+
+ tcu->timer_channel = find_first_zero_bit(&tcu->pwm_channels_mask,
+ soc_info->num_channels);
+ tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask,
+ soc_info->num_channels,
+ tcu->timer_channel + 1);
+
+ ret = ingenic_tcu_clocksource_init(np, tcu);
+ if (ret) {
+ pr_crit("%s: Unable to init clocksource: %i\n", __func__, ret);
+ goto err_free_ingenic_tcu;
+ }
+
+ ret = ingenic_tcu_timer_init(np, tcu);
+ if (ret)
+ goto err_tcu_clocksource_cleanup;
+
+ /* Register the sched_clock at the end as there's no way to undo it */
+ rate = clk_get_rate(tcu->cs_clk);
+ sched_clock_register(ingenic_tcu_timer_read, 16, rate);
+
+ return 0;
+
+err_tcu_clocksource_cleanup:
+ clocksource_unregister(&tcu->cs);
+ clk_disable_unprepare(tcu->cs_clk);
+ clk_put(tcu->cs_clk);
+err_free_ingenic_tcu:
+ kfree(tcu);
+ return ret;
+}
+
+TIMER_OF_DECLARE(jz4740_tcu_intc, "ingenic,jz4740-tcu", ingenic_tcu_init);
+TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
+TIMER_OF_DECLARE(jz4770_tcu_intc, "ingenic,jz4770-tcu", ingenic_tcu_init);
+
+
+static int __init ingenic_tcu_probe(struct platform_device *pdev)
+{
+ platform_set_drvdata(pdev, ingenic_tcu);
+
+ return 0;
+}
+
+static int __maybe_unused ingenic_tcu_suspend(struct device *dev)
+{
+ struct ingenic_tcu *tcu = dev_get_drvdata(dev);
+
+ clk_disable(tcu->cs_clk);
+ clk_disable(tcu->timer_clk);
+ return 0;
+}
+
+static int __maybe_unused ingenic_tcu_resume(struct device *dev)
+{
+ struct ingenic_tcu *tcu = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_enable(tcu->timer_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(tcu->cs_clk);
+ if (ret) {
+ clk_disable(tcu->timer_clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dev_pm_ops __maybe_unused ingenic_tcu_pm_ops = {
+ /* _noirq: We want the TCU clocks to be gated last / ungated first */
+ .suspend_noirq = ingenic_tcu_suspend,
+ .resume_noirq = ingenic_tcu_resume,
+};
+
+static struct platform_driver ingenic_tcu_driver = {
+ .driver = {
+ .name = "ingenic-tcu-timer",
+#ifdef CONFIG_PM_SLEEP
+ .pm = &ingenic_tcu_pm_ops,
+#endif
+ .of_match_table = ingenic_tcu_of_match,
+ },
+};
+builtin_platform_driver_probe(ingenic_tcu_driver, ingenic_tcu_probe);
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 04/13] mfd: Add Ingenic TCU driver
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
This driver will provide a regmap that can be retrieved very early in
the boot process through the API function ingenic_tcu_get_regmap().
Additionally, it will call devm_of_platform_populate() so that all the
children devices will be probed.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v12: New patch
v13: No change
drivers/mfd/Kconfig | 8 +++
drivers/mfd/Makefile | 1 +
drivers/mfd/ingenic-tcu.c | 113 ++++++++++++++++++++++++++++++++
include/linux/mfd/ingenic-tcu.h | 8 +++
4 files changed, 130 insertions(+)
create mode 100644 drivers/mfd/ingenic-tcu.c
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index a17d275bf1d4..f3ed22613cbc 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -495,6 +495,14 @@ config HTC_I2CPLD
This device provides input and output GPIOs through an I2C
interface to one or more sub-chips.
+config INGENIC_TCU
+ bool "Ingenic Timer/Counter Unit (TCU) support"
+ depends on MIPS || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ Say yes here to support the Timer/Counter Unit (TCU) IP present
+ in the JZ47xx SoCs from Ingenic.
+
config MFD_INTEL_QUARK_I2C_GPIO
tristate "Intel Quark MFD I2C GPIO"
depends on PCI
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 52b1a90ff515..fb89e131ae98 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -180,6 +180,7 @@ obj-$(CONFIG_AB8500_CORE) += ab8500-core.o ab8500-sysctrl.o
obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o
obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
obj-$(CONFIG_MFD_KEMPLD) += kempld-core.o
+obj-$(CONFIG_INGENIC_TCU) += ingenic-tcu.o
obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
obj-$(CONFIG_LPC_SCH) += lpc_sch.o
obj-$(CONFIG_LPC_ICH) += lpc_ich.o
diff --git a/drivers/mfd/ingenic-tcu.c b/drivers/mfd/ingenic-tcu.c
new file mode 100644
index 000000000000..6c1d5e4310c1
--- /dev/null
+++ b/drivers/mfd/ingenic-tcu.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * JZ47xx SoCs TCU MFD driver
+ * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
+ */
+
+#include <linux/mfd/ingenic-tcu.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+struct ingenic_soc_info {
+ unsigned int num_channels;
+};
+
+static struct regmap *tcu_regmap __initdata;
+
+static const struct regmap_config ingenic_tcu_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = TCU_REG_OST_CNTHBUF,
+};
+
+static const struct ingenic_soc_info jz4740_soc_info = {
+ .num_channels = 8,
+};
+
+static const struct ingenic_soc_info jz4725b_soc_info = {
+ .num_channels = 6,
+};
+
+static const struct of_device_id ingenic_tcu_of_match[] = {
+ { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
+ { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
+ { .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
+ { }
+};
+
+static struct regmap * __init ingenic_tcu_create_regmap(struct device_node *np)
+{
+ struct resource res;
+ void __iomem *base;
+ struct regmap *map;
+
+ if (!of_match_node(ingenic_tcu_of_match, np))
+ return ERR_PTR(-EINVAL);
+
+ base = of_io_request_and_map(np, 0, "TCU");
+ if (IS_ERR(base))
+ return ERR_PTR(PTR_ERR(base));
+
+ map = regmap_init_mmio(NULL, base, &ingenic_tcu_regmap_config);
+ if (IS_ERR(map))
+ goto err_iounmap;
+
+ return map;
+
+err_iounmap:
+ iounmap(base);
+ of_address_to_resource(np, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+
+ return map;
+}
+
+static int __init ingenic_tcu_probe(struct platform_device *pdev)
+{
+ struct regmap *map = ingenic_tcu_get_regmap(pdev->dev.of_node);
+
+ platform_set_drvdata(pdev, map);
+
+ regmap_attach_dev(&pdev->dev, map, &ingenic_tcu_regmap_config);
+
+ return devm_of_platform_populate(&pdev->dev);
+}
+
+static struct platform_driver ingenic_tcu_driver = {
+ .driver = {
+ .name = "ingenic-tcu",
+ .of_match_table = ingenic_tcu_of_match,
+ },
+};
+
+static int __init ingenic_tcu_platform_init(void)
+{
+ return platform_driver_probe(&ingenic_tcu_driver,
+ ingenic_tcu_probe);
+}
+subsys_initcall(ingenic_tcu_platform_init);
+
+struct regmap * __init ingenic_tcu_get_regmap(struct device_node *np)
+{
+ if (!tcu_regmap)
+ tcu_regmap = ingenic_tcu_create_regmap(np);
+
+ return tcu_regmap;
+}
+
+bool ingenic_tcu_pwm_can_use_chn(struct device *dev, unsigned int channel)
+{
+ const struct ingenic_soc_info *soc = device_get_match_data(dev->parent);
+
+ /* Enable all TCU channels for PWM use by default except channels 0/1 */
+ u32 pwm_channels_mask = GENMASK(soc->num_channels - 1, 2);
+
+ device_property_read_u32(dev->parent, "ingenic,pwm-channels-mask",
+ &pwm_channels_mask);
+
+ return !!(pwm_channels_mask & BIT(channel));
+}
+EXPORT_SYMBOL_GPL(ingenic_tcu_pwm_can_use_chn);
diff --git a/include/linux/mfd/ingenic-tcu.h b/include/linux/mfd/ingenic-tcu.h
index 2083fa20821d..21df23916cd2 100644
--- a/include/linux/mfd/ingenic-tcu.h
+++ b/include/linux/mfd/ingenic-tcu.h
@@ -6,6 +6,11 @@
#define __LINUX_MFD_INGENIC_TCU_H_
#include <linux/bitops.h>
+#include <linux/init.h>
+
+struct device;
+struct device_node;
+struct regmap;
#define TCU_REG_WDT_TDR 0x00
#define TCU_REG_WDT_TCER 0x04
@@ -53,4 +58,7 @@
#define TCU_REG_TCNTc(c) (TCU_REG_TCNT0 + ((c) * TCU_CHANNEL_STRIDE))
#define TCU_REG_TCSRc(c) (TCU_REG_TCSR0 + ((c) * TCU_CHANNEL_STRIDE))
+struct regmap * __init ingenic_tcu_get_regmap(struct device_node *np);
+bool ingenic_tcu_pwm_can_use_chn(struct device *dev, unsigned int channel);
+
#endif /* __LINUX_MFD_INGENIC_TCU_H_ */
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 03/13] dt-bindings: Add doc for the Ingenic TCU drivers
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Rob Herring, Artur Rojek
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
Add documentation about how to properly use the Ingenic TCU
(Timer/Counter Unit) drivers from devicetree.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
Notes:
v4: New patch in this series. Corresponds to V2 patches 3-4-5 with
added content.
v5:
- Edited PWM/watchdog DT bindings documentation to point to the new
document.
- Moved main document to
Documentation/devicetree/bindings/timer/ingenic,tcu.txt
- Updated documentation to reflect the new devicetree bindings.
v6:
- Removed PWM/watchdog documentation files as asked by upstream
- Removed doc about properties that should be implicit
- Removed doc about ingenic,timer-channel /
ingenic,clocksource-channel as they are gone
- Fix WDT clock name in the binding doc
- Fix lengths of register areas in watchdog/pwm nodes
v7: No change
v8:
- Fix address of the PWM node
- Added doc about system timer and clocksource children nodes
v9:
- Remove doc about system timer and clocksource children
nodes...
- Add doc about ingenic,pwm-channels-mask property
v10: No change
v11: Fix info about default value of ingenic,pwm-channels-mask
v12: Drop sub-nodes for now; they will be introduced in a follow-up
patchset.
v13:
- Revert back to v11. Turns out it was okay.
- Remove 'interrupt-parent' of the list of required properties.
.../bindings/pwm/ingenic,jz47xx-pwm.txt | 25 ----
.../devicetree/bindings/timer/ingenic,tcu.txt | 136 ++++++++++++++++++
.../bindings/watchdog/ingenic,jz4740-wdt.txt | 17 ---
3 files changed, 136 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
create mode 100644 Documentation/devicetree/bindings/timer/ingenic,tcu.txt
delete mode 100644 Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt
diff --git a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
deleted file mode 100644
index 7d9d3f90641b..000000000000
--- a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Ingenic JZ47xx PWM Controller
-=============================
-
-Required properties:
-- compatible: One of:
- * "ingenic,jz4740-pwm"
- * "ingenic,jz4770-pwm"
- * "ingenic,jz4780-pwm"
-- #pwm-cells: Should be 3. See pwm.txt in this directory for a description
- of the cells format.
-- clocks : phandle to the external clock.
-- clock-names : Should be "ext".
-
-
-Example:
-
- pwm: pwm@10002000 {
- compatible = "ingenic,jz4740-pwm";
- reg = <0x10002000 0x1000>;
-
- #pwm-cells = <3>;
-
- clocks = <&ext>;
- clock-names = "ext";
- };
diff --git a/Documentation/devicetree/bindings/timer/ingenic,tcu.txt b/Documentation/devicetree/bindings/timer/ingenic,tcu.txt
new file mode 100644
index 000000000000..87962da64561
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ingenic,tcu.txt
@@ -0,0 +1,136 @@
+Ingenic JZ47xx SoCs Timer/Counter Unit devicetree bindings
+==========================================================
+
+For a description of the TCU hardware and drivers, have a look at
+Documentation/mips/ingenic-tcu.txt.
+
+Required properties:
+
+- compatible: Must be one of:
+ * ingenic,jz4740-tcu
+ * ingenic,jz4725b-tcu
+ * ingenic,jz4770-tcu
+- reg: Should be the offset/length value corresponding to the TCU registers
+- clocks: List of phandle & clock specifiers for clocks external to the TCU.
+ The "pclk", "rtc" and "ext" clocks should be provided. The "tcu" clock
+ should be provided if the SoC has it.
+- clock-names: List of name strings for the external clocks.
+- #clock-cells: Should be <1>;
+ Clock consumers specify this argument to identify a clock. The valid values
+ may be found in <dt-bindings/clock/ingenic,tcu.h>.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value should be 1.
+- interrupts : Specifies the interrupt the controller is connected to.
+
+Optional properties:
+
+- ingenic,pwm-channels-mask: Bitmask of TCU channels reserved for PWM use.
+ Default value is 0xfc.
+
+
+Children nodes
+==========================================================
+
+
+PWM node:
+---------
+
+Required properties:
+
+- compatible: Must be one of:
+ * ingenic,jz4740-pwm
+ * ingenic,jz4725b-pwm
+- #pwm-cells: Should be 3. See ../pwm/pwm.txt for a description of the cell
+ format.
+- clocks: List of phandle & clock specifiers for the TCU clocks.
+- clock-names: List of name strings for the TCU clocks.
+
+
+Watchdog node:
+--------------
+
+Required properties:
+
+- compatible: Must be "ingenic,jz4740-watchdog"
+- clocks: phandle to the WDT clock
+- clock-names: should be "wdt"
+
+
+OS Timer node:
+---------
+
+Required properties:
+
+- compatible: Must be one of:
+ * ingenic,jz4725b-ost
+ * ingenic,jz4770-ost
+- clocks: phandle to the OST clock
+- clock-names: should be "ost"
+- interrupts : Specifies the interrupt the OST is connected to.
+
+
+Example
+==========================================================
+
+#include <dt-bindings/clock/jz4770-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+/ {
+ tcu: timer@10002000 {
+ compatible = "ingenic,jz4770-tcu";
+ reg = <0x10002000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10002000 0x1000>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu JZ4770_CLK_RTC
+ &cgu JZ4770_CLK_EXT
+ &cgu JZ4770_CLK_PCLK>;
+ clock-names = "rtc", "ext", "pclk";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27 26 25>;
+
+ watchdog: watchdog@0 {
+ compatible = "ingenic,jz4740-watchdog";
+ reg = <0x0 0xc>;
+
+ clocks = <&tcu TCU_CLK_WDT>;
+ clock-names = "wdt";
+ };
+
+ pwm: pwm@40 {
+ compatible = "ingenic,jz4740-pwm";
+ reg = <0x40 0x80>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&tcu TCU_CLK_TIMER0
+ &tcu TCU_CLK_TIMER1
+ &tcu TCU_CLK_TIMER2
+ &tcu TCU_CLK_TIMER3
+ &tcu TCU_CLK_TIMER4
+ &tcu TCU_CLK_TIMER5
+ &tcu TCU_CLK_TIMER6
+ &tcu TCU_CLK_TIMER7>;
+ clock-names = "timer0", "timer1", "timer2", "timer3",
+ "timer4", "timer5", "timer6", "timer7";
+ };
+
+ ost: timer@e0 {
+ compatible = "ingenic,jz4770-ost";
+ reg = <0xe0 0x20>;
+
+ clocks = <&tcu TCU_CLK_OST>;
+ clock-names = "ost";
+
+ interrupts = <15>;
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt b/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt
deleted file mode 100644
index ce1cb72d5345..000000000000
--- a/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Ingenic Watchdog Timer (WDT) Controller for JZ4740 & JZ4780
-
-Required properties:
-compatible: "ingenic,jz4740-watchdog" or "ingenic,jz4780-watchdog"
-reg: Register address and length for watchdog registers
-clocks: phandle to the RTC clock
-clock-names: should be "rtc"
-
-Example:
-
-watchdog: jz4740-watchdog@10002000 {
- compatible = "ingenic,jz4740-watchdog";
- reg = <0x10002000 0x10>;
-
- clocks = <&cgu JZ4740_CLK_RTC>;
- clock-names = "rtc";
-};
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* [PATCH v13 01/13] dt-bindings: ingenic: Add DT bindings for TCU clocks
From: Paul Cercueil @ 2019-06-24 22:57 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Ralf Baechle, Paul Burton,
James Hogan, Jonathan Corbet, Michael Turquette, Stephen Boyd,
Jason Cooper, Marc Zyngier, Lee Jones
Cc: Mathieu Malaterre, od, devicetree, linux-kernel, linux-mips,
linux-doc, linux-clk, Paul Cercueil, Artur Rojek, Rob Herring
In-Reply-To: <20190624225759.18299-1-paul@crapouillou.net>
This header provides clock numbers for the ingenic,tcu
DT binding.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
Notes:
v2: Use SPDX identifier for the license
v3/v4: No change
v5: s/JZ47*_/TCU_/ and dropped *_CLK_LAST defines
v6-v13: No change
include/dt-bindings/clock/ingenic,tcu.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 include/dt-bindings/clock/ingenic,tcu.h
diff --git a/include/dt-bindings/clock/ingenic,tcu.h b/include/dt-bindings/clock/ingenic,tcu.h
new file mode 100644
index 000000000000..d569650a7945
--- /dev/null
+++ b/include/dt-bindings/clock/ingenic,tcu.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,tcu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_INGENIC_TCU_H__
+#define __DT_BINDINGS_CLOCK_INGENIC_TCU_H__
+
+#define TCU_CLK_TIMER0 0
+#define TCU_CLK_TIMER1 1
+#define TCU_CLK_TIMER2 2
+#define TCU_CLK_TIMER3 3
+#define TCU_CLK_TIMER4 4
+#define TCU_CLK_TIMER5 5
+#define TCU_CLK_TIMER6 6
+#define TCU_CLK_TIMER7 7
+#define TCU_CLK_WDT 8
+#define TCU_CLK_OST 9
+
+#endif /* __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ */
--
2.21.0.593.g511ec345e18
^ permalink raw reply related
* Re: [PATCH] bcache: make stripe_size configurable and persistent for hardware raid5/6
From: Martin K. Petersen @ 2019-06-24 23:24 UTC (permalink / raw)
To: Eric Wheeler
Cc: Coly Li, linux-block, Jonathan Corbet, Kent Overstreet,
open list:DOCUMENTATION, open list,
open list:BCACHE (BLOCK LAYER CACHE), Martin K. Petersen
In-Reply-To: <alpine.LRH.2.11.1906241800350.1114@mx.ewheeler.net>
Eric,
> Perhaps they do not set stripe_width using io_opt? I did a grep to see
> if any of them did, but I didn't see them. How is stripe_width
> indicated by RAID controllers?
The values are reported in the Block Limits VPD page for each SCSI block
device and are thus set by the SCSI disk driver. IOW, the RAID
controller device drivers have nothing to do with this.
For RAID controllers specifically, the controller firmware will fill out
the VPD fields for each virtual SCSI disk when you configure a RAID
set. For pretty much everything else, the Block Limits come straight
from the device itself.
Also note that these values aren't specific to RAID controllers at
all. Most new SCSI devices, including disk drives and SSDs, will fill
out the Block Limits VPD page one way or the other. Even some USB
storage devices are providing this page.
> If they do set io_opt, then at least my Areca 1883 does not set io_opt
> as of 4.19.x. I also have a LSI MegaRAID 3108 which does not report
> io_opt as of 4.1.x, but that is an older kernel so maybe support has
> been added since then.
I have several MegaRAIDs that all report it. But it depends on the
controller firmware.
> Is it visible through sysfs or debugfs so I can check my hardware
> support without hacking debugging the kernel?
To print the block device topology:
# lsblk -t
or look up io_opt in sysfs:
# grep . /sys/block/sdX/queue/optimal_io_size
You can also query a SCSI device's Block Limits directly:
# sg_vpd -p bl /dev/sdX
If you want to tinker, you can simulate a SCSI disk with your choice of
io_opt:
# modprobe scsi_debug opt_blks=N
where N is the number of logical blocks to report as being the optimal
I/O size.
--
Martin K. Petersen Oracle Linux Engineering
^ permalink raw reply
* Re: [PATCH] bcache: make stripe_size configurable and persistent for hardware raid5/6
From: Coly Li @ 2019-06-25 1:59 UTC (permalink / raw)
To: Eric Wheeler
Cc: linux-block, Jonathan Corbet, Kent Overstreet,
open list:DOCUMENTATION, open list,
open list:BCACHE (BLOCK LAYER CACHE), Martin K. Petersen
In-Reply-To: <alpine.LRH.2.11.1906241800350.1114@mx.ewheeler.net>
On 2019/6/25 2:14 上午, Eric Wheeler wrote:
> On Mon, 24 Jun 2019, Coly Li wrote:
>
>> On 2019/6/23 7:16 上午, Eric Wheeler wrote:
>>> From: Eric Wheeler <git@linux.ewheeler.net>
>>>
>>> While some drivers set queue_limits.io_opt (e.g., md raid5), there are
>>> currently no SCSI/RAID controller drivers that do. Previously stripe_size
>>> and partial_stripes_expensive were read-only values and could not be
>>> tuned by users (eg, for hardware RAID5/6).
>>>
>>> This patch enables users to save the optimal IO size via sysfs through
>>> the backing device attributes stripe_size and partial_stripes_expensive
>>> into the bcache superblock.
>>>
>>> Superblock changes are backwards-compatable:
>>>
>>> * partial_stripes_expensive: One bit was used in the superblock flags field
>>>
>>> * stripe_size: There are eight 64-bit "pad" fields for future use in
>>> the superblock which default to 0; from those, 32-bits are now used
>>> to save the stripe_size and load at device registration time.
>>>
>>> Signed-off-by: Eric Wheeler <bcache@linux.ewheeler.net>
>>
>> Hi Eric,
>>
>> In general I am OK with this patch. Since Peter comments lots of SCSI
>> RAID devices reports a stripe width, could you please list the hardware
>> raid devices which don't list stripe size ? Then we can make decision
>> whether it is necessary to have such option enabled.
>
> Perhaps they do not set stripe_width using io_opt? I did a grep to see if
> any of them did, but I didn't see them. How is stripe_width indicated by
> RAID controllers?
>
> If they do set io_opt, then at least my Areca 1883 does not set io_opt as
> of 4.19.x. I also have a LSI MegaRAID 3108 which does not report io_opt as
> of 4.1.x, but that is an older kernel so maybe support has been added
> since then.
>
> Martin,
>
> Where would stripe_width be configured in the SCSI drivers? Is it visible
> through sysfs or debugfs so I can check my hardware support without
> hacking debugging the kernel?
>
>>
>> Another point is, this patch changes struct cache_sb, it is no problem
>> to change on-disk format. I plan to update the super block version soon,
>> to store more configuration persistently into super block. stripe_size
>> can be added to cache_sb with other on-disk changes.
>
Hi Eric,
> Maybe bumping version makes sense, but even if you do not, this is safe to
> use on systems without bumping the version because the values are unused
> and default to 0.
Yes, I understand you, it works as you suggested. I need to think how to
organize all options in struct cache_sb, stripe_size will be arranged
then. And I will ask help to you for reviewing the changes of on-disk
format.
Thanks.
[snipped]
--
Coly Li
^ permalink raw reply
* [PATCH next v2] softirq: enable MAX_SOFTIRQ_TIME tuning with sysctl, max_softirq_time_msecs
From: Zhiqiang Liu @ 2019-06-25 3:13 UTC (permalink / raw)
To: tglx, corbet, Kees Cook, Eric Dumazet
Cc: Andrew Morton, manfred, jwilk, dvyukov, feng.tang, sunilmut,
quentin.perret, linux, alex.popov, linux-doc, linux-kernel,
linux-fsdevel, wangxiaogang (F), Zhoukang (A), Mingfangsen,
tedheadster
From: Zhiqiang liu <liuzhiqiang26@huawei.com>
In __do_softirq func, MAX_SOFTIRQ_TIME was set to 2ms via experimentation by
commit c10d73671 ("softirq: reduce latencies") in 2013, which was designed
to reduce latencies for various network workloads. The key reason is that the
maximum number of microseconds in one NAPI polling cycle in net_rx_action func
was set to 2 jiffies, so different HZ settting will lead to different latencies.
However, commit 7acf8a1e8 ("Replace 2 jiffies with sysctl netdev_budget_usecs
to enable softirq tuning") adopts netdev_budget_usecs to tun maximum number of
microseconds in one NAPI polling cycle. So the latencies of net_rx_action can be
controlled by sysadmins to copy with hardware changes over time.
Correspondingly, the MAX_SOFTIRQ_TIME should be able to be tunned by sysadmins,
who knows best about hardware performance, for excepted tradeoff between latence
and fairness. Here, we add sysctl variable max_softirq_time_msecs to replace
MAX_SOFTIRQ_TIME with 2ms default value.
Note: max_softirq_time_msecs will be coverted to jiffies, and any budget
value will be rounded up to the next jiffies, which relates to CONFIG_HZ.
The time accuracy of jiffies will result in a certain difference
between the setting jiffies of max_softirq_time_msecs and the actual
value, which is in one jiffies range.
Signed-off-by: Zhiqiang liu <liuzhiqiang26@huawei.com>
---
Documentation/sysctl/kernel.txt | 17 +++++++++++++++++
kernel/softirq.c | 8 +++++---
kernel/sysctl.c | 9 +++++++++
3 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt
index f0c86fbb3b48..23b36393f150 100644
--- a/Documentation/sysctl/kernel.txt
+++ b/Documentation/sysctl/kernel.txt
@@ -44,6 +44,7 @@ show up in /proc/sys/kernel:
- kexec_load_disabled
- kptr_restrict
- l2cr [ PPC only ]
+- max_softirq_time_msecs
- modprobe ==> Documentation/debugging-modules.txt
- modules_disabled
- msg_next_id [ sysv ipc ]
@@ -445,6 +446,22 @@ This flag controls the L2 cache of G3 processor boards. If
==============================================================
+max_softirq_time_msecs:
+
+Maximum number of milliseconds to break the loop of restarting softirq
+processing for at most MAX_SOFTIRQ_RESTART times in __do_softirq().
+max_softirq_time_msecs will be coverted to jiffies, and any budget
+value will be rounded up to the next jiffies, which relates to CONFIG_HZ.
+The time accuracy of jiffies will result in a certain difference
+between the setting jiffies of max_softirq_time_msecs and the actual
+value, which is in one jiffies range.
+
+max_softirq_time_msecs is a non-negative integer value, and setting
+negative value is meaningless and will return error.
+Default: 2
+
+==============================================================
+
modules_disabled:
A toggle value indicating if modules are allowed to be loaded
diff --git a/kernel/softirq.c b/kernel/softirq.c
index a6b81c6b6bff..1e456db70093 100644
--- a/kernel/softirq.c
+++ b/kernel/softirq.c
@@ -199,7 +199,8 @@ EXPORT_SYMBOL(__local_bh_enable_ip);
/*
* We restart softirq processing for at most MAX_SOFTIRQ_RESTART times,
- * but break the loop if need_resched() is set or after 2 ms.
+ * but break the loop if need_resched() is set or after
+ * max_softirq_time_msecs msecs.
* The MAX_SOFTIRQ_TIME provides a nice upper bound in most cases, but in
* certain cases, such as stop_machine(), jiffies may cease to
* increment and so we need the MAX_SOFTIRQ_RESTART limit as
@@ -210,7 +211,7 @@ EXPORT_SYMBOL(__local_bh_enable_ip);
* we want to handle softirqs as soon as possible, but they
* should not be able to lock up the box.
*/
-#define MAX_SOFTIRQ_TIME msecs_to_jiffies(2)
+unsigned int __read_mostly max_softirq_time_msecs = 2;
#define MAX_SOFTIRQ_RESTART 10
#ifdef CONFIG_TRACE_IRQFLAGS
@@ -248,7 +249,8 @@ static inline void lockdep_softirq_end(bool in_hardirq) { }
asmlinkage __visible void __softirq_entry __do_softirq(void)
{
- unsigned long end = jiffies + MAX_SOFTIRQ_TIME;
+ unsigned long end = jiffies +
+ msecs_to_jiffies(max_softirq_time_msecs);
unsigned long old_flags = current->flags;
int max_restart = MAX_SOFTIRQ_RESTART;
struct softirq_action *h;
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index 1beca96fb625..96ff292ce7f6 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -118,6 +118,7 @@ extern unsigned int sysctl_nr_open_min, sysctl_nr_open_max;
#ifndef CONFIG_MMU
extern int sysctl_nr_trim_pages;
#endif
+extern unsigned int max_softirq_time_msecs;
/* Constants used for minimum and maximum */
#ifdef CONFIG_LOCKUP_DETECTOR
@@ -1276,6 +1277,14 @@ static struct ctl_table kern_table[] = {
.extra2 = &one,
},
#endif
+ {
+ .procname = "max_softirq_time_msecs",
+ .data = &max_softirq_time_msecs,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ .extra1 = &zero,
+ },
{ }
};
--
2.19.1
^ permalink raw reply related
* Re: [PATCH v3] Add a document on rebasing and merging
From: Dmitry Vyukov @ 2019-06-25 5:35 UTC (permalink / raw)
To: Jonathan Corbet
Cc: open list:DOCUMENTATION, LKML, Theodore Ts'o,
Geert Uytterhoeven, David Rientjes, Jani Nikula, Michael Ellerman
In-Reply-To: <20190614082542.3f8674eb@lwn.net>
On Fri, Jun 14, 2019 at 4:25 PM Jonathan Corbet <corbet@lwn.net> wrote:
>
> On Fri, 14 Jun 2019 11:59:03 +0200
> Dmitry Vyukov <dvyukov@google.com> wrote:
>
> > I will appreciate if you elaborate a bit on this "scale of the
> > project". I wondered about reasons for having the current hierarchy of
> > trees and complex merging for a while, but wasn't able to find any
> > rationale. What exactly scale do you mean? I know a number of projects
> > that are comparable to Linux kernel, with the largest being 2 orders
> > of magnitude larger than kernel both in terms of code size and rate of
> > change, that use single tree and linear history.
>
> I'm not sure what projects you're talking about, so it's hard to compare.
>
> During the 5.2 merge window, Linus did 209 pulls, bringing in just over
> 12,000 changesets, from on the order of 1600 developers. Even if, at the
> beginning of the window, each of those pulls was set up to be a
> fast-forward, they would no longer be positioned that way once the first
> pull was done.
>
> Are you really saying that subsystem maintainers should be continuously
> rebasing their trees to avoid merges at the top level? Do you see how
> much work that would take, how badly it would obscure the development
> history, and how many bugs it would introduce? Or perhaps I misunderstood
> what you're arguing for?
I mean projects like Chromium which seems to be comparable to kernel
in code size/rate of change. LLVM, Android are several times smaller,
but on the other hand has hundreds times less trees (1). And in
particular large monorepos in companies like Google, Facebook,
Microsoft. E.g. the Google codebase sees the v5.2 number of changesets
in few hours. Although, it's not apples-to-apples with the kernel but
shows that scale per-se is not a requirement for multiple
trees/non-linear history.
So for the kernel it must a combination of scale + something else (in
the process, ownership model, ...). I am trying to understand what is
that something else, how inherent it is and what would degrade if
kernel switches to single tree/linear history. It would obviously
require some adjustments to other parts of the process as well, e.g.
you asked what maintainers do with their trees but if there is a
single tree, they don't have a tree at all. In most other scalable
processes that I am aware of, as much work as possible is pushed down
to individual contributors and they do any required rebasing. The
closest analog of maintainers only do review and approval. The idea is
to remove bottlenecks and distribute process as much as possible to
increase scalability. I heard about "maintainer scalability" in the
context of the kernel process multiple times.
^ permalink raw reply
* Re: [PATCH v13 02/13] doc: Add doc for the Ingenic TCU hardware
From: Thomas Gleixner @ 2019-06-25 6:44 UTC (permalink / raw)
To: Paul Cercueil
Cc: Daniel Lezcano, Ralf Baechle, Paul Burton, James Hogan,
Jonathan Corbet, Michael Turquette, Stephen Boyd, Jason Cooper,
Marc Zyngier, Lee Jones, Mathieu Malaterre, od, devicetree,
linux-kernel, linux-mips, linux-doc, linux-clk, Artur Rojek
In-Reply-To: <20190624225759.18299-3-paul@crapouillou.net>
Paul,
On Tue, 25 Jun 2019, Paul Cercueil wrote:
> Add a documentation file about the Timer/Counter Unit (TCU) present in
s/Add a /Add /
> the Ingenic JZ47xx SoCs.
>
> diff --git a/Documentation/mips/ingenic-tcu.txt b/Documentation/mips/ingenic-tcu.txt
> new file mode 100644
> index 000000000000..1a753805779c
> --- /dev/null
> +++ b/Documentation/mips/ingenic-tcu.txt
There is a massive effort to convert the whole Documentation tree to rst
format. Please do not introduce new txt files.
Also documentation wants a SPDX license identifier.
> +Implementation
> +--------------
> +
> +The functionalities of the TCU hardware are spread across multiple drivers:
> +- boilerplate: drivers/mfd/ingenic-tcu.c
> +- clocks: drivers/clk/ingenic/tcu.c
> +- interrupts: drivers/irqchip/irq-ingenic-tcu.c
> +- timers: drivers/clocksource/ingenic-timer.c
> +- PWM: drivers/pwm/pwm-jz4740.c
> +- watchdog: drivers/watchdog/jz4740_wdt.c
> +- OST: drivers/clocksource/ingenic-ost.c
Hrm. These file names are going to be stale over time, but I have no better
idea either.
Thanks,
tglx
^ permalink raw reply
* Re: [PATCH v13 06/13] irqchip: Add irq-ingenic-tcu driver
From: Thomas Gleixner @ 2019-06-25 6:51 UTC (permalink / raw)
To: Paul Cercueil
Cc: Daniel Lezcano, Ralf Baechle, Paul Burton, James Hogan,
Jonathan Corbet, Michael Turquette, Stephen Boyd, Jason Cooper,
Marc Zyngier, Lee Jones, Mathieu Malaterre, od, devicetree,
linux-kernel, linux-mips, linux-doc, linux-clk, Artur Rojek
In-Reply-To: <20190624225759.18299-7-paul@crapouillou.net>
On Tue, 25 Jun 2019, Paul Cercueil wrote:
> --- /dev/null
> +++ b/drivers/irqchip/irq-ingenic-tcu.c
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * JZ47xx SoCs TCU IRQ driver
> + * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
> + */
Nothing to complain here. Just a few nit picks.
> +
> +struct ingenic_tcu {
> + struct regmap *map;
> + struct clk *clk;
> +
> + struct irq_domain *domain;
> + unsigned int nb_parent_irqs;
> + u32 parent_irqs[3];
> +};
In case you respin this then please format it tabular:
struct ingenic_tcu {
struct regmap *map;
struct clk *clk;
struct irq_domain *domain;
unsigned int nb_parent_irqs;
u32 parent_irqs[3];
};
It's simpler to parse that way, at least for me :)
Anyway:
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
^ permalink raw reply
* Re: [PATCH v13 07/13] clocksource: Add a new timer-ingenic driver
From: Thomas Gleixner @ 2019-06-25 6:53 UTC (permalink / raw)
To: Paul Cercueil
Cc: Daniel Lezcano, Ralf Baechle, Paul Burton, James Hogan,
Jonathan Corbet, Michael Turquette, Stephen Boyd, Jason Cooper,
Marc Zyngier, Lee Jones, Mathieu Malaterre, od, devicetree,
linux-kernel, linux-mips, linux-doc, linux-clk, Artur Rojek
In-Reply-To: <20190624225759.18299-8-paul@crapouillou.net>
On Tue, 25 Jun 2019, Paul Cercueil wrote:
> +
> +struct ingenic_soc_info {
> + unsigned int num_channels;
> +};
> +
> +struct ingenic_tcu {
> + struct regmap *map;
> + struct clk *timer_clk, *cs_clk;
> +
> + unsigned int timer_channel, cs_channel;
> + struct clock_event_device cevt;
> + struct clocksource cs;
> + char name[4];
> +
> + unsigned long pwm_channels_mask;
> +};
As in the irq driver. Aside of that:
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
^ permalink raw reply
* Re: [PATCH v4 00/14] ima: introduce IMA Digest Lists extension
From: Roberto Sassu @ 2019-06-25 12:57 UTC (permalink / raw)
To: zohar, dmitry.kasatkin, mjg59
Cc: linux-integrity, linux-security-module, linux-fsdevel, linux-doc,
linux-kernel, silviu.vlasceanu
In-Reply-To: <9029dd14-1077-ec89-ddc2-e677e16ad314@huawei.com>
On 6/17/2019 8:56 AM, Roberto Sassu wrote:
> On 6/14/2019 7:54 PM, Roberto Sassu wrote:
>> This patch set introduces a new IMA extension called IMA Digest Lists.
>>
>> At early boot, the extension preloads in kernel memory reference digest
>> values, that can be compared with actual file digests when files are
>> accessed in the system.
>>
>> The extension will open for new possibilities: PCR with predictable
>> value,
>> that can be used for sealing policies associated to data or TPM keys;
>> appraisal based on reference digests already provided by Linux
>> distribution
>> vendors in the software packages.
>>
>> The first objective can be achieved because the PCR values does not
>> depend
>> on which and when files are measured: the extension measures digest lists
>> sequentially and files whose digest is not in the digest list.
>>
>> The second objective can be reached because the extension is able to
>> extract reference measurements from packages (with a user space tool) and
>> use it as a source for appraisal verification as the reference came from
>> the security.ima xattr. This approach will also reduce the overhead as
>> only
>> one signature is verified for many files (as opposed to one signature for
>> each file with the current implementation).
>>
>> This version of the patch set provides a clear separation between current
>> and new functionality. First, the new functionality must be explicitly
>> enabled from the kernel command line. Second, results of operations
>> performed by the extension can be distinguished from those obtained from
>> the existing code: measurement entries created by the extension have a
>> different PCR; mutable files appraised with the extension have a
>> different
>> security.ima type.
>>
>> The review of this patch set should start from patch 11 and 12, which
>> modify the IMA-Measure and IMA-Appraise submodules to use digest lists.
>> Patch 1 to 5 are prerequisites. Patch 6 to 10 adds support for digest
>> lists. Finally, patch 13 introduces two new policies to measure/appraise
>> rootfs and patch 14 adds the documentation (including a flow chart to
>> show how IMA has been modified).
>>
>> The user space tools to configure digest lists are available at:
>>
>> https://github.com/euleros/digest-list-tools/releases/tag/v0.3
>>
>> The patch set applies on top of linux-integrity/next-queued-testing
>> (73589972b987).
>>
>> It is necessary to apply also:
>> https://patchwork.kernel.org/cover/10957495/
>
> Another dependency is:
>
> https://patchwork.kernel.org/cover/10979341/
>
> Roberto
I uploaded this patch set and all the required dependencies to:
https://github.com/euleros/linux/releases/tag/ima-digest-lists-v4
It should be easy to test. Let me know if you have questions about the
installation.
Mimi, do you have any thoughts on this version?
Thanks
Roberto
--
HUAWEI TECHNOLOGIES Duesseldorf GmbH, HRB 56063
Managing Director: Bo PENG, Jian LI, Yanli SHI
^ permalink raw reply
* Re: [PATCH 2/3] crypto: doc - Describe the crypto engine
From: Gary R Hook @ 2019-06-25 13:05 UTC (permalink / raw)
To: Eric Biggers, Hook, Gary
Cc: herbert@gondor.apana.org.au, corbet@lwn.net,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-crypto@vger.kernel.org, davem@davemloft.net
In-Reply-To: <20190624220313.GB237341@gmail.com>
On 6/24/19 5:03 PM, Eric Biggers wrote:
> On Mon, Jun 24, 2019 at 07:07:49PM +0000, Hook, Gary wrote:
>> Add a reference to the crypto engine documentation to
>> the index.
>>
>> Signed-off-by: Gary R Hook <gary.hook@amd.com>
>> ---
>> Documentation/crypto/index.rst | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst
>> index c4ff5d791233..37cd7fb0ea82 100644
>> --- a/Documentation/crypto/index.rst
>> +++ b/Documentation/crypto/index.rst
>> @@ -19,6 +19,7 @@ for cryptographic use cases, as well as programming examples.
>> intro
>> architecture
>> devel-algos
>> + crypto_engine
>> userspace-if
>> crypto_engine
>> api
>>
>
> It's already in the list.
Gah! And at the moment I can't remember why that even got put there.
Apologies.
grh
^ permalink raw reply
* Re: [PATCH v3 13/33] docs: infiniband: convert docs to ReST and rename to *.rst
From: Jason Gunthorpe @ 2019-06-25 13:24 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Linux Doc Mailing List, Mauro Carvalho Chehab,
linux-kernel@vger.kernel.org, Jonathan Corbet, Doug Ledford,
linux-rdma@vger.kernel.org
In-Reply-To: <09036fdb89c4bec94cb92d25398c026afdb134e7.1560045490.git.mchehab+samsung@kernel.org>
On Sat, Jun 08, 2019 at 11:27:03PM -0300, Mauro Carvalho Chehab wrote:
> The InfiniBand docs are plain text with no markups.
> So, all we needed to do were to add the title markups and
> some markup sequences in order to properly parse tables,
> lists and literal blocks.
>
> At its new index.rst, let's add a :orphan: while this is not linked to
> the main index.rst file, in order to avoid build warnings.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
> ---
> .../{core_locking.txt => core_locking.rst} | 64 ++++++-----
> Documentation/infiniband/index.rst | 23 ++++
> .../infiniband/{ipoib.txt => ipoib.rst} | 24 ++--
> .../infiniband/{opa_vnic.txt => opa_vnic.rst} | 108 +++++++++---------
> .../infiniband/{sysfs.txt => sysfs.rst} | 4 +-
> .../{tag_matching.txt => tag_matching.rst} | 5 +
> .../infiniband/{user_mad.txt => user_mad.rst} | 33 ++++--
> .../{user_verbs.txt => user_verbs.rst} | 12 +-
> drivers/infiniband/core/user_mad.c | 2 +-
> drivers/infiniband/ulp/ipoib/Kconfig | 2 +-
> 10 files changed, 174 insertions(+), 103 deletions(-)
> rename Documentation/infiniband/{core_locking.txt => core_locking.rst} (78%)
> create mode 100644 Documentation/infiniband/index.rst
> rename Documentation/infiniband/{ipoib.txt => ipoib.rst} (90%)
> rename Documentation/infiniband/{opa_vnic.txt => opa_vnic.rst} (63%)
> rename Documentation/infiniband/{sysfs.txt => sysfs.rst} (69%)
> rename Documentation/infiniband/{tag_matching.txt => tag_matching.rst} (98%)
> rename Documentation/infiniband/{user_mad.txt => user_mad.rst} (90%)
> rename Documentation/infiniband/{user_verbs.txt => user_verbs.rst} (93%)
Applied to for-next, thanks
Jason
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox