* [PATCH v11 net-next 01/11] net/nebula-matrix: add minimum nbl build framework
From: illusion.wang @ 2026-04-08 9:37 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, linux-doc, lorenzo, pabeni, horms,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260408093739.56001-1-illusion.wang@nebula-matrix.com>
1.Add nbl min build infrastructure for nbl driver.
2.Add PCI driver skeleton with empty stubs for nbl driver.
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../device_drivers/ethernet/index.rst | 1 +
.../ethernet/nebula-matrix/nbl.rst | 27 +++++
MAINTAINERS | 10 ++
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/nebula-matrix/Kconfig | 34 ++++++
drivers/net/ethernet/nebula-matrix/Makefile | 6 +
.../net/ethernet/nebula-matrix/nbl/Makefile | 6 +
.../net/ethernet/nebula-matrix/nbl/nbl_core.h | 16 +++
.../nbl/nbl_include/nbl_include.h | 21 ++++
.../net/ethernet/nebula-matrix/nbl/nbl_main.c | 113 ++++++++++++++++++
11 files changed, 236 insertions(+)
create mode 100644 Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
create mode 100644 drivers/net/ethernet/nebula-matrix/Kconfig
create mode 100644 drivers/net/ethernet/nebula-matrix/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/Documentation/networking/device_drivers/ethernet/index.rst
index 5f3f06111911..14868fabc1c6 100644
--- a/Documentation/networking/device_drivers/ethernet/index.rst
+++ b/Documentation/networking/device_drivers/ethernet/index.rst
@@ -48,6 +48,7 @@ Contents:
meta/fbnic
microsoft/netvsc
mucse/rnpgbe
+ nebula-matrix/nbl
netronome/nfp
pensando/ionic
pensando/ionic_rdma
diff --git a/Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst b/Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
new file mode 100644
index 000000000000..10feb5f37c04
--- /dev/null
+++ b/Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
@@ -0,0 +1,27 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================================================
+Linux Base Driver for Nebula-matrix M18000-NIC family
+=====================================================
+
+Overview:
+=========
+M18000-NIC is a series of network interface cards for the Data Center Area.
+
+The driver supports link-speed 100GbE/25GE/10GE.
+
+M18000-NIC devices support MSI-X interrupt vector for each Tx/Rx queue and
+interrupt moderation.
+
+M18000-NIC devices support also various offload features such as checksum offload,
+Receive-Side Scaling(RSS).
+
+Support
+=======
+
+For more information about M18000-NIC, please visit the following URL:
+https://www.nebula-matrix.com/
+
+If an issue is identified with the released source code on the supported kernel
+with a supported adapter, email the specific information related to the issue to
+open@nebula-matrix.com.
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d1e6d3acbac..0f2e7b6bd089 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18209,6 +18209,16 @@ F: Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml
F: Documentation/hwmon/nct7363.rst
F: drivers/hwmon/nct7363.c
+NEBULA-MATRIX ETHERNET DRIVER (nebula-matrix)
+M: Illusion Wang <illusion.wang@nebula-matrix.com>
+M: Dimon Zhao <dimon.zhao@nebula-matrix.com>
+M: Alvin Wang <alvin.wang@nebula-matrix.com>
+M: Sam Chen <sam.chen@nebula-matrix.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/networking/device_drivers/ethernet/nebula-matrix/
+F: drivers/net/ethernet/nebula-matrix/
+
NETCONSOLE
M: Breno Leitao <leitao@debian.org>
S: Maintained
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index bdc29d143160..def67e8a35a9 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -130,6 +130,7 @@ config FEALNX
source "drivers/net/ethernet/ni/Kconfig"
source "drivers/net/ethernet/natsemi/Kconfig"
+source "drivers/net/ethernet/nebula-matrix/Kconfig"
source "drivers/net/ethernet/netronome/Kconfig"
source "drivers/net/ethernet/8390/Kconfig"
source "drivers/net/ethernet/nvidia/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 6bffb60ba644..44ce1cbba2ef 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_NET_VENDOR_MUCSE) += mucse/
obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/
obj-$(CONFIG_FEALNX) += fealnx.o
obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/
+obj-$(CONFIG_NET_VENDOR_NEBULA_MATRIX) += nebula-matrix/
obj-$(CONFIG_NET_VENDOR_NETRONOME) += netronome/
obj-$(CONFIG_NET_VENDOR_NI) += ni/
obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/
diff --git a/drivers/net/ethernet/nebula-matrix/Kconfig b/drivers/net/ethernet/nebula-matrix/Kconfig
new file mode 100644
index 000000000000..9c8b4cf13b48
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/Kconfig
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Nebula-matrix network device configuration
+#
+
+config NET_VENDOR_NEBULA_MATRIX
+ bool "Nebula-matrix devices"
+ default y
+ help
+ If you have a network (Ethernet) card belonging to this class, say Y.
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Nebula-matrix cards. If you say Y, you will be asked
+ for your specific card in the following questions.
+
+if NET_VENDOR_NEBULA_MATRIX
+
+config NBL
+ tristate "Nebula-matrix Ethernet Controller m18110/m18000 support"
+ depends on PCI && (64BIT || COMPILE_TEST)
+ help
+ This driver supports Nebula-matrix Ethernet Controller m18110/m18000
+ Family of devices. For more information about this product, go to
+ the product description with smart NIC:
+
+ <http://www.nebula-matrix.com>
+
+ More specific information on configuring the driver is in
+ <file:Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst>.
+
+ To compile this driver as a module, choose M here. The module
+ will be called nbl.
+
+endif # NET_VENDOR_NEBULA_MATRIX
diff --git a/drivers/net/ethernet/nebula-matrix/Makefile b/drivers/net/ethernet/nebula-matrix/Makefile
new file mode 100644
index 000000000000..42cdf2db8f0c
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the Nebula-matrix network device drivers.
+#
+
+obj-$(CONFIG_NBL) += nbl/
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
new file mode 100644
index 000000000000..b90fba239401
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2025 Nebula Matrix Limited.
+
+obj-$(CONFIG_NBL) := nbl.o
+
+nbl-objs += nbl_main.o
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
new file mode 100644
index 000000000000..c525114297b4
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_CORE_H_
+#define _NBL_CORE_H_
+
+enum {
+ NBL_CAP_HAS_CTRL_BIT,
+ NBL_CAP_HAS_NET_BIT,
+ NBL_CAP_IS_NIC_BIT,
+ NBL_CAP_IS_LEONIS_BIT,
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
new file mode 100644
index 000000000000..1046e6517b15
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_INCLUDE_H_
+#define _NBL_INCLUDE_H_
+
+#include <linux/types.h>
+
+/* ------ Basic definitions ------- */
+#define NBL_DRIVER_NAME "nbl"
+
+struct nbl_func_caps {
+ u32 has_ctrl:1;
+ u32 has_net:1;
+ u32 is_nic:1;
+ u32 rsv:29;
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
new file mode 100644
index 000000000000..10c3536b327b
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#include <linux/device.h>
+#include <linux/pci.h>
+#include <linux/module.h>
+#include "nbl_include/nbl_include.h"
+#include "nbl_core.h"
+
+static int nbl_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ return 0;
+}
+
+static void nbl_remove(struct pci_dev *pdev)
+{
+}
+
+/*
+ * PCI Device IDs for Leonis/NBL Network Controllers
+ *
+ * Vendor ID: 0x1F0F
+ * SNIC v3r1 product Device IDs range: 0x3403-0x3412
+ */
+#define NBL_VENDOR_ID 0x1F0F
+
+#define NBL_DEVICE_ID_M18110 0x3403
+#define NBL_DEVICE_ID_M18110_LX 0x3404
+#define NBL_DEVICE_ID_M18110_BASE_T 0x3405
+#define NBL_DEVICE_ID_M18110_LX_BASE_T 0x3406
+#define NBL_DEVICE_ID_M18110_OCP 0x3407
+#define NBL_DEVICE_ID_M18110_LX_OCP 0x3408
+#define NBL_DEVICE_ID_M18110_BASE_T_OCP 0x3409
+#define NBL_DEVICE_ID_M18110_LX_BASE_T_OCP 0x340a
+#define NBL_DEVICE_ID_M18000 0x340b
+#define NBL_DEVICE_ID_M18000_LX 0x340c
+#define NBL_DEVICE_ID_M18000_BASE_T 0x340d
+#define NBL_DEVICE_ID_M18000_LX_BASE_T 0x340e
+#define NBL_DEVICE_ID_M18000_OCP 0x340f
+#define NBL_DEVICE_ID_M18000_LX_OCP 0x3410
+#define NBL_DEVICE_ID_M18000_BASE_T_OCP 0x3411
+#define NBL_DEVICE_ID_M18000_LX_BASE_T_OCP 0x3412
+
+static const struct pci_device_id nbl_id_table[] = {
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_BASE_T),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_BASE_T_OCP),
+ .driver_data = BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) |
+ BIT(NBL_CAP_IS_LEONIS_BIT) },
+ /* required as sentinel */
+ {
+ 0,
+ }
+};
+MODULE_DEVICE_TABLE(pci, nbl_id_table);
+
+static struct pci_driver nbl_driver = {
+ .name = NBL_DRIVER_NAME,
+ .id_table = nbl_id_table,
+ .probe = nbl_probe,
+ .remove = nbl_remove,
+};
+
+module_pci_driver(nbl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Nebula Matrix Network Driver");
--
2.47.3
^ permalink raw reply related
* [PATCH v11 net-next 07/11] net/nebula-matrix: add intr resource implementation
From: illusion.wang @ 2026-04-08 9:37 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, linux-doc, lorenzo, pabeni, horms,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260408093739.56001-1-illusion.wang@nebula-matrix.com>
MSI-X Interrupt Configuration:
Dynamically allocate and manage MSI-X interrupt vectors, including
network interrupts and other types of interrupts.
Interrupt Mapping Table Management: Maintain the MSI-X mapping table
(msix_map_table) to establish interrupt associations between hardware
and software.
Interrupt Enabling/Disabling:
Support enabling or disabling specific interrupts through hardware
operations.
Interrupt Information Query: Provide interfaces to obtain the
hardware register addresses and data of interrupts.
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../net/ethernet/nebula-matrix/nbl/Makefile | 1 +
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 71 +++++
.../nbl_hw_leonis/nbl_resource_leonis.c | 13 +
.../nebula-matrix/nbl/nbl_hw/nbl_interrupt.c | 246 ++++++++++++++++++
.../nebula-matrix/nbl/nbl_hw/nbl_interrupt.h | 12 +
.../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 33 +++
.../nbl/nbl_include/nbl_include.h | 2 +
7 files changed, 378 insertions(+)
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
index b03c20f9988e..a56e722a5ac7 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -9,6 +9,7 @@ nbl-objs += nbl_common/nbl_common.o \
nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \
nbl_hw/nbl_resource.o \
+ nbl_hw/nbl_interrupt.o \
nbl_core/nbl_dispatch.o \
nbl_core/nbl_dev.o \
nbl_main.o
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
index 4ef0d5989a76..aa5e91c2b278 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
@@ -63,6 +63,73 @@ static void nbl_hw_wr_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, const u32 *data,
spin_unlock(&hw_mgt->reg_lock);
}
+static void nbl_hw_enable_mailbox_irq(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool enable_msix, u16 global_vec_id)
+{
+ struct nbl_mailbox_qinfo_map_table mb_qinfo_map = { 0 };
+
+ nbl_hw_rd_regs(hw_mgt, NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id),
+ (u32 *)&mb_qinfo_map, sizeof(mb_qinfo_map));
+
+ if (enable_msix) {
+ mb_qinfo_map.msix_idx = global_vec_id;
+ mb_qinfo_map.msix_idx_valid = 1;
+ } else {
+ mb_qinfo_map.msix_idx = 0;
+ mb_qinfo_map.msix_idx_valid = 0;
+ }
+
+ nbl_hw_wr_regs(hw_mgt, NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id),
+ (u32 *)&mb_qinfo_map, sizeof(mb_qinfo_map));
+}
+
+static void nbl_hw_configure_msix_map(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool valid, dma_addr_t dma_addr, u8 bus,
+ u8 devid, u8 function)
+{
+ struct nbl_function_msix_map function_msix_map = { 0 };
+
+ if (valid) {
+ function_msix_map.msix_map_base_addr = dma_addr;
+ /* use af's bdf, because dma memmory is alloc by af */
+ function_msix_map.function = function;
+ function_msix_map.devid = devid;
+ function_msix_map.bus = bus;
+ function_msix_map.valid = 1;
+ }
+
+ nbl_hw_wr_regs(hw_mgt,
+ NBL_PCOMPLETER_FUNCTION_MSIX_MAP_REG_ARR(func_id),
+ (u32 *)&function_msix_map, sizeof(function_msix_map));
+}
+
+static void nbl_hw_configure_msix_info(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool valid, u16 interrupt_id, u8 bus,
+ u8 devid, u8 function, bool msix_mask_en)
+{
+ struct nbl_pcompleter_host_msix_fid_table host_msix_fid_tbl = { 0 };
+ struct nbl_host_msix_info msix_info = { 0 };
+
+ if (valid) {
+ host_msix_fid_tbl.vld = 1;
+ host_msix_fid_tbl.fid = func_id;
+
+ msix_info.intrl_pnum = 0;
+ msix_info.intrl_rate = 0;
+ msix_info.function = function;
+ msix_info.devid = devid;
+ msix_info.bus = bus;
+ msix_info.valid = 1;
+ if (msix_mask_en)
+ msix_info.msix_mask_en = 1;
+ }
+
+ nbl_hw_wr_regs(hw_mgt, NBL_PADPT_HOST_MSIX_INFO_REG_ARR(interrupt_id),
+ (u32 *)&msix_info, sizeof(msix_info));
+ nbl_hw_wr_regs(hw_mgt, NBL_PCOMPLETER_HOST_MSIX_FID_TABLE(interrupt_id),
+ (u32 *)&host_msix_fid_tbl, sizeof(host_msix_fid_tbl));
+}
+
static void nbl_hw_update_mailbox_queue_tail_ptr(struct nbl_hw_mgt *hw_mgt,
u16 tail_ptr, u8 txrx)
{
@@ -195,6 +262,9 @@ static u32 nbl_hw_get_fw_eth_map(struct nbl_hw_mgt *hw_mgt)
}
static struct nbl_hw_ops hw_ops = {
+ .configure_msix_map = nbl_hw_configure_msix_map,
+ .configure_msix_info = nbl_hw_configure_msix_info,
+
.update_mailbox_queue_tail_ptr = nbl_hw_update_mailbox_queue_tail_ptr,
.config_mailbox_rxq = nbl_hw_config_mailbox_rxq,
.config_mailbox_txq = nbl_hw_config_mailbox_txq,
@@ -204,6 +274,7 @@ static struct nbl_hw_ops hw_ops = {
.get_real_bus = nbl_hw_get_real_bus,
.cfg_mailbox_qinfo = nbl_hw_cfg_mailbox_qinfo,
+ .enable_mailbox_irq = nbl_hw_enable_mailbox_irq,
.get_fw_eth_num = nbl_hw_get_fw_eth_num,
.get_fw_eth_map = nbl_hw_get_fw_eth_map,
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
index 9908189bc3f6..a9b1167b38d9 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
@@ -12,6 +12,7 @@ static struct nbl_resource_ops res_ops = {
.get_eth_id = nbl_res_get_eth_id,
};
+static bool is_ops_inited;
static struct nbl_resource_mgt *
nbl_res_setup_res_mgt(struct nbl_common_info *common)
{
@@ -37,11 +38,19 @@ static struct nbl_resource_ops_tbl *
nbl_res_setup_ops(struct device *dev, struct nbl_resource_mgt *res_mgt)
{
struct nbl_resource_ops_tbl *res_ops_tbl;
+ int ret;
res_ops_tbl = devm_kzalloc(dev, sizeof(*res_ops_tbl), GFP_KERNEL);
if (!res_ops_tbl)
return ERR_PTR(-ENOMEM);
+ if (!is_ops_inited) {
+ ret = nbl_intr_setup_ops(&res_ops);
+ if (ret)
+ return ERR_PTR(-ENOMEM);
+ is_ops_inited = true;
+ }
+
res_ops_tbl->ops = &res_ops;
res_ops_tbl->priv = res_mgt;
@@ -204,6 +213,10 @@ static int nbl_res_start(struct nbl_resource_mgt *res_mgt)
ret = nbl_res_ctrl_dev_vsi_info_init(res_mgt);
if (ret)
return ret;
+
+ ret = nbl_intr_mgt_start(res_mgt);
+ if (ret)
+ return ret;
}
return 0;
}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c
new file mode 100644
index 000000000000..92a6fff5523e
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include "nbl_interrupt.h"
+
+static int nbl_res_intr_destroy_msix_map(struct nbl_resource_mgt *res_mgt,
+ u16 func_id)
+{
+ struct nbl_interrupt_mgt *intr_mgt = res_mgt->intr_mgt;
+ struct nbl_hw_ops *hw_ops = res_mgt->hw_ops_tbl->ops;
+ struct device *dev = res_mgt->common->dev;
+ struct nbl_msix_map_table *msix_map_table;
+ u16 *interrupts;
+ u16 intr_num, i;
+
+ /* use ctrl dev bdf */
+ hw_ops->configure_msix_map(res_mgt->hw_ops_tbl->priv, func_id, false, 0,
+ 0, 0, 0);
+
+ intr_num = intr_mgt->func_intr_res[func_id].num_interrupts;
+ interrupts = intr_mgt->func_intr_res[func_id].interrupts;
+
+ if (!interrupts) {
+ dev_err(dev, "No interrupts to clr for func_id %u\n", func_id);
+ return -EINVAL;
+ }
+ for (i = 0; i < intr_num; i++) {
+ if (interrupts[i] >= NBL_MAX_OTHER_INTERRUPT)
+ clear_bit(interrupts[i] - NBL_MAX_OTHER_INTERRUPT,
+ intr_mgt->interrupt_net_bitmap);
+ else
+ clear_bit(interrupts[i],
+ intr_mgt->interrupt_others_bitmap);
+
+ hw_ops->configure_msix_info(res_mgt->hw_ops_tbl->priv, func_id,
+ false, interrupts[i], 0, 0, 0,
+ false);
+ }
+
+ kfree(interrupts);
+ intr_mgt->func_intr_res[func_id].interrupts = NULL;
+ intr_mgt->func_intr_res[func_id].num_interrupts = 0;
+
+ msix_map_table = &intr_mgt->func_intr_res[func_id].msix_map_table;
+ dma_free_coherent(dev, msix_map_table->size, msix_map_table->base_addr,
+ msix_map_table->dma);
+ msix_map_table->size = 0;
+ msix_map_table->base_addr = NULL;
+ msix_map_table->dma = 0;
+
+ return 0;
+}
+
+static int nbl_res_intr_configure_msix_map(struct nbl_resource_mgt *res_mgt,
+ u16 func_id, u16 num_net_msix,
+ u16 num_others_msix,
+ bool net_msix_mask_en)
+{
+ struct nbl_interrupt_mgt *intr_mgt = res_mgt->intr_mgt;
+ struct nbl_hw_ops *hw_ops = res_mgt->hw_ops_tbl->ops;
+ struct nbl_common_info *common = res_mgt->common;
+ struct nbl_msix_map_table *msix_map_table;
+ struct nbl_msix_map *msix_map_entries;
+ struct device *dev = common->dev;
+ u16 requested, intr_index;
+ u8 bus, devid, function;
+ bool msix_mask_en;
+ u16 *interrupts;
+ int ret = 0;
+ u16 i;
+
+ requested = num_net_msix + num_others_msix;
+ if (requested > NBL_MSIX_MAP_TABLE_MAX_ENTRIES)
+ return -EINVAL;
+ if (intr_mgt->func_intr_res[func_id].interrupts)
+ nbl_res_intr_destroy_msix_map(res_mgt, func_id);
+
+ ret = nbl_res_func_id_to_bdf(res_mgt, func_id, &bus, &devid, &function);
+ if (ret == U32_MAX)
+ return -EINVAL;
+
+ msix_map_table = &intr_mgt->func_intr_res[func_id].msix_map_table;
+ WARN_ON(msix_map_table->base_addr);
+ msix_map_table->size =
+ sizeof(struct nbl_msix_map) * NBL_MSIX_MAP_TABLE_MAX_ENTRIES;
+ msix_map_table->base_addr = dma_alloc_coherent(dev,
+ msix_map_table->size,
+ &msix_map_table->dma,
+ GFP_KERNEL);
+ if (!msix_map_table->base_addr) {
+ dev_err(dev, "Allocate DMA memory for function msix map table failed\n");
+ msix_map_table->size = 0;
+ return -ENOMEM;
+ }
+
+ interrupts = kcalloc(requested, sizeof(interrupts[0]), GFP_KERNEL);
+ if (!interrupts) {
+ ret = -ENOMEM;
+ goto alloc_interrupts_err;
+ }
+
+ intr_mgt->func_intr_res[func_id].interrupts = interrupts;
+ intr_mgt->func_intr_res[func_id].num_interrupts = requested;
+ intr_mgt->func_intr_res[func_id].num_net_interrupts = num_net_msix;
+
+ for (i = 0; i < num_net_msix; i++) {
+ intr_index = find_first_zero_bit(intr_mgt->interrupt_net_bitmap,
+ NBL_MAX_NET_INTERRUPT);
+ if (intr_index == NBL_MAX_NET_INTERRUPT) {
+ dev_err(dev, "There is no available interrupt left\n");
+ ret = -EAGAIN;
+ goto get_interrupt_err;
+ }
+ interrupts[i] = intr_index + NBL_MAX_OTHER_INTERRUPT;
+ set_bit(intr_index, intr_mgt->interrupt_net_bitmap);
+ }
+
+ for (i = num_net_msix; i < requested; i++) {
+ intr_index =
+ find_first_zero_bit(intr_mgt->interrupt_others_bitmap,
+ NBL_MAX_OTHER_INTERRUPT);
+ if (intr_index == NBL_MAX_OTHER_INTERRUPT) {
+ dev_err(dev, "There is no available interrupt left\n");
+ ret = -EAGAIN;
+ goto get_interrupt_err;
+ }
+ interrupts[i] = intr_index;
+ set_bit(intr_index, intr_mgt->interrupt_others_bitmap);
+ }
+
+ msix_map_entries = msix_map_table->base_addr;
+ for (i = 0; i < requested; i++) {
+ msix_map_entries[i].global_msix_index = interrupts[i];
+ msix_map_entries[i].valid = 1;
+
+ if (i < num_net_msix && net_msix_mask_en)
+ msix_mask_en = 1;
+ else
+ msix_mask_en = 0;
+ hw_ops->configure_msix_info(res_mgt->hw_ops_tbl->priv, func_id,
+ true, interrupts[i], bus, devid,
+ function, msix_mask_en);
+ }
+
+ /* use ctrl dev bdf */
+ hw_ops->configure_msix_map(res_mgt->hw_ops_tbl->priv, func_id, true,
+ msix_map_table->dma, common->hw_bus,
+ common->devid, common->function);
+
+ return 0;
+
+get_interrupt_err:
+ while (i--) {
+ intr_index = interrupts[i];
+ if (intr_index >= NBL_MAX_OTHER_INTERRUPT)
+ clear_bit(intr_index - NBL_MAX_OTHER_INTERRUPT,
+ intr_mgt->interrupt_net_bitmap);
+ else
+ clear_bit(intr_index,
+ intr_mgt->interrupt_others_bitmap);
+ }
+ kfree(interrupts);
+ intr_mgt->func_intr_res[func_id].num_interrupts = 0;
+ intr_mgt->func_intr_res[func_id].interrupts = NULL;
+
+alloc_interrupts_err:
+ dma_free_coherent(dev, msix_map_table->size, msix_map_table->base_addr,
+ msix_map_table->dma);
+ msix_map_table->size = 0;
+ msix_map_table->base_addr = NULL;
+ msix_map_table->dma = 0;
+
+ return ret;
+}
+
+static int nbl_res_intr_enable_mailbox_irq(struct nbl_resource_mgt *res_mgt,
+ u16 func_id, u16 vector_id,
+ bool enable_msix)
+{
+ struct nbl_interrupt_mgt *intr_mgt = res_mgt->intr_mgt;
+ struct nbl_hw_ops *hw_ops = res_mgt->hw_ops_tbl->ops;
+ u16 global_vec_id;
+
+ global_vec_id = intr_mgt->func_intr_res[func_id].interrupts[vector_id];
+ hw_ops->enable_mailbox_irq(res_mgt->hw_ops_tbl->priv, func_id,
+ enable_msix, global_vec_id);
+
+ return 0;
+}
+
+/* NBL_INTR_SET_OPS(ops_name, func)
+ *
+ * Use X Macros to reduce setup and remove codes.
+ */
+#define NBL_INTR_OPS_TBL \
+do { \
+ NBL_INTR_SET_OPS(configure_msix_map, \
+ nbl_res_intr_configure_msix_map); \
+ NBL_INTR_SET_OPS(destroy_msix_map, \
+ nbl_res_intr_destroy_msix_map); \
+ NBL_INTR_SET_OPS(enable_mailbox_irq, \
+ nbl_res_intr_enable_mailbox_irq); \
+} while (0)
+
+/* Structure starts here, adding an op should not modify anything below */
+static struct nbl_interrupt_mgt *nbl_intr_setup_mgt(struct device *dev)
+{
+ struct nbl_interrupt_mgt *intr_mgt;
+
+ intr_mgt = devm_kzalloc(dev, sizeof(*intr_mgt), GFP_KERNEL);
+ if (!intr_mgt)
+ return ERR_PTR(-ENOMEM);
+
+ return intr_mgt;
+}
+
+int nbl_intr_mgt_start(struct nbl_resource_mgt *res_mgt)
+{
+ struct device *dev = res_mgt->common->dev;
+ struct nbl_interrupt_mgt *intr_mgt;
+ int ret;
+
+ intr_mgt = nbl_intr_setup_mgt(dev);
+ if (IS_ERR(intr_mgt)) {
+ ret = PTR_ERR(intr_mgt);
+ return ret;
+ }
+ res_mgt->intr_mgt = intr_mgt;
+ return 0;
+}
+
+int nbl_intr_setup_ops(struct nbl_resource_ops *res_ops)
+{
+#define NBL_INTR_SET_OPS(name, func) \
+ do { \
+ res_ops->NBL_NAME(name) = func; \
+ ; \
+ } while (0)
+ NBL_INTR_OPS_TBL;
+#undef NBL_INTR_SET_OPS
+
+ return 0;
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h
new file mode 100644
index 000000000000..b876bf30084b
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_INTERRUPT_H_
+#define _NBL_INTERRUPT_H_
+
+#include "nbl_resource.h"
+
+#define NBL_MSIX_MAP_TABLE_MAX_ENTRIES 1024
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
index 51b5b958cde8..1b80676cf19a 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
@@ -18,6 +18,37 @@
struct nbl_resource_mgt;
+/* --------- INTERRUPT ---------- */
+#define NBL_MAX_OTHER_INTERRUPT 1024
+#define NBL_MAX_NET_INTERRUPT 4096
+
+struct nbl_msix_map {
+ u16 valid:1;
+ u16 global_msix_index:13;
+ u16 rsv:2;
+};
+
+struct nbl_msix_map_table {
+ struct nbl_msix_map *base_addr;
+ dma_addr_t dma;
+ size_t size;
+};
+
+struct nbl_func_interrupt_resource_mng {
+ u16 num_interrupts;
+ u16 num_net_interrupts;
+ u16 msix_base;
+ u16 msix_max;
+ u16 *interrupts;
+ struct nbl_msix_map_table msix_map_table;
+};
+
+struct nbl_interrupt_mgt {
+ DECLARE_BITMAP(interrupt_net_bitmap, NBL_MAX_NET_INTERRUPT);
+ DECLARE_BITMAP(interrupt_others_bitmap, NBL_MAX_OTHER_INTERRUPT);
+ struct nbl_func_interrupt_resource_mng func_intr_res[NBL_MAX_FUNC];
+};
+
/* --------- INFO ---------- */
struct nbl_sriov_info {
unsigned int bdf;
@@ -77,6 +108,8 @@ int nbl_res_func_id_to_bdf(struct nbl_resource_mgt *res_mgt, u16 func_id,
u8 *bus, u8 *dev, u8 *function);
void nbl_res_get_eth_id(struct nbl_resource_mgt *res_mgt, u16 vsi_id,
u8 *eth_mode, u8 *eth_id, u8 *logic_eth_id);
+int nbl_intr_mgt_start(struct nbl_resource_mgt *res_mgt);
+int nbl_intr_setup_ops(struct nbl_resource_ops *resource_ops);
void nbl_res_pf_dev_vsi_type_to_hw_vsi_type(u16 src_type,
enum nbl_vsi_serv_type *dst_type);
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
index 6a0bf5e8ca32..e4f11e6ded94 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -19,6 +19,8 @@
#define NBL_MAX_FUNC 520
#define NBL_MAX_ETHERNET 4
+/* Used for macros to pass checkpatch */
+#define NBL_NAME(x) x
enum nbl_product_type {
NBL_LEONIS_TYPE,
--
2.47.3
^ permalink raw reply related
* [PATCH v11 net-next 05/11] net/nebula-matrix: add channel layer
From: illusion.wang @ 2026-04-08 9:37 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, linux-doc, lorenzo, pabeni, horms,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260408093739.56001-1-illusion.wang@nebula-matrix.com>
a channel management layer provides structured approach to handle
communication between different components and drivers. Here's a summary
of its key functionalities:
1. Message Handling Framework
Message Registration/Unregistration: Functions (nbl_chan_register_msg,
nbl_chan_unregister_msg) allow dynamic registration of message handlers
for specific message types, enabling extensible communication protocols.
Message Sending/Acknowledgment: Core functions (nbl_chan_send_msg,
nbl_chan_send_ack) handle message transmission, including asynchronous
operations with acknowledgment (ACK) support.
Received ACKs are processed via nbl_chan_recv_ack_msg.
Hash-Based Handler Lookup: A hash table (handle_hash_tbl) stores message
handlers for efficient O(1) lookup by message type.
2. Channel Types and Queue Management
Mailbox Channel: For direct communication between PF0 and Other PF.
Queue Initialization/Teardown: Functions (nbl_chan_init_queue,
nbl_chan_teardown_queue) manage transmit (TX) and receive (RX) queues.
Queue Configuration: Hardware-specific queue parameters (e.g., buffer
sizes, entry counts) are set via nbl_chan_config_queue, with hardware
interactions delegated to hw_ops.
3. Hardware Abstraction Layer (HW Ops)
Hardware-Specific Operations: The nbl_hw_ops structure abstracts
hardware interactions: queue configuration (config_mailbox_txq/rxq),
tail pointer updates(update_mailbox_queue_tail_ptr).
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../net/ethernet/nebula-matrix/nbl/Makefile | 3 +-
.../nbl/nbl_channel/nbl_channel.c | 771 +++++++++++++++++-
.../nbl/nbl_channel/nbl_channel.h | 134 +++
.../nebula-matrix/nbl/nbl_common/nbl_common.c | 212 +++++
.../nebula-matrix/nbl/nbl_common/nbl_common.h | 34 +
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 143 ++++
.../nbl/nbl_include/nbl_def_channel.h | 87 ++
.../nbl/nbl_include/nbl_def_common.h | 30 +
.../nbl/nbl_include/nbl_def_hw.h | 28 +
.../nbl/nbl_include/nbl_include.h | 6 +
10 files changed, 1444 insertions(+), 4 deletions(-)
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
index 63116d1d7043..c9bc060732e7 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -3,7 +3,8 @@
obj-$(CONFIG_NBL) := nbl.o
-nbl-objs += nbl_channel/nbl_channel.o \
+nbl-objs += nbl_common/nbl_common.o \
+ nbl_channel/nbl_channel.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
index c1b724a8b92d..85072c20f260 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
@@ -2,12 +2,757 @@
/*
* Copyright (c) 2025 Nebula Matrix Limited.
*/
-
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/pci.h>
+#include <linux/bits.h>
+#include <linux/dma-mapping.h>
#include "nbl_channel.h"
+static int nbl_chan_add_msg_handler(struct nbl_channel_mgt *chan_mgt,
+ u16 msg_type, nbl_chan_resp func,
+ void *priv)
+{
+ struct nbl_chan_msg_node_data handler = { 0 };
+ int ret;
+
+ handler.func = func;
+ handler.priv = priv;
+ ret = nbl_common_alloc_hash_node(chan_mgt->handle_hash_tbl, &msg_type,
+ &handler, NULL);
+
+ return ret;
+}
+
+static int nbl_chan_init_msg_handler(struct nbl_channel_mgt *chan_mgt)
+{
+ struct nbl_common_info *common = chan_mgt->common;
+ struct nbl_hash_tbl_key tbl_key;
+
+ tbl_key.dev = common->dev;
+ tbl_key.key_size = sizeof(u16);
+ tbl_key.data_size = sizeof(struct nbl_chan_msg_node_data);
+ tbl_key.bucket_size = NBL_CHAN_HANDLER_TBL_BUCKET_SIZE;
+
+ chan_mgt->handle_hash_tbl = nbl_common_init_hash_table(&tbl_key);
+ if (!chan_mgt->handle_hash_tbl)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void nbl_chan_remove_msg_handler(struct nbl_channel_mgt *chan_mgt)
+{
+ nbl_common_remove_hash_table(chan_mgt->handle_hash_tbl, NULL);
+
+ chan_mgt->handle_hash_tbl = NULL;
+}
+
+static void nbl_chan_init_queue_param(struct nbl_chan_info *chan_info,
+ u16 num_txq_entries, u16 num_rxq_entries,
+ u16 txq_buf_size, u16 rxq_buf_size)
+{
+ mutex_init(&chan_info->txq_lock);
+ chan_info->num_txq_entries = num_txq_entries;
+ chan_info->num_rxq_entries = num_rxq_entries;
+ chan_info->txq_buf_size = txq_buf_size;
+ chan_info->rxq_buf_size = rxq_buf_size;
+}
+
+static int nbl_chan_init_tx_queue(struct nbl_common_info *common,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct device *dev = common->dev;
+ size_t size =
+ chan_info->num_txq_entries * sizeof(struct nbl_chan_tx_desc);
+
+ txq->desc.tx_desc = dmam_alloc_coherent(dev, size, &txq->dma,
+ GFP_KERNEL);
+ if (!txq->desc.tx_desc)
+ return -ENOMEM;
+
+ chan_info->wait = devm_kcalloc(dev, chan_info->num_txq_entries,
+ sizeof(*chan_info->wait),
+ GFP_KERNEL);
+ if (!chan_info->wait)
+ return -ENOMEM;
+
+ txq->buf = devm_kcalloc(dev, chan_info->num_txq_entries,
+ sizeof(*txq->buf), GFP_KERNEL);
+ if (!txq->buf)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int nbl_chan_init_rx_queue(struct nbl_common_info *common,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *rxq = &chan_info->rxq;
+ struct device *dev = common->dev;
+ size_t size =
+ chan_info->num_rxq_entries * sizeof(struct nbl_chan_rx_desc);
+
+ rxq->desc.rx_desc = dmam_alloc_coherent(dev, size, &rxq->dma,
+ GFP_KERNEL);
+ if (!rxq->desc.rx_desc) {
+ dev_err(dev,
+ "Allocate DMA for chan rx descriptor ring failed\n");
+ return -ENOMEM;
+ }
+
+ rxq->buf = devm_kcalloc(dev, chan_info->num_rxq_entries,
+ sizeof(*rxq->buf), GFP_KERNEL);
+ if (!rxq->buf)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int nbl_chan_init_queue(struct nbl_common_info *common,
+ struct nbl_chan_info *chan_info)
+{
+ int err;
+
+ err = nbl_chan_init_tx_queue(common, chan_info);
+ if (err)
+ return err;
+
+ err = nbl_chan_init_rx_queue(common, chan_info);
+
+ return err;
+}
+
+static void nbl_chan_config_queue(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info, bool tx)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_hw_mgt *p = chan_mgt->hw_ops_tbl->priv;
+ int size_bwid;
+ struct nbl_chan_ring *ring;
+ dma_addr_t dma_addr;
+
+ if (tx)
+ ring = &chan_info->txq;
+ else
+ ring = &chan_info->rxq;
+ dma_addr = ring->dma;
+ if (tx) {
+ size_bwid = ilog2(chan_info->num_txq_entries);
+ hw_ops->config_mailbox_txq(p, dma_addr, size_bwid);
+ } else {
+ size_bwid = ilog2(chan_info->num_rxq_entries);
+ hw_ops->config_mailbox_rxq(p, dma_addr, size_bwid);
+ }
+}
+
+static int nbl_chan_alloc_all_tx_bufs(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_buf *buf;
+ u16 i;
+
+ for (i = 0; i < chan_info->num_txq_entries; i++) {
+ buf = &txq->buf[i];
+ buf->va = dmam_alloc_coherent(dev, chan_info->txq_buf_size,
+ &buf->pa,
+ GFP_KERNEL);
+ if (!buf->va) {
+ dev_err(dev,
+ "Allocate buffer for chan tx queue failed\n");
+ return -ENOMEM;
+ }
+ }
+
+ txq->next_to_clean = 0;
+ txq->next_to_use = 0;
+ txq->tail_ptr = 0;
+
+ return 0;
+}
+
+static int
+nbl_chan_cfg_mailbox_qinfo_map_table(struct nbl_channel_mgt *chan_mgt)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_common_info *common = chan_mgt->common;
+ struct nbl_hw_mgt *p = chan_mgt->hw_ops_tbl->priv;
+ u16 func_id;
+ u32 pf_mask;
+
+ pf_mask = hw_ops->get_host_pf_mask(p);
+ for (func_id = 0; func_id < NBL_MAX_PF; func_id++) {
+ if (!(pf_mask & (1 << func_id)))
+ hw_ops->cfg_mailbox_qinfo(p, func_id, common->hw_bus,
+ common->devid,
+ common->function + func_id);
+ }
+
+ return 0;
+}
+
+static int nbl_chan_cfg_qinfo_map_table(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type)
+{
+ return nbl_chan_cfg_mailbox_qinfo_map_table(chan_mgt);
+}
+
+#define NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, tail_ptr, qid)\
+do { \
+ (void)(chan_info); \
+ typeof(hw_ops) _hw_ops = (hw_ops); \
+ typeof(chan_mgt) _chan_mgt = (chan_mgt); \
+ typeof(tail_ptr) _tail_ptr = (tail_ptr); \
+ typeof(qid) _qid = (qid); \
+ (_hw_ops)->update_mailbox_queue_tail_ptr( \
+ _chan_mgt->hw_ops_tbl->priv, _tail_ptr, _qid); \
+} while (0)
+
+static int nbl_chan_alloc_all_rx_bufs(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_chan_ring *rxq = &chan_info->rxq;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_rx_desc *desc;
+ struct nbl_chan_buf *buf;
+ u16 i;
+
+ for (i = 0; i < chan_info->num_rxq_entries; i++) {
+ buf = &rxq->buf[i];
+ buf->va = dmam_alloc_coherent(dev, chan_info->rxq_buf_size,
+ &buf->pa,
+ GFP_KERNEL);
+ if (!buf->va) {
+ dev_err(dev,
+ "Allocate buffer for chan rx queue failed\n");
+ goto err;
+ }
+ }
+
+ desc = rxq->desc.rx_desc;
+ for (i = 0; i < chan_info->num_rxq_entries - 1; i++) {
+ buf = &rxq->buf[i];
+ desc[i].flags = BIT(NBL_CHAN_RX_DESC_AVAIL);
+ desc[i].buf_addr = buf->pa;
+ desc[i].buf_len = chan_info->rxq_buf_size;
+ }
+
+ rxq->next_to_clean = 0;
+ rxq->next_to_use = chan_info->num_rxq_entries - 1;
+ rxq->tail_ptr = chan_info->num_rxq_entries - 1;
+
+ NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, rxq->tail_ptr,
+ NBL_MB_RX_QID);
+
+ return 0;
+err:
+ return -ENOMEM;
+}
+
+static int nbl_chan_alloc_all_bufs(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ int err;
+
+ err = nbl_chan_alloc_all_tx_bufs(chan_mgt, chan_info);
+ if (err)
+ return err;
+ err = nbl_chan_alloc_all_rx_bufs(chan_mgt, chan_info);
+
+ return err;
+}
+
+static void nbl_chan_stop_queue(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+
+ hw_ops->stop_mailbox_rxq(chan_mgt->hw_ops_tbl->priv);
+ hw_ops->stop_mailbox_txq(chan_mgt->hw_ops_tbl->priv);
+}
+
+static int nbl_chan_teardown_queue(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ nbl_chan_stop_queue(chan_mgt, chan_info);
+
+ return 0;
+}
+
+static int nbl_chan_setup_queue(struct nbl_channel_mgt *chan_mgt, u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+ struct nbl_common_info *common = chan_mgt->common;
+ int err;
+
+ nbl_chan_init_queue_param(chan_info, NBL_CHAN_QUEUE_LEN,
+ NBL_CHAN_QUEUE_LEN, NBL_CHAN_BUF_LEN,
+ NBL_CHAN_BUF_LEN);
+ err = nbl_chan_init_queue(common, chan_info);
+ if (err)
+ return err;
+
+ nbl_chan_config_queue(chan_mgt, chan_info, true); /* tx */
+ nbl_chan_config_queue(chan_mgt, chan_info, false); /* rx */
+
+ err = nbl_chan_alloc_all_bufs(chan_mgt, chan_info);
+ if (err)
+ goto chan_q_setup_fail;
+
+ return 0;
+
+chan_q_setup_fail:
+ nbl_chan_teardown_queue(chan_mgt, chan_type);
+ return err;
+}
+
+static int nbl_chan_update_txqueue(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info,
+ struct nbl_chan_tx_param *param)
+{
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct nbl_chan_tx_desc *tx_desc =
+ NBL_CHAN_TX_RING_TO_DESC(txq, txq->next_to_use);
+ struct nbl_chan_buf *tx_buf =
+ NBL_CHAN_TX_RING_TO_BUF(txq, txq->next_to_use);
+
+ if (param->arg_len > NBL_CHAN_BUF_LEN - sizeof(*tx_desc))
+ return -EINVAL;
+
+ tx_desc->dstid = param->dstid;
+ tx_desc->msg_type = param->msg_type;
+ tx_desc->msgid = param->msgid;
+
+ if (param->arg_len > NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN) {
+ memcpy(tx_buf->va, param->arg, param->arg_len);
+ tx_desc->buf_addr = tx_buf->pa;
+ tx_desc->buf_len = param->arg_len;
+ tx_desc->data_len = 0;
+ } else {
+ memcpy(tx_desc->data, param->arg, param->arg_len);
+ tx_desc->buf_len = 0;
+ tx_desc->data_len = param->arg_len;
+ }
+ tx_desc->flags = BIT(NBL_CHAN_TX_DESC_AVAIL);
+
+ txq->next_to_use =
+ NBL_NEXT_ID(txq->next_to_use, chan_info->num_txq_entries - 1);
+ txq->tail_ptr++;
+
+ return 0;
+}
+
+static int nbl_chan_kick_tx_ring(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_chan_ring *txq = &chan_info->txq;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_tx_desc *tx_desc;
+ int i = 0;
+
+ NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, txq->tail_ptr,
+ NBL_MB_TX_QID);
+
+ tx_desc = NBL_CHAN_TX_RING_TO_DESC(txq, txq->next_to_clean);
+
+ while (!(tx_desc->flags & BIT(NBL_CHAN_TX_DESC_USED))) {
+ udelay(NBL_CHAN_TX_WAIT_US);
+ i++;
+
+ if (!(i % NBL_CHAN_TX_REKICK_WAIT_TIMES))
+ NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt,
+ txq->tail_ptr, NBL_MB_TX_QID);
+
+ if (i == NBL_CHAN_TX_WAIT_TIMES) {
+ dev_err(dev, "chan send message type: %d timeout\n",
+ tx_desc->msg_type);
+ return -ETIMEDOUT;
+ }
+ }
+
+ txq->next_to_clean = txq->next_to_use;
+
+ return 0;
+}
+
+static void nbl_chan_recv_ack_msg(void *priv, u16 srcid, u16 msgid, void *data,
+ u32 data_len)
+{
+ struct nbl_channel_mgt *chan_mgt = (struct nbl_channel_mgt *)priv;
+ struct nbl_chan_waitqueue_head *wait_head = NULL;
+ union nbl_chan_msg_id ack_msgid = { { 0 } };
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_info *chan_info =
+ chan_mgt->chan_info[NBL_CHAN_TYPE_MAILBOX];
+ u32 *payload = (u32 *)data;
+ u32 ack_datalen;
+ u32 copy_len;
+
+ if (data_len < NBL_CHAN_ACK_HEAD_LEN * sizeof(u32)) {
+ dev_err(dev, "Invalid ACK data_len: %u\n", data_len);
+ return;
+ }
+ ack_datalen = data_len - NBL_CHAN_ACK_HEAD_LEN * sizeof(u32);
+ ack_msgid.id = *(u16 *)(payload + NBL_CHAN_MSG_ID_POS);
+ if (ack_msgid.info.loc >= NBL_CHAN_QUEUE_LEN) {
+ dev_err(dev, "chan recv msg loc: %d err\n", ack_msgid.info.loc);
+ return;
+ }
+ wait_head = &chan_info->wait[ack_msgid.info.loc];
+ wait_head->ack_err = *(payload + NBL_CHAN_ACK_RET_POS);
+
+ copy_len = min_t(u32, wait_head->ack_data_len, ack_datalen);
+ if (wait_head->ack_err >= 0 && copy_len > 0)
+ memcpy((char *)wait_head->ack_data,
+ payload + NBL_CHAN_ACK_HEAD_LEN, copy_len);
+ wait_head->ack_data_len = (u16)copy_len;
+
+ /*
+ * Ensure all writes to ack_data and ack_data_len are completed
+ * before setting the 'acked' flag. This prevents other threads
+ * from observing stale or partially updated data.
+ */
+ wmb();
+ wait_head->acked = 1;
+ if (wait_head->need_waked)
+ wake_up(&wait_head->wait_queue);
+}
+
+static void nbl_chan_recv_msg(struct nbl_channel_mgt *chan_mgt, void *data)
+{
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_msg_node_data *msg_handler;
+ u16 msg_type, payload_len, srcid, msgid;
+ struct nbl_chan_tx_desc *tx_desc;
+ void *payload;
+
+ tx_desc = data;
+ msg_type = tx_desc->msg_type;
+ dev_dbg(dev, "recv msg_type: %d\n", tx_desc->msg_type);
+
+ srcid = tx_desc->srcid;
+ msgid = tx_desc->msgid;
+ /* Only check if the value exceeds the maximum, relying on the hash
+ * table to filter invalid message IDs.
+ * The gap values are reserved for future protocol extensions.
+ */
+ if (msg_type >= NBL_CHAN_MSG_MAILBOX_MAX)
+ return;
+
+ if (tx_desc->data_len) {
+ payload = (void *)tx_desc->data;
+ payload_len = tx_desc->data_len;
+ } else {
+ payload = (void *)(tx_desc + 1);
+ payload_len = tx_desc->buf_len;
+ }
+
+ msg_handler =
+ nbl_common_get_hash_node(chan_mgt->handle_hash_tbl, &msg_type);
+ if (!msg_handler) {
+ dev_err(dev, "Invalid msg_type: %d\n", msg_type);
+ return;
+ }
+ msg_handler->func(msg_handler->priv, srcid, msgid, payload,
+ payload_len);
+}
+
+static void nbl_chan_advance_rx_ring(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info,
+ struct nbl_chan_ring *rxq)
+{
+ struct nbl_hw_ops *hw_ops = chan_mgt->hw_ops_tbl->ops;
+ struct nbl_chan_rx_desc *rx_desc;
+ struct nbl_chan_buf *rx_buf;
+ u16 next_to_use;
+
+ next_to_use = rxq->next_to_use;
+ rx_desc = NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_use);
+ rx_buf = NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_use);
+
+ rx_desc->flags = BIT(NBL_CHAN_RX_DESC_AVAIL);
+ rx_desc->buf_addr = rx_buf->pa;
+ rx_desc->buf_len = chan_info->rxq_buf_size;
+
+ rxq->next_to_use++;
+ if (rxq->next_to_use == chan_info->num_rxq_entries)
+ rxq->next_to_use = 0;
+ rxq->tail_ptr++;
+
+ NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, rxq->tail_ptr,
+ NBL_MB_RX_QID);
+}
+
+static void nbl_chan_clean_queue(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_info *chan_info)
+{
+ struct nbl_chan_ring *rxq = &chan_info->rxq;
+ struct device *dev = chan_mgt->common->dev;
+ struct nbl_chan_rx_desc *rx_desc;
+ struct nbl_chan_buf *rx_buf;
+ u16 next_to_clean;
+
+ next_to_clean = rxq->next_to_clean;
+ rx_desc = NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_clean);
+ rx_buf = NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_clean);
+ while (rx_desc->flags & BIT(NBL_CHAN_RX_DESC_USED)) {
+ if (!(rx_desc->flags & BIT(NBL_CHAN_RX_DESC_WRITE)))
+ dev_dbg(dev,
+ "mailbox rx flag 0x%x has no NBL_CHAN_RX_DESC_WRITE\n",
+ rx_desc->flags);
+
+ dma_rmb();
+ nbl_chan_recv_msg(chan_mgt, rx_buf->va);
+ nbl_chan_advance_rx_ring(chan_mgt, chan_info, rxq);
+ next_to_clean++;
+ if (next_to_clean == chan_info->num_rxq_entries)
+ next_to_clean = 0;
+ rx_desc = NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_clean);
+ rx_buf = NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_clean);
+ }
+ rxq->next_to_clean = next_to_clean;
+}
+
+static void nbl_chan_clean_queue_subtask(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ if (!test_bit(NBL_CHAN_INTERRUPT_READY, chan_info->state) ||
+ test_bit(NBL_CHAN_RESETTING, chan_info->state))
+ return;
+
+ nbl_chan_clean_queue(chan_mgt, chan_info);
+}
+
+static int nbl_chan_get_msg_id(struct nbl_chan_info *chan_info,
+ union nbl_chan_msg_id *msgid)
+{
+ int valid_loc = chan_info->wait_head_index, i;
+ struct nbl_chan_waitqueue_head *wait = NULL;
+
+ for (i = 0; i < NBL_CHAN_QUEUE_LEN; i++) {
+ wait = &chan_info->wait[valid_loc];
+
+ if (wait->status != NBL_MBX_STATUS_WAITING) {
+ wait->msg_index = NBL_NEXT_ID(wait->msg_index,
+ NBL_CHAN_MSG_INDEX_MAX);
+ msgid->info.index = wait->msg_index;
+ msgid->info.loc = valid_loc;
+
+ valid_loc = NBL_NEXT_ID(valid_loc,
+ chan_info->num_txq_entries - 1);
+ chan_info->wait_head_index = valid_loc;
+ return 0;
+ }
+
+ valid_loc =
+ NBL_NEXT_ID(valid_loc, chan_info->num_txq_entries - 1);
+ }
+
+ /*
+ * the current NBL_CHAN_QUEUE_LEN configuration meets the design
+ * requirements and theoretically should not return errors, the
+ * following scenarios may still cause the waiting queue to
+ * become full:
+ * High-concurrency scenarios:
+ * If the sender (calling nbl_chan_send_msg()) generates messages
+ * at a rate far exceeding the receiver's ability to process
+ * acknowledgments (ACKs),the waiting queue may become fully occupied.
+ * Delayed or failed ACK handling by the receiver:
+ * The receiver may fail to send ACKs in a timely manner due to
+ * processing delays, blocking, or faults, causing the sender's
+ * waiting queue slots to remain occupied for an extended period.
+ */
+ return -EAGAIN;
+}
+
+static int nbl_chan_send_msg(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_send_info *chan_send)
+{
+ struct nbl_common_info *common = chan_mgt->common;
+ struct nbl_chan_waitqueue_head *wait_head;
+ struct nbl_chan_tx_param tx_param = { 0 };
+ union nbl_chan_msg_id msgid = { { 0 } };
+ int i = NBL_CHAN_TX_WAIT_ACK_TIMES, ret;
+ struct nbl_chan_info *chan_info =
+ chan_mgt->chan_info[NBL_CHAN_TYPE_MAILBOX];
+ struct device *dev = common->dev;
+
+ if (test_bit(NBL_CHAN_ABNORMAL, chan_info->state))
+ return -EIO;
+
+ mutex_lock(&chan_info->txq_lock);
+
+ ret = nbl_chan_get_msg_id(chan_info, &msgid);
+ if (ret) {
+ mutex_unlock(&chan_info->txq_lock);
+ dev_err(dev,
+ "Channel tx wait head full, send msgtype:%u to dstid:%u failed\n",
+ chan_send->msg_type, chan_send->dstid);
+ return ret;
+ }
+
+ tx_param.msg_type = chan_send->msg_type;
+ tx_param.arg = chan_send->arg;
+ tx_param.arg_len = chan_send->arg_len;
+ tx_param.dstid = chan_send->dstid;
+ tx_param.msgid = msgid.id;
+
+ ret = nbl_chan_update_txqueue(chan_mgt, chan_info, &tx_param);
+ if (ret) {
+ mutex_unlock(&chan_info->txq_lock);
+ dev_err(dev,
+ "Channel tx queue full, send msgtype:%u to dstid:%u failed\n",
+ chan_send->msg_type, chan_send->dstid);
+ return ret;
+ }
+
+ wait_head = &chan_info->wait[msgid.info.loc];
+ init_waitqueue_head(&wait_head->wait_queue);
+ wait_head->acked = 0;
+ wait_head->ack_data = chan_send->resp;
+ wait_head->ack_data_len = chan_send->resp_len;
+ wait_head->msg_type = chan_send->msg_type;
+ wait_head->need_waked = chan_send->ack;
+ wait_head->msg_index = msgid.info.index;
+ wait_head->status = chan_send->ack ? NBL_MBX_STATUS_WAITING :
+ NBL_MBX_STATUS_IDLE;
+
+ ret = nbl_chan_kick_tx_ring(chan_mgt, chan_info);
+
+ mutex_unlock(&chan_info->txq_lock);
+ if (ret) {
+ wait_head->status = NBL_MBX_STATUS_TIMEOUT;
+ return ret;
+ }
+ if (!chan_send->ack)
+ return 0;
+
+ if (test_bit(NBL_CHAN_INTERRUPT_READY, chan_info->state)) {
+ ret = wait_event_timeout(wait_head->wait_queue,
+ wait_head->acked,
+ NBL_CHAN_ACK_WAIT_TIME);
+ if (!ret) {
+ wait_head->status = NBL_MBX_STATUS_TIMEOUT;
+ dev_err(dev,
+ "Channel waiting ack failed, message type: %d, msg id: %u\n",
+ chan_send->msg_type, msgid.id);
+ return -ETIMEDOUT;
+ }
+
+ /*
+ * ensure that after observing 'acked == 1', all subsequent
+ * reads (ack_data_len, ack_err) observe the latest values
+ * written by the sender (nbl_chan_recv_ack_msg()). This
+ * prevents stale reads of ACK data or status.
+ */
+ rmb();
+ chan_send->ack_len = wait_head->ack_data_len;
+ wait_head->status = NBL_MBX_STATUS_IDLE;
+ return wait_head->ack_err;
+ }
+
+ /*polling wait mailbox ack*/
+ while (i--) {
+ nbl_chan_clean_queue(chan_mgt, chan_info);
+
+ if (wait_head->acked) {
+ chan_send->ack_len = wait_head->ack_data_len;
+ wait_head->status = NBL_MBX_STATUS_IDLE;
+ return wait_head->ack_err;
+ }
+ usleep_range(NBL_CHAN_TX_WAIT_ACK_US_MIN,
+ NBL_CHAN_TX_WAIT_ACK_US_MAX);
+ }
+
+ wait_head->status = NBL_MBX_STATUS_TIMEOUT;
+ dev_err(dev,
+ "Channel polling ack failed, message type: %d msg id: %u\n",
+ chan_send->msg_type, msgid.id);
+
+ return -EFAULT;
+}
+
+static int nbl_chan_send_ack(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_ack_info *chan_ack)
+{
+ u32 len = NBL_CHAN_ACK_HEAD_LEN * sizeof(u32) + chan_ack->data_len;
+ struct nbl_chan_send_info chan_send;
+ u32 *tmp;
+ int ret;
+
+ tmp = kzalloc(len, GFP_KERNEL);
+ if (!tmp)
+ return -ENOMEM;
+
+ tmp[NBL_CHAN_MSG_TYPE_POS] = chan_ack->msg_type;
+ tmp[NBL_CHAN_MSG_ID_POS] = chan_ack->msgid;
+ tmp[NBL_CHAN_ACK_RET_POS] = (u32)chan_ack->err;
+ if (chan_ack->data && chan_ack->data_len)
+ memcpy(&tmp[NBL_CHAN_ACK_HEAD_LEN], chan_ack->data,
+ chan_ack->data_len);
+
+ NBL_CHAN_SEND(chan_send, chan_ack->dstid, NBL_CHAN_MSG_ACK, tmp, len,
+ NULL, 0, 0);
+ ret = nbl_chan_send_msg(chan_mgt, &chan_send);
+ kfree(tmp);
+
+ return ret;
+}
+
+static int nbl_chan_register_msg(struct nbl_channel_mgt *chan_mgt, u16 msg_type,
+ nbl_chan_resp func, void *callback)
+{
+ return nbl_chan_add_msg_handler(chan_mgt, msg_type, func, callback);
+}
+
+static bool nbl_chan_check_queue_exist(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ return chan_info ? true : false;
+}
+
+static void nbl_chan_register_chan_task(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type, struct work_struct *task)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ chan_info->clean_task = task;
+}
+
+static void nbl_chan_set_queue_state(struct nbl_channel_mgt *chan_mgt,
+ enum nbl_chan_state state, u8 chan_type,
+ u8 set)
+{
+ struct nbl_chan_info *chan_info = chan_mgt->chan_info[chan_type];
+
+ if (set)
+ set_bit(state, chan_info->state);
+ else
+ clear_bit(state, chan_info->state);
+}
+
static struct nbl_channel_ops chan_ops = {
+ .send_msg = nbl_chan_send_msg,
+ .send_ack = nbl_chan_send_ack,
+ .register_msg = nbl_chan_register_msg,
+ .cfg_chan_qinfo_map_table = nbl_chan_cfg_qinfo_map_table,
+ .check_queue_exist = nbl_chan_check_queue_exist,
+ .setup_queue = nbl_chan_setup_queue,
+ .teardown_queue = nbl_chan_teardown_queue,
+ .clean_queue_subtask = nbl_chan_clean_queue_subtask,
+ .register_chan_task = nbl_chan_register_chan_task,
+ .set_queue_state = nbl_chan_set_queue_state,
};
static struct nbl_channel_mgt *
@@ -18,6 +763,7 @@ nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter)
struct device *dev = &adapter->pdev->dev;
struct nbl_channel_mgt *chan_mgt;
struct nbl_chan_info *mailbox;
+ int ret;
chan_mgt = devm_kzalloc(dev, sizeof(*chan_mgt), GFP_KERNEL);
if (!chan_mgt)
@@ -32,6 +778,10 @@ nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter)
mailbox->chan_type = NBL_CHAN_TYPE_MAILBOX;
chan_mgt->chan_info[NBL_CHAN_TYPE_MAILBOX] = mailbox;
+ ret = nbl_chan_init_msg_handler(chan_mgt);
+ if (ret)
+ return ERR_PTR(-ENOMEM);
+
return chan_mgt;
}
@@ -39,6 +789,7 @@ static struct nbl_channel_ops_tbl *
nbl_chan_setup_ops(struct device *dev, struct nbl_channel_mgt *chan_mgt)
{
struct nbl_channel_ops_tbl *chan_ops_tbl;
+ int ret;
chan_ops_tbl = devm_kzalloc(dev, sizeof(*chan_ops_tbl), GFP_KERNEL);
if (!chan_ops_tbl)
@@ -47,6 +798,11 @@ nbl_chan_setup_ops(struct device *dev, struct nbl_channel_mgt *chan_mgt)
chan_ops_tbl->ops = &chan_ops;
chan_ops_tbl->priv = chan_mgt;
+ ret = nbl_chan_register_msg(chan_mgt, NBL_CHAN_MSG_ACK,
+ nbl_chan_recv_ack_msg, chan_mgt);
+ if (ret)
+ return ERR_PTR(-ENOMEM);
+
return chan_ops_tbl;
}
@@ -60,19 +816,28 @@ int nbl_chan_init_common(struct nbl_adapter *adap)
chan_mgt = nbl_chan_setup_chan_mgt(adap);
if (IS_ERR(chan_mgt)) {
ret = PTR_ERR(chan_mgt);
- return ret;
+ goto setup_mgt_fail;
}
adap->core.chan_mgt = chan_mgt;
chan_ops_tbl = nbl_chan_setup_ops(dev, chan_mgt);
if (IS_ERR(chan_ops_tbl)) {
ret = PTR_ERR(chan_ops_tbl);
- return ret;
+ goto setup_ops_fail;
}
adap->intf.channel_ops_tbl = chan_ops_tbl;
+
return 0;
+
+setup_ops_fail:
+ nbl_chan_remove_msg_handler(chan_mgt);
+setup_mgt_fail:
+ return ret;
}
void nbl_chan_remove_common(struct nbl_adapter *adap)
{
+ struct nbl_channel_mgt *chan_mgt = adap->core.chan_mgt;
+
+ nbl_chan_remove_msg_handler(chan_mgt);
}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
index 637912d1e806..b7e085faac96 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
@@ -15,10 +15,144 @@
#include "../nbl_include/nbl_def_common.h"
#include "../nbl_core.h"
+#define NBL_CHAN_TX_RING_TO_DESC(tx_ring, i) \
+ (&((((tx_ring)->desc.tx_desc))[i]))
+#define NBL_CHAN_RX_RING_TO_DESC(rx_ring, i) \
+ (&((((rx_ring)->desc.rx_desc))[i]))
+#define NBL_CHAN_TX_RING_TO_BUF(tx_ring, i) (&(((tx_ring)->buf)[i]))
+#define NBL_CHAN_RX_RING_TO_BUF(rx_ring, i) (&(((rx_ring)->buf)[i]))
+
+#define NBL_CHAN_TX_WAIT_US 100
+#define NBL_CHAN_TX_REKICK_WAIT_TIMES 2000
+#define NBL_CHAN_TX_WAIT_TIMES 30000
+#define NBL_CHAN_TX_WAIT_ACK_US_MIN 100
+#define NBL_CHAN_TX_WAIT_ACK_US_MAX 120
+#define NBL_CHAN_TX_WAIT_ACK_TIMES 50000
+#define NBL_CHAN_QUEUE_LEN 256
+#define NBL_CHAN_BUF_LEN 4096
+#define NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN 16
+
+#define NBL_CHAN_TX_DESC_AVAIL 0
+#define NBL_CHAN_TX_DESC_USED 1
+#define NBL_CHAN_RX_DESC_WRITE 1
+#define NBL_CHAN_RX_DESC_AVAIL 3
+#define NBL_CHAN_RX_DESC_USED 4
+
+#define NBL_CHAN_ACK_HEAD_LEN 3
+#define NBL_CHAN_ACK_RET_POS 2
+#define NBL_CHAN_MSG_ID_POS 1
+#define NBL_CHAN_MSG_TYPE_POS 0
+
+#define NBL_CHAN_ACK_WAIT_TIME (3 * HZ)
+
+#define NBL_CHAN_HANDLER_TBL_BUCKET_SIZE 512
+
+enum {
+ NBL_MB_RX_QID = 0,
+ NBL_MB_TX_QID = 1,
+};
+
+enum {
+ NBL_MBX_STATUS_IDLE = 0,
+ NBL_MBX_STATUS_WAITING,
+ NBL_MBX_STATUS_TIMEOUT = -1,
+};
+
+struct nbl_chan_tx_param {
+ enum nbl_chan_msg_type msg_type;
+ void *arg;
+ size_t arg_len;
+ u16 dstid;
+ u16 msgid;
+};
+
+struct nbl_chan_buf {
+ void *va;
+ dma_addr_t pa;
+ size_t size;
+};
+
+struct nbl_chan_tx_desc {
+ u16 flags;
+ u16 srcid;
+ u16 dstid;
+ u16 data_len;
+ u16 buf_len;
+ u64 buf_addr;
+ u16 msg_type;
+ u8 data[16];
+ u16 msgid;
+ u8 rsv[26];
+} __packed;
+
+struct nbl_chan_rx_desc {
+ u16 flags;
+ u32 buf_len;
+ u16 buf_id;
+ u64 buf_addr;
+} __packed;
+
+union nbl_chan_desc_ptr {
+ struct nbl_chan_tx_desc *tx_desc;
+ struct nbl_chan_rx_desc *rx_desc;
+};
+
+struct nbl_chan_ring {
+ union nbl_chan_desc_ptr desc;
+ struct nbl_chan_buf *buf;
+ u16 next_to_use;
+ u16 tail_ptr;
+ u16 next_to_clean;
+ dma_addr_t dma;
+};
+
+#define NBL_CHAN_MSG_INDEX_MAX 63
+
+union nbl_chan_msg_id {
+ struct nbl_chan_msg_id_info {
+ u16 index : 6;
+ u16 loc : 10;
+ } info;
+ u16 id;
+};
+
+struct nbl_chan_waitqueue_head {
+ struct wait_queue_head wait_queue;
+ char *ack_data;
+ int acked;
+ int ack_err;
+ u16 ack_data_len;
+ u16 need_waked;
+ u16 msg_type;
+ u8 status;
+ u8 msg_index;
+};
+
struct nbl_chan_info {
+ struct nbl_chan_ring txq;
+ struct nbl_chan_ring rxq;
+ struct nbl_chan_waitqueue_head *wait;
+ /*
+ *Protects access to the TX queue (txq) and related metadata.
+ *This mutex ensures exclusive access when updating the TX queue
+ *or waiting for ACKs to prevent race conditions.
+ */
+ struct mutex txq_lock;
+ struct work_struct *clean_task;
+ u16 wait_head_index;
+ u16 num_txq_entries;
+ u16 num_rxq_entries;
+ u16 txq_buf_size;
+ u16 rxq_buf_size;
+ DECLARE_BITMAP(state, NBL_CHAN_STATE_NBITS);
u8 chan_type;
};
+struct nbl_chan_msg_node_data {
+ nbl_chan_resp func;
+ void *priv;
+};
+
struct nbl_channel_mgt {
struct nbl_common_info *common;
struct nbl_hw_ops_tbl *hw_ops_tbl;
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
new file mode 100644
index 000000000000..5b92db4987dc
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#include <linux/device.h>
+#include "nbl_common.h"
+
+static struct nbl_common_wq_mgt *wq_mgt;
+
+void nbl_common_queue_work(struct work_struct *task)
+{
+ queue_work(wq_mgt->ctrl_dev_wq, task);
+}
+
+void nbl_common_destroy_wq(void)
+{
+ destroy_workqueue(wq_mgt->ctrl_dev_wq);
+ kfree(wq_mgt);
+}
+
+int nbl_common_create_wq(void)
+{
+ wq_mgt = kzalloc_obj(*wq_mgt);
+ if (!wq_mgt)
+ return -ENOMEM;
+
+ wq_mgt->ctrl_dev_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM | WQ_UNBOUND,
+ 0, "nbl_ctrldev_wq");
+ if (!wq_mgt->ctrl_dev_wq) {
+ pr_err("Failed to create workqueue nbl_ctrldev_wq\n");
+ goto alloc_ctrl_dev_wq_failed;
+ }
+
+ return 0;
+alloc_ctrl_dev_wq_failed:
+ kfree(wq_mgt);
+ return -ENOMEM;
+}
+
+u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common,
+ u32 pf_id)
+{
+ u32 diff = U32_MAX;
+
+ if (pf_id >= common->mgt_pf)
+ diff = pf_id - common->mgt_pf;
+
+ return diff;
+}
+
+#define FNV_PRIME_32 0x01000193
+#define FNV_OFFSET_32 0x811C9DC5
+static u32 nbl_common_calc_hash_key(void *key, u32 key_size, u32 bucket_size)
+{
+ u32 hash = FNV_OFFSET_32;
+ u8 *p = (u8 *)key;
+ u32 i;
+
+ if (bucket_size == 0 || bucket_size == NBL_HASH_TBL_LIST_BUCKET_SIZE)
+ return 0;
+
+ for (i = 0; i < key_size; i++) {
+ hash ^= p[i];
+ hash *= FNV_PRIME_32;
+ }
+ /* Use bitmask if bucket_size is a power of 2 */
+ if ((bucket_size & (bucket_size - 1)) == 0)
+ return hash & (bucket_size - 1);
+ else
+ return hash % bucket_size;
+}
+
+/*
+ * alloc a hash table
+ * the table support multi thread
+ */
+struct nbl_hash_tbl_mgt *
+nbl_common_init_hash_table(struct nbl_hash_tbl_key *key)
+{
+ struct nbl_hash_tbl_mgt *tbl_mgt;
+ int bucket_size;
+ int i;
+
+ tbl_mgt = devm_kzalloc(key->dev, sizeof(*tbl_mgt), GFP_KERNEL);
+ if (!tbl_mgt)
+ return NULL;
+
+ bucket_size = key->bucket_size;
+ tbl_mgt->hash = devm_kcalloc(key->dev, bucket_size,
+ sizeof(struct hlist_head), GFP_KERNEL);
+ if (!tbl_mgt->hash)
+ goto alloc_hash_failed;
+
+ for (i = 0; i < bucket_size; i++)
+ INIT_HLIST_HEAD(tbl_mgt->hash + i);
+
+ memcpy(&tbl_mgt->tbl_key, key, sizeof(struct nbl_hash_tbl_key));
+
+ return tbl_mgt;
+
+alloc_hash_failed:
+ return NULL;
+}
+
+/*
+ * The number of nodes in the hash table is guaranteed to be bounded
+ * (as defined in nbl_disp_setup_msg).
+ * So all hash nodes (struct nbl_hash_entry_node) and their associated keys/data
+ * are allocated via devm_kzalloc() and will be automatically freed when the
+ * device is removed. Functions like nbl_common_detach_hash_node() only remove
+ * nodes from the list but do not trigger immediate memory deallocation.
+ */
+int nbl_common_alloc_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key,
+ void *data, void **out_data)
+{
+ struct nbl_hash_entry_node *hash_node;
+ u16 data_size;
+ u32 hash_val;
+ u16 key_size;
+
+ hash_node = devm_kzalloc(tbl_mgt->tbl_key.dev, sizeof(*hash_node),
+ GFP_KERNEL);
+ if (!hash_node)
+ return -ENOMEM;
+
+ key_size = tbl_mgt->tbl_key.key_size;
+ hash_node->key =
+ devm_kzalloc(tbl_mgt->tbl_key.dev, key_size, GFP_KERNEL);
+ if (!hash_node->key)
+ return -ENOMEM;
+
+ data_size = tbl_mgt->tbl_key.data_size;
+ hash_node->data =
+ devm_kzalloc(tbl_mgt->tbl_key.dev, data_size, GFP_KERNEL);
+ if (!hash_node->data)
+ return -ENOMEM;
+
+ memcpy(hash_node->key, key, key_size);
+ memcpy(hash_node->data, data, data_size);
+
+ hash_val = nbl_common_calc_hash_key(key, key_size,
+ tbl_mgt->tbl_key.bucket_size);
+
+ hlist_add_head(&hash_node->node, tbl_mgt->hash + hash_val);
+ tbl_mgt->node_num++;
+ if (out_data)
+ *out_data = hash_node->data;
+
+ return 0;
+}
+
+/*
+ * get a hash node, return the data if node exist
+ */
+void *nbl_common_get_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key)
+{
+ struct nbl_hash_entry_node *hash_node;
+ struct hlist_head *head;
+ void *data = NULL;
+ u32 hash_val;
+ u16 key_size;
+
+ key_size = tbl_mgt->tbl_key.key_size;
+ hash_val = nbl_common_calc_hash_key(key, key_size,
+ tbl_mgt->tbl_key.bucket_size);
+ head = tbl_mgt->hash + hash_val;
+
+ hlist_for_each_entry(hash_node, head, node)
+ if (!memcmp(hash_node->key, key, key_size)) {
+ data = hash_node->data;
+ break;
+ }
+
+ return data;
+}
+
+/*
+ * Detaches the node from the hash list but does NOT free the memory.
+ * Memory is managed by devm and will be released automatically
+ * when the device is removed.
+ */
+static void nbl_common_detach_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt,
+ struct nbl_hash_entry_node *hash_node)
+{
+ hlist_del(&hash_node->node);
+ tbl_mgt->node_num--;
+}
+
+/*
+ * Detaches all nodes from the hash table but does NOT free their memory.
+ * Memory will be released automatically by devm when the device is removed.
+ */
+void nbl_common_remove_hash_table(struct nbl_hash_tbl_mgt *tbl_mgt,
+ struct nbl_hash_tbl_del_key *key)
+{
+ struct nbl_hash_entry_node *hash_node;
+ struct hlist_node *safe_node;
+ struct hlist_head *head;
+ u32 i;
+
+ for (i = 0; i < tbl_mgt->tbl_key.bucket_size; i++) {
+ head = tbl_mgt->hash + i;
+ hlist_for_each_entry_safe(hash_node, safe_node, head, node) {
+ if (key && key->action_func)
+ key->action_func(key->action_priv,
+ hash_node->key,
+ hash_node->data);
+ nbl_common_detach_hash_node(tbl_mgt, hash_node);
+ }
+ }
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
new file mode 100644
index 000000000000..7d628d3556ee
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_COMMON_H_
+#define _NBL_COMMON_H_
+
+#include <linux/types.h>
+
+#include "../nbl_include/nbl_include.h"
+#include "../nbl_include/nbl_def_common.h"
+
+/* list only need one bucket size */
+#define NBL_HASH_TBL_LIST_BUCKET_SIZE 1
+
+struct nbl_common_wq_mgt {
+ struct workqueue_struct *ctrl_dev_wq;
+};
+
+struct nbl_hash_tbl_mgt {
+ struct nbl_hash_tbl_key tbl_key;
+ struct hlist_head *hash;
+ u16 node_num;
+};
+
+/* it used for y_axis no necessay */
+struct nbl_hash_entry_node {
+ struct hlist_node node;
+ void *key;
+ void *data;
+};
+
+#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
index 6dd8d3a087dd..83a4dc584f48 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
@@ -9,7 +9,150 @@
#include <linux/spinlock.h>
#include "nbl_hw_leonis.h"
+static void nbl_hw_write_mbx_regs(struct nbl_hw_mgt *hw_mgt, u64 reg,
+ const u32 *data, u32 len)
+{
+ u32 i;
+
+ if (len % 4)
+ return;
+
+ for (i = 0; i < len / 4; i++)
+ nbl_mbx_wr32(hw_mgt, reg + i * sizeof(u32), data[i]);
+}
+
+static void nbl_hw_rd_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, u32 *data,
+ u32 len)
+{
+ u32 size = len / 4;
+ u32 i;
+
+ if (len % 4)
+ return;
+
+ spin_lock(&hw_mgt->reg_lock);
+
+ for (i = 0; i < size; i++)
+ data[i] = rd32(hw_mgt->hw_addr, reg + i * sizeof(u32));
+ spin_unlock(&hw_mgt->reg_lock);
+}
+
+static void nbl_hw_wr_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, const u32 *data,
+ u32 len)
+{
+ u32 size = len / 4;
+ u32 i;
+
+ if (len % 4)
+ return;
+ spin_lock(&hw_mgt->reg_lock);
+ for (i = 0; i < size; i++)
+ wr32(hw_mgt->hw_addr, reg + i * sizeof(u32), data[i]);
+ spin_unlock(&hw_mgt->reg_lock);
+}
+
+static void nbl_hw_update_mailbox_queue_tail_ptr(struct nbl_hw_mgt *hw_mgt,
+ u16 tail_ptr, u8 txrx)
+{
+ /* local_qid 0 and 1 denote rx and tx queue respectively */
+ u32 local_qid = txrx;
+ u32 value = ((u32)tail_ptr << 16) | local_qid;
+
+ /* wmb for doorbell */
+ wmb();
+ nbl_mbx_wr32(hw_mgt, NBL_MAILBOX_NOTIFY_ADDR, value);
+}
+
+static void nbl_hw_config_mailbox_rxq(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid)
+{
+ struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_rx_table = { 0 };
+
+ qinfo_cfg_rx_table.queue_rst = 1;
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR,
+ (u32 *)&qinfo_cfg_rx_table,
+ sizeof(qinfo_cfg_rx_table));
+
+ qinfo_cfg_rx_table.queue_base_addr_l = (u32)(dma_addr & 0xFFFFFFFF);
+ qinfo_cfg_rx_table.queue_base_addr_h = (u32)(dma_addr >> 32);
+ qinfo_cfg_rx_table.queue_size_bwind = (u32)size_bwid;
+ qinfo_cfg_rx_table.queue_rst = 0;
+ qinfo_cfg_rx_table.queue_en = 1;
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR,
+ (u32 *)&qinfo_cfg_rx_table,
+ sizeof(qinfo_cfg_rx_table));
+}
+
+static void nbl_hw_config_mailbox_txq(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid)
+{
+ struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_tx_table = { 0 };
+
+ qinfo_cfg_tx_table.queue_rst = 1;
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR,
+ (u32 *)&qinfo_cfg_tx_table,
+ sizeof(qinfo_cfg_tx_table));
+
+ qinfo_cfg_tx_table.queue_base_addr_l = (u32)(dma_addr & 0xFFFFFFFF);
+ qinfo_cfg_tx_table.queue_base_addr_h = (u32)(dma_addr >> 32);
+ qinfo_cfg_tx_table.queue_size_bwind = (u32)size_bwid;
+ qinfo_cfg_tx_table.queue_rst = 0;
+ qinfo_cfg_tx_table.queue_en = 1;
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR,
+ (u32 *)&qinfo_cfg_tx_table,
+ sizeof(qinfo_cfg_tx_table));
+}
+
+static void nbl_hw_stop_mailbox_rxq(struct nbl_hw_mgt *hw_mgt)
+{
+ struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_rx_table = { 0 };
+
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR,
+ (u32 *)&qinfo_cfg_rx_table,
+ sizeof(qinfo_cfg_rx_table));
+}
+
+static void nbl_hw_stop_mailbox_txq(struct nbl_hw_mgt *hw_mgt)
+{
+ struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_tx_table = { 0 };
+
+ nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR,
+ (u32 *)&qinfo_cfg_tx_table,
+ sizeof(qinfo_cfg_tx_table));
+}
+
+static u32 nbl_hw_get_host_pf_mask(struct nbl_hw_mgt *hw_mgt)
+{
+ u32 data;
+
+ nbl_hw_rd_regs(hw_mgt, NBL_PCIE_HOST_K_PF_MASK_REG, &data,
+ sizeof(data));
+ return data;
+}
+
+static void nbl_hw_cfg_mailbox_qinfo(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ u16 bus, u16 devid, u16 function)
+{
+ struct nbl_mailbox_qinfo_map_table mb_qinfo_map;
+
+ memset(&mb_qinfo_map, 0, sizeof(mb_qinfo_map));
+ mb_qinfo_map.function = function;
+ mb_qinfo_map.devid = devid;
+ mb_qinfo_map.bus = bus;
+ mb_qinfo_map.msix_idx_valid = 0;
+ nbl_hw_wr_regs(hw_mgt, NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id),
+ (u32 *)&mb_qinfo_map, sizeof(mb_qinfo_map));
+}
+
static struct nbl_hw_ops hw_ops = {
+ .update_mailbox_queue_tail_ptr = nbl_hw_update_mailbox_queue_tail_ptr,
+ .config_mailbox_rxq = nbl_hw_config_mailbox_rxq,
+ .config_mailbox_txq = nbl_hw_config_mailbox_txq,
+ .stop_mailbox_rxq = nbl_hw_stop_mailbox_rxq,
+ .stop_mailbox_txq = nbl_hw_stop_mailbox_txq,
+ .get_host_pf_mask = nbl_hw_get_host_pf_mask,
+ .cfg_mailbox_qinfo = nbl_hw_cfg_mailbox_qinfo,
+
};
/* Structure starts here, adding an op should not modify anything below */
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
index 99e1d8455e0e..39d23160a7a4 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
@@ -6,8 +6,42 @@
#ifndef _NBL_DEF_CHANNEL_H_
#define _NBL_DEF_CHANNEL_H_
+#include <linux/types.h>
+
struct nbl_channel_mgt;
struct nbl_adapter;
+#define NBL_CHAN_SEND(chan_send, dst_id, mesg_type, argument, arg_length,\
+ response, resp_length, need_ack) \
+do { \
+ typeof(chan_send) *__chan_send = &(chan_send); \
+ __chan_send->dstid = (dst_id); \
+ __chan_send->msg_type = (mesg_type); \
+ __chan_send->arg = (argument); \
+ __chan_send->arg_len = (arg_length); \
+ __chan_send->resp = (response); \
+ __chan_send->resp_len = (resp_length); \
+ __chan_send->ack = (need_ack); \
+} while (0)
+
+#define NBL_CHAN_ACK(chan_ack, dst_id, mesg_type, msg_id, err_code, ack_data, \
+ data_length) \
+do { \
+ typeof(chan_ack) *__chan_ack = &(chan_ack); \
+ __chan_ack->dstid = (dst_id); \
+ __chan_ack->msg_type = (mesg_type); \
+ __chan_ack->msgid = (msg_id); \
+ __chan_ack->err = (err_code); \
+ __chan_ack->data = (ack_data); \
+ __chan_ack->data_len = (data_length); \
+} while (0)
+
+typedef void (*nbl_chan_resp)(void *, u16, u16, void *, u32);
+
+enum {
+ NBL_CHAN_RESP_OK,
+ NBL_CHAN_RESP_ERR,
+};
+
enum nbl_chan_msg_type {
NBL_CHAN_MSG_ACK,
NBL_CHAN_MSG_ADD_MACVLAN,
@@ -234,6 +268,13 @@ enum nbl_chan_msg_type {
NBL_CHAN_MSG_MAILBOX_MAX,
};
+enum nbl_chan_state {
+ NBL_CHAN_INTERRUPT_READY,
+ NBL_CHAN_RESETTING,
+ NBL_CHAN_ABNORMAL,
+ NBL_CHAN_STATE_NBITS
+};
+
struct nbl_chan_param_cfg_msix_map {
u16 num_net_msix;
u16 num_others_msix;
@@ -257,12 +298,58 @@ struct nbl_chan_param_get_eth_id {
u8 logic_eth_id;
};
+struct nbl_board_port_info {
+ u8 eth_num;
+ u8 eth_speed;
+ u8 p4_version;
+ u8 rsv[5];
+};
+
+struct nbl_chan_send_info {
+ void *arg;
+ size_t arg_len;
+ void *resp;
+ size_t resp_len;
+ u16 dstid;
+ u16 msg_type;
+ u16 ack;
+ u16 ack_len;
+};
+
+struct nbl_chan_ack_info {
+ void *data;
+ int err;
+ u32 data_len;
+ u16 dstid;
+ u16 msg_type;
+ u16 msgid;
+};
+
enum nbl_channel_type {
NBL_CHAN_TYPE_MAILBOX,
NBL_CHAN_TYPE_MAX
};
struct nbl_channel_ops {
+ int (*send_msg)(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_send_info *chan_send);
+ int (*send_ack)(struct nbl_channel_mgt *chan_mgt,
+ struct nbl_chan_ack_info *chan_ack);
+ int (*register_msg)(struct nbl_channel_mgt *chan_mgt, u16 msg_type,
+ nbl_chan_resp func, void *callback_priv);
+ int (*cfg_chan_qinfo_map_table)(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type);
+ bool (*check_queue_exist)(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type);
+ int (*setup_queue)(struct nbl_channel_mgt *chan_mgt, u8 chan_type);
+ int (*teardown_queue)(struct nbl_channel_mgt *chan_mgt, u8 chan_type);
+ void (*clean_queue_subtask)(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type);
+ void (*register_chan_task)(struct nbl_channel_mgt *chan_mgt,
+ u8 chan_type, struct work_struct *task);
+ void (*set_queue_state)(struct nbl_channel_mgt *chan_mgt,
+ enum nbl_chan_state state, u8 chan_type,
+ u8 set);
};
struct nbl_channel_ops_tbl {
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
index cc73d6a91f3c..5c532247c852 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
@@ -11,6 +11,8 @@
#include <linux/device.h>
#include "nbl_include.h"
+struct nbl_hash_tbl_mgt;
+
struct nbl_common_info {
struct pci_dev *pdev;
struct device *dev;
@@ -32,4 +34,32 @@ struct nbl_common_info {
u8 has_net;
};
+struct nbl_hash_tbl_key {
+ struct device *dev;
+ u16 key_size;
+ u16 data_size; /* no include key or node member */
+ u16 bucket_size;
+ u16 resv;
+};
+
+struct nbl_hash_tbl_del_key {
+ void *action_priv;
+ void (*action_func)(void *priv, void *key, void *data);
+};
+
+void nbl_common_queue_work(struct work_struct *task);
+
+void nbl_common_destroy_wq(void);
+int nbl_common_create_wq(void);
+u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common,
+ u32 pf_id);
+
+struct nbl_hash_tbl_mgt *
+nbl_common_init_hash_table(struct nbl_hash_tbl_key *key);
+void nbl_common_remove_hash_table(struct nbl_hash_tbl_mgt *tbl_mgt,
+ struct nbl_hash_tbl_del_key *key);
+int nbl_common_alloc_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key,
+ void *data, void **out_data);
+void *nbl_common_get_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key);
+
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
index 168504b30973..f97f7a810ad0 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
@@ -6,9 +6,37 @@
#ifndef _NBL_DEF_HW_H_
#define _NBL_DEF_HW_H_
+#include <linux/types.h>
+
struct nbl_hw_mgt;
struct nbl_adapter;
struct nbl_hw_ops {
+ void (*configure_msix_map)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool valid, dma_addr_t dma_addr, u8 bus,
+ u8 devid, u8 function);
+ void (*configure_msix_info)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool valid, u16 interrupt_id, u8 bus,
+ u8 devid, u8 function,
+ bool net_msix_mask_en);
+ void (*update_mailbox_queue_tail_ptr)(struct nbl_hw_mgt *hw_mgt,
+ u16 tail_ptr, u8 txrx);
+ void (*config_mailbox_rxq)(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid);
+ void (*config_mailbox_txq)(struct nbl_hw_mgt *hw_mgt,
+ dma_addr_t dma_addr, int size_bwid);
+ void (*stop_mailbox_rxq)(struct nbl_hw_mgt *hw_mgt);
+ void (*stop_mailbox_txq)(struct nbl_hw_mgt *hw_mgt);
+ u32 (*get_host_pf_mask)(struct nbl_hw_mgt *hw_mgt);
+ u32 (*get_real_bus)(struct nbl_hw_mgt *hw_mgt);
+
+ void (*cfg_mailbox_qinfo)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ u16 bus, u16 devid, u16 function);
+ void (*enable_mailbox_irq)(struct nbl_hw_mgt *hw_mgt, u16 func_id,
+ bool enable_msix, u16 global_vec_id);
+ u32 (*get_fw_eth_num)(struct nbl_hw_mgt *hw_mgt);
+ u32 (*get_fw_eth_map)(struct nbl_hw_mgt *hw_mgt);
+ void (*get_board_info)(struct nbl_hw_mgt *hw_mgt,
+ struct nbl_board_port_info *board);
};
struct nbl_hw_ops_tbl {
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
index 50f30f756bf3..a01c32f57d84 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
@@ -10,6 +10,12 @@
/* ------ Basic definitions ------- */
#define NBL_DRIVER_NAME "nbl"
+#define NBL_MAX_PF 8
+#define NBL_NEXT_ID(id, max) \
+ ({ \
+ typeof(id) _id = (id); \
+ ((_id) == (max) ? 0 : (_id) + 1); \
+ })
enum nbl_product_type {
NBL_LEONIS_TYPE,
--
2.47.3
^ permalink raw reply related
* [PATCH v11 net-next 03/11] net/nebula-matrix: add chip related definitions
From: illusion.wang @ 2026-04-08 9:37 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, linux-doc, lorenzo, pabeni, horms,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
In-Reply-To: <20260408093739.56001-1-illusion.wang@nebula-matrix.com>
1. nbl_hw.h/nbl_hw_leonis.h
chip-related reg definitions
2. nbl_hw_leonis_regs.c
P4 configuration that will be invoked during chip initialization
These nbl_sec*_data are used to configure P4-related registers. The
driver’s functionality depends heavily on these register settings. But
they can be not marked __initdata. Because it will be called by
pci_driver.probe.They also should not be moved into firmware files,
as the software functionality is tightly coupled with these
configurations.If they were moved to firmware,users could easily end up
with mismatched versions of the firmware and the kernel driver module,
leading to functional inconsistencies or system malfunctions.
Signed-off-by: illusion.wang <illusion.wang@nebula-matrix.com>
---
.../net/ethernet/nebula-matrix/nbl/Makefile | 1 +
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 469 +++
.../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c | 2901 +++++++++++++++++
.../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h | 11 +
4 files changed, 3382 insertions(+)
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
index 271605920396..63116d1d7043 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile
+++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NBL) := nbl.o
nbl-objs += nbl_channel/nbl_channel.o \
nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \
nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \
+ nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \
nbl_core/nbl_dispatch.o \
nbl_core/nbl_dev.o \
nbl_main.o
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
index 77c67b67ba31..8831394ed11b 100644
--- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
@@ -11,4 +11,473 @@
#include "../../nbl_include/nbl_include.h"
#include "../nbl_hw_reg.h"
+#define NBL_DRIVER_STATUS_REG 0x1300444
+#define NBL_DRIVER_STATUS_BIT 16
+
+#pragma pack(1)
+
+/* ---------- REG BASE ADDR ---------- */
+/* Interface modules base addr */
+#define NBL_INTF_HOST_PCOMPLETER_BASE 0x00f08000
+#define NBL_INTF_HOST_PADPT_BASE 0x00f4c000
+#define NBL_INTF_HOST_MAILBOX_BASE 0x00fb0000
+#define NBL_INTF_HOST_PCIE_BASE 0X01504000
+/* DP modules base addr */
+#define NBL_DP_USTORE_BASE 0x00104000
+#define NBL_DP_UQM_BASE 0x00114000
+#define NBL_DP_UPED_BASE 0x0015c000
+#define NBL_DP_UVN_BASE 0x00244000
+#define NBL_DP_DSCH_BASE 0x00404000
+#define NBL_DP_SHAPING_BASE 0x00504000
+#define NBL_DP_DVN_BASE 0x00514000
+#define NBL_DP_DSTORE_BASE 0x00704000
+#define NBL_DP_DQM_BASE 0x00714000
+#define NBL_DP_DPED_BASE 0x0075c000
+#define NBL_DP_DDMUX_BASE 0x00984000
+/* -------- MAILBOX BAR2 ----- */
+#define NBL_MAILBOX_NOTIFY_ADDR 0x00000000
+#define NBL_MAILBOX_BAR_REG 0x00000000
+#define NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR 0x10
+#define NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR 0x20
+#define NBL_MAILBOX_QINFO_CFG_DBG_TABLE_ADDR 0x30
+
+/* -------- MAILBOX -------- */
+
+/* mailbox BAR qinfo_cfg_table */
+struct nbl_mailbox_qinfo_cfg_table {
+ u32 queue_base_addr_l;
+ u32 queue_base_addr_h;
+ u32 queue_size_bwind:4;
+ u32 rsv1:28;
+ u32 queue_rst:1;
+ u32 queue_en:1;
+ u32 dif_err:1;
+ u32 ptr_err:1;
+ u32 rsv2:28;
+};
+
+/* -------- MAILBOX BAR0 ----- */
+/* mailbox qinfo_map_table */
+#define NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id) \
+ (NBL_INTF_HOST_MAILBOX_BASE + 0x00001000 + \
+ (func_id) * sizeof(struct nbl_mailbox_qinfo_map_table))
+
+/* MAILBOX qinfo_map_table */
+struct nbl_mailbox_qinfo_map_table {
+ u32 function:3;
+ u32 devid:5;
+ u32 bus:8;
+ u32 msix_idx:13;
+ u32 msix_idx_valid:1;
+ u32 rsv:2;
+};
+
+/* -------- HOST_PCIE -------- */
+#define NBL_PCIE_HOST_K_PF_MASK_REG (NBL_INTF_HOST_PCIE_BASE + 0x00001004)
+#define NBL_PCIE_HOST_TL_CFG_BUSDEV (NBL_INTF_HOST_PCIE_BASE + 0x11040)
+
+/* -------- HOST_PADPT -------- */
+#define NBL_HOST_PADPT_HOST_CFG_FC_PD_DN (NBL_INTF_HOST_PADPT_BASE + 0x00000160)
+#define NBL_HOST_PADPT_HOST_CFG_FC_PH_DN (NBL_INTF_HOST_PADPT_BASE + 0x00000164)
+#define NBL_HOST_PADPT_HOST_CFG_FC_NPH_DN \
+ (NBL_INTF_HOST_PADPT_BASE + 0x0000016C)
+#define NBL_HOST_PADPT_HOST_CFG_FC_CPLH_UP \
+ (NBL_INTF_HOST_PADPT_BASE + 0x00000170)
+/* host_padpt host_msix_info */
+#define NBL_PADPT_HOST_MSIX_INFO_REG_ARR(vector_id) \
+ (NBL_INTF_HOST_PADPT_BASE + 0x00010000 + \
+ (vector_id) * sizeof(struct nbl_host_msix_info))
+
+struct nbl_host_msix_info {
+ u32 intrl_pnum:16;
+ u32 intrl_rate:16;
+ u32 function:3;
+ u32 devid:5;
+ u32 bus:8;
+ u32 valid:1;
+ u32 msix_mask_en:1;
+ u32 rsv:14;
+};
+
+/* -------- HOST_PCOMPLETER -------- */
+/* pcompleter_host pcompleter_host_virtio_qid_map_table */
+#define NBL_PCOMPLETER_FUNCTION_MSIX_MAP_REG_ARR(i) \
+ (NBL_INTF_HOST_PCOMPLETER_BASE + 0x00004000 + \
+ (i) * sizeof(struct nbl_function_msix_map))
+#define NBL_PCOMPLETER_HOST_MSIX_FID_TABLE(i) \
+ (NBL_INTF_HOST_PCOMPLETER_BASE + 0x0003a000 + \
+ (i) * sizeof(struct nbl_pcompleter_host_msix_fid_table))
+
+struct nbl_pcompleter_host_msix_fid_table {
+ u32 fid:10;
+ u32 vld:1;
+ u32 rsv:21;
+};
+
+struct nbl_function_msix_map {
+ u64 msix_map_base_addr;
+ u32 function:3;
+ u32 devid:5;
+ u32 bus:8;
+ u32 valid:1;
+ u32 rsv0:15;
+ u32 rsv1;
+};
+
+/* ---------- DPED ---------- */
+#define NBL_DPED_VLAN_OFFSET (NBL_DP_DPED_BASE + 0x000003F4)
+#define NBL_DPED_DSCP_OFFSET_0 (NBL_DP_DPED_BASE + 0x000003F8)
+#define NBL_DPED_DSCP_OFFSET_1 (NBL_DP_DPED_BASE + 0x000003FC)
+
+/* DPED hw_edt_prof/ UPED hw_edt_prof */
+struct ped_hw_edit_profile {
+ u32 l4_len:2;
+#define NBL_PED_L4_LEN_MDY_CMD_0 0
+#define NBL_PED_L4_LEN_MDY_CMD_1 1
+#define NBL_PED_L4_LEN_MDY_DISABLE 2
+ u32 l3_len:2;
+#define NBL_PED_L3_LEN_MDY_CMD_0 0
+#define NBL_PED_L3_LEN_MDY_CMD_1 1
+#define NBL_PED_L3_LEN_MDY_DISABLE 2
+ u32 l4_ck:3;
+#define NBL_PED_L4_CKSUM_CMD_0 0
+#define NBL_PED_L4_CKSUM_CMD_1 1
+#define NBL_PED_L4_CKSUM_CMD_2 2
+#define NBL_PED_L4_CKSUM_CMD_3 3
+#define NBL_PED_L4_CKSUM_CMD_4 4
+#define NBL_PED_L4_CKSUM_CMD_5 5
+#define NBL_PED_L4_CKSUM_CMD_6 6
+#define NBL_PED_L4_CKSUM_DISABLE 7
+ u32 l3_ck:1;
+#define NBL_PED_L3_CKSUM_ENABLE 1
+#define NBL_PED_L3_CKSUM_DISABLE 0
+ u32 l4_ck_zero_free:1;
+#define NBL_PED_L4_CKSUM_ZERO_FREE_ENABLE 1
+#define NBL_PED_L4_CKSUM_ZERO_FREE_DISABLE 0
+ u32 rsv:23;
+};
+
+/* ---------- UPED ---------- */
+/* UPED uped_hw_edt_prof */
+#define NBL_UPED_HW_EDT_PROF_TABLE(i) \
+ (NBL_DP_UPED_BASE + 0x00001000 + \
+ (i) * sizeof(struct ped_hw_edit_profile))
+
+/* --------- SHAPING --------- */
+#define NBL_SHAPING_NET(i) \
+ (NBL_DP_SHAPING_BASE + 0x00001800 + \
+ (i) * sizeof(struct nbl_shaping_net))
+
+/* cir 1, bandwidth 1kB/s in protol environment */
+/* cir 1, bandwidth 1Mb/s */
+#define NBL_LR_LEONIS_NET_BUCKET_DEPTH 9600
+
+#define NBL_SHAPING_DPORT_25G_RATE 0x61A8
+#define NBL_SHAPING_DPORT_HALF_25G_RATE 0x30D4
+
+#define NBL_SHAPING_DPORT_100G_RATE 0x1A400
+#define NBL_SHAPING_DPORT_HALF_100G_RATE 0xD200
+
+#define NBL_DSTORE_DROP_XOFF_TH 0xC8
+#define NBL_DSTORE_DROP_XON_TH 0x64
+
+#define NBL_DSTORE_DROP_XOFF_TH_100G 0x1F4
+#define NBL_DSTORE_DROP_XON_TH_100G 0x12C
+
+#define NBL_DSTORE_DROP_XOFF_TH_BOND_MAIN 0x180
+#define NBL_DSTORE_DROP_XON_TH_BOND_MAIN 0x180
+
+#define NBL_DSTORE_DROP_XOFF_TH_BOND_OTHER 0x64
+#define NBL_DSTORE_DROP_XON_TH_BOND_OTHER 0x64
+
+#define NBL_DSTORE_DROP_XOFF_TH_100G_BOND_MAIN 0x2D5
+#define NBL_DSTORE_DROP_XON_TH_100G_BOND_MAIN 0x2BC
+
+#define NBL_DSTORE_DROP_XOFF_TH_100G_BOND_OTHER 0x145
+#define NBL_DSTORE_DROP_XON_TH_100G_BOND_OTHER 0x12C
+
+#define NBL_DSTORE_DISC_BP_TH (NBL_DP_DSTORE_BASE + 0x00000630)
+
+struct dstore_disc_bp_th {
+ u32 xoff_th:10;
+ u32 rsv1:6;
+ u32 xon_th:10;
+ u32 rsv:5;
+ u32 en:1;
+};
+
+struct dsch_psha_en {
+ u32 en:4;
+ u32 rsv:28;
+};
+
+/* SHAPING shaping_net */
+struct nbl_shaping_net {
+ u32 valid:1;
+ u32 depth:19;
+ u32 cir:19;
+ u32 pir:19;
+ u32 cbs:21;
+ u32 pbs:21;
+ u32 rsv:28;
+};
+
+struct nbl_shaping_dport {
+ u32 valid:1;
+ u32 depth:19;
+ u32 cir:19;
+ u32 pir:19;
+ u32 cbs:21;
+ u32 pbs:21;
+ u32 rsv:28;
+};
+
+struct nbl_shaping_dvn_dport {
+ u32 valid:1;
+ u32 depth:19;
+ u32 cir:19;
+ u32 pir:19;
+ u32 cbs:21;
+ u32 pbs:21;
+ u32 rsv:28;
+};
+
+/* ---------- DSCH ---------- */
+/* DSCH dsch maxqid */
+#define NBL_DSCH_HOST_QID_MAX (NBL_DP_DSCH_BASE + 0x00000118)
+#define NBL_DSCH_VN_QUANTA_ADDR (NBL_DP_DSCH_BASE + 0x00000134)
+
+#define NBL_MAX_QUEUE_ID 0x7ff
+#define NBL_HOST_QUANTA 0x8000
+#define NBL_ECPU_QUANTA 0x1000
+
+struct dsch_vn_quanta {
+ u32 h_qua:16;
+ u32 e_qua:16;
+};
+
+/* ---------- DVN ---------- */
+/* DVN dvn_queue_table */
+#define NBL_DVN_ECPU_QUEUE_NUM (NBL_DP_DVN_BASE + 0x0000041C)
+#define NBL_DVN_DESCREQ_NUM_CFG (NBL_DP_DVN_BASE + 0x00000430)
+#define NBL_DVN_DESC_WR_MERGE_TIMEOUT (NBL_DP_DVN_BASE + 0x00000480)
+#define NBL_DVN_DIF_REQ_RD_RO_FLAG (NBL_DP_DVN_BASE + 0x0000045C)
+
+#define DEFAULT_DVN_DESCREQ_NUMCFG 0x00080014
+#define DEFAULT_DVN_100G_DESCREQ_NUMCFG 0x00080020
+
+#define DEFAULT_DVN_DESC_WR_MERGE_TIMEOUT_MAX 0x3FF
+
+struct nbl_dvn_descreq_num_cfg {
+ u32 avring_cfg_num:1; /* spilit ring descreq_num 0:8,1:16 */
+ u32 rsv0:3;
+ /* packet ring descreq_num 0:8,1:12,2:16;3:20,4:24,5:26;6:32,7:32 */
+ u32 packed_l1_num:3;
+ u32 rsv1:25;
+};
+
+struct nbl_dvn_desc_wr_merge_timeout {
+ u32 cfg_cycle:10;
+ u32 rsv:22;
+};
+
+struct nbl_dvn_dif_req_rd_ro_flag {
+ u32 rd_desc_ro_en:1;
+ u32 rd_data_ro_en:1;
+ u32 rd_avring_ro_en:1;
+ u32 rsv:29;
+};
+
+/* ---------- UVN ---------- */
+/* UVN uvn_queue_table */
+
+#define NBL_UVN_DESC_RD_WAIT (NBL_DP_UVN_BASE + 0x0000020C)
+#define NBL_UVN_QUEUE_ERR_MASK (NBL_DP_UVN_BASE + 0x00000224)
+#define NBL_UVN_ECPU_QUEUE_NUM (NBL_DP_UVN_BASE + 0x0000023C)
+#define NBL_UVN_DESC_WR_TIMEOUT (NBL_DP_UVN_BASE + 0x00000214)
+#define NBL_UVN_DIF_REQ_RO_FLAG (NBL_DP_UVN_BASE + 0x00000250)
+#define NBL_UVN_DESC_PREFETCH_INIT (NBL_DP_UVN_BASE + 0x00000204)
+#define NBL_UVN_DESC_PREFETCH_NUM 4
+
+struct uvn_dif_req_ro_flag {
+ u32 avail_rd:1;
+ u32 desc_rd:1;
+ u32 pkt_wr:1;
+ u32 desc_wr:1;
+ u32 rsv:28;
+};
+
+struct uvn_desc_wr_timeout {
+ u32 num:15;
+ u32 mask:1;
+ u32 rsv:16;
+};
+
+struct uvn_queue_err_mask {
+ u32 rsv0:1;
+ u32 buffer_len_err:1;
+ u32 next_err:1;
+ u32 indirect_err:1;
+ u32 split_err:1;
+ u32 dif_err:1;
+ u32 rsv1:26;
+};
+
+struct uvn_desc_prefetch_init {
+ u32 num:8;
+ u32 rsv1:8;
+ u32 sel:1;
+ u32 rsv:15;
+};
+
+/* -------- USTORE -------- */
+#define NBL_USTORE_PKT_LEN_ADDR (NBL_DP_USTORE_BASE + 0x00000108)
+#define NBL_USTORE_PORT_DROP_TH_REG_ARR(port_id) \
+ (NBL_DP_USTORE_BASE + 0x00000150 + \
+ (port_id) * sizeof(struct nbl_ustore_port_drop_th))
+#define NBL_USTORE_BUF_PORT_DROP_PKT(eth_id) \
+ (NBL_DP_USTORE_BASE + 0x00002500 + (eth_id) * sizeof(u32))
+#define NBL_USTORE_BUF_PORT_TRUN_PKT(eth_id) \
+ (NBL_DP_USTORE_BASE + 0x00002540 + (eth_id) * sizeof(u32))
+
+#define NBL_USTORE_SINGLE_ETH_DROP_TH 0xC80
+#define NBL_USTORE_DUAL_ETH_DROP_TH 0x640
+#define NBL_USTORE_QUAD_ETH_DROP_TH 0x320
+
+/* USTORE pkt_len */
+struct ustore_pkt_len {
+ u32 min:7;
+ u32 rsv:8;
+ u32 min_chk_en:1;
+ u32 max:14;
+ u32 rsv2:1;
+ u32 max_chk_len:1;
+};
+
+/* USTORE port_drop_th */
+struct nbl_ustore_port_drop_th {
+ u32 disc_th:12;
+ u32 rsv:19;
+ u32 en:1;
+};
+
+#define NBL_UQM_QUE_TYPE (NBL_DP_UQM_BASE + 0x0000013c)
+#define NBL_UQM_DROP_PKT_CNT (NBL_DP_UQM_BASE + 0x000009C0)
+#define NBL_UQM_DROP_PKT_SLICE_CNT (NBL_DP_UQM_BASE + 0x000009C4)
+#define NBL_UQM_DROP_PKT_LEN_ADD_CNT (NBL_DP_UQM_BASE + 0x000009C8)
+#define NBL_UQM_DROP_HEAD_PNTR_ADD_CNT (NBL_DP_UQM_BASE + 0x000009CC)
+#define NBL_UQM_DROP_WEIGHT_ADD_CNT (NBL_DP_UQM_BASE + 0x000009D0)
+#define NBL_UQM_PORT_DROP_PKT_CNT (NBL_DP_UQM_BASE + 0x000009D4)
+#define NBL_UQM_PORT_DROP_PKT_SLICE_CNT (NBL_DP_UQM_BASE + 0x000009F4)
+#define NBL_UQM_PORT_DROP_PKT_LEN_ADD_CNT (NBL_DP_UQM_BASE + 0x00000A14)
+#define NBL_UQM_PORT_DROP_HEAD_PNTR_ADD_CNT (NBL_DP_UQM_BASE + 0x00000A34)
+#define NBL_UQM_PORT_DROP_WEIGHT_ADD_CNT (NBL_DP_UQM_BASE + 0x00000A54)
+#define NBL_UQM_FWD_DROP_CNT (NBL_DP_UQM_BASE + 0x00000A80)
+#define NBL_UQM_DPORT_DROP_CNT (NBL_DP_UQM_BASE + 0x00000B74)
+
+#define NBL_UQM_PORT_DROP_DEPTH 6
+#define NBL_UQM_DPORT_DROP_DEPTH 16
+
+struct nbl_uqm_que_type {
+ u32 bp_drop:1;
+ u32 rsv:31;
+};
+
+#pragma pack()
+
+#define NBL_BYTES_IN_REG 4
+#define NBL_SHAPING_DPORT_ADDR 0x504700
+#define NBL_SHAPING_DPORT_DWLEN 4
+#define NBL_SHAPING_DPORT_REG(r) \
+ (NBL_SHAPING_DPORT_ADDR + (NBL_SHAPING_DPORT_DWLEN * 4) * (r))
+#define NBL_SHAPING_DVN_DPORT_ADDR 0x504750
+#define NBL_SHAPING_DVN_DPORT_DWLEN 4
+#define NBL_SHAPING_DVN_DPORT_REG(r) \
+ (NBL_SHAPING_DVN_DPORT_ADDR + (NBL_SHAPING_DVN_DPORT_DWLEN * 4) * (r))
+#define NBL_DSCH_PSHA_EN_ADDR 0x404314
+#define NBL_SHAPING_NET_ADDR 0x505800
+#define NBL_SHAPING_NET_DWLEN 4
+#define NBL_SHAPING_NET_REG(r) \
+ (NBL_SHAPING_NET_ADDR + (NBL_SHAPING_NET_DWLEN * 4) * (r))
+
+#define NBL_DPED_L4_CK_CMD_40_ADDR 0x75c338
+#define NBL_DPED_L4_CK_CMD_40_DEPTH 1
+#define NBL_DPED_L4_CK_CMD_40_WIDTH 32
+#define NBL_DPED_L4_CK_CMD_40_DWLEN 1
+union dped_l4_ck_cmd_40_u {
+ struct dped_l4_ck_cmd_40 {
+ u32 value:8; /* [7:0] Default:0x0 RW */
+ u32 len_in_oft:7; /* [14:8] Default:0x0 RW */
+ u32 len_phid:2; /* [16:15] Default:0x0 RW */
+ u32 len_vld:1; /* [17] Default:0x0 RW */
+ u32 data_vld:1; /* [18] Default:0x0 RW */
+ u32 in_oft:7; /* [25:19] Default:0x8 RW */
+ u32 phid:2; /* [27:26] Default:0x3 RW */
+ u32 flag:1; /* [28] Default:0x0 RW */
+ u32 mode:1; /* [29] Default:0x1 RW */
+ u32 rsv:1; /* [30] Default:0x0 RO */
+ u32 en:1; /* [31] Default:0x0 RW */
+ } __packed info;
+ u32 data[NBL_DPED_L4_CK_CMD_40_DWLEN];
+} __packed;
+
+#define NBL_DSTORE_D_DPORT_FC_TH_ADDR 0x704600
+#define NBL_DSTORE_D_DPORT_FC_TH_DEPTH 5
+#define NBL_DSTORE_D_DPORT_FC_TH_WIDTH 32
+#define NBL_DSTORE_D_DPORT_FC_TH_DWLEN 1
+union dstore_d_dport_fc_th_u {
+ struct dstore_d_dport_fc_th {
+ u32 xoff_th:11; /* [10:0] Default:200 RW */
+ u32 rsv1:5; /* [15:11] Default:0x0 RO */
+ u32 xon_th:11; /* [26:16] Default:100 RW */
+ u32 rsv:3; /* [29:27] Default:0x0 RO */
+ u32 fc_set:1; /* [30:30] Default:0x0 RW */
+ u32 fc_en:1; /* [31:31] Default:0x0 RW */
+ } __packed info;
+ u32 data[NBL_DSTORE_D_DPORT_FC_TH_DWLEN];
+} __packed;
+#define NBL_DSTORE_D_DPORT_FC_TH_REG(r) (NBL_DSTORE_D_DPORT_FC_TH_ADDR + \
+ (NBL_DSTORE_D_DPORT_FC_TH_DWLEN * 4) * (r))
+#define NBL_DSTORE_PORT_DROP_TH_ADDR 0x704150
+#define NBL_DSTORE_PORT_DROP_TH_DEPTH 6
+#define NBL_DSTORE_PORT_DROP_TH_WIDTH 32
+#define NBL_DSTORE_PORT_DROP_TH_DWLEN 1
+union dstore_port_drop_th_u {
+ struct dstore_port_drop_th {
+ u32 disc_th:10; /* [9:0] Default:800 RW */
+ u32 rsv:21; /* [30:10] Default:0x0 RO */
+ u32 en:1; /* [31] Default:0x1 RW */
+ } __packed info;
+ u32 data[NBL_DSTORE_PORT_DROP_TH_DWLEN];
+} __packed;
+#define NBL_DSTORE_PORT_DROP_TH_REG(r) (NBL_DSTORE_PORT_DROP_TH_ADDR + \
+ (NBL_DSTORE_PORT_DROP_TH_DWLEN * 4) * (r))
+
+#define NBL_FW_BOARD_CONFIG 0x200
+#define NBL_FW_BOARD_DW3_OFFSET (NBL_FW_BOARD_CONFIG + 12)
+#define NBL_FW_BOARD_DW6_OFFSET (NBL_FW_BOARD_CONFIG + 24)
+union nbl_fw_board_cfg_dw3 {
+ struct board_cfg_dw3 {
+ u32 port_type:1;
+ u32 port_num:7;
+ u32 port_speed:2;
+ u32 gpio_type:3;
+ u32 p4_version:1; /* 0: low version; 1: high version */
+ u32 rsv:18;
+ } __packed info;
+ u32 data;
+};
+
+union nbl_fw_board_cfg_dw6 {
+ struct board_cfg_dw6 {
+ u8 lane_bitmap;
+ u8 eth_bitmap;
+ u16 rsv;
+ } __packed info;
+ u32 data;
+};
+
+#define NBL_LEONIS_QUIRKS_OFFSET 0x00000140
+#define NBL_LEONIS_ILLEGAL_REG_VALUE 0xDEADBEEF
+
#endif
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c
new file mode 100644
index 000000000000..9e0f546f50fc
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c
@@ -0,0 +1,2901 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+#include <linux/device.h>
+#include <linux/io.h>
+#include "nbl_hw_leonis.h"
+#include "nbl_hw_leonis_regs.h"
+
+#define NBL_SEC_BLOCK_SIZE 0x100
+#define NBL_SEC000_SIZE 1
+#define NBL_SEC000_ADDR 0x114150
+#define NBL_SEC001_SIZE 1
+#define NBL_SEC001_ADDR 0x15c190
+#define NBL_SEC002_SIZE 1
+#define NBL_SEC002_ADDR 0x10417c
+#define NBL_SEC003_SIZE 1
+#define NBL_SEC003_ADDR 0x714154
+#define NBL_SEC004_SIZE 1
+#define NBL_SEC004_ADDR 0x75c190
+#define NBL_SEC005_SIZE 1
+#define NBL_SEC005_ADDR 0x70417c
+#define NBL_SEC006_SIZE 512
+#define NBL_SEC006_ADDR 0x8f000
+#define NBL_SEC006_REGI(i) (0x8f000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC007_SIZE 256
+#define NBL_SEC007_ADDR 0x8f800
+#define NBL_SEC007_REGI(i) (0x8f800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC008_SIZE 1024
+#define NBL_SEC008_ADDR 0x90000
+#define NBL_SEC008_REGI(i) (0x90000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC009_SIZE 2048
+#define NBL_SEC009_ADDR 0x94000
+#define NBL_SEC009_REGI(i) (0x94000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC010_SIZE 256
+#define NBL_SEC010_ADDR 0x96000
+#define NBL_SEC010_REGI(i) (0x96000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC011_SIZE 1024
+#define NBL_SEC011_ADDR 0x91000
+#define NBL_SEC011_REGI(i) (0x91000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC012_SIZE 128
+#define NBL_SEC012_ADDR 0x92000
+#define NBL_SEC012_REGI(i) (0x92000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC013_SIZE 64
+#define NBL_SEC013_ADDR 0x92200
+#define NBL_SEC013_REGI(i) (0x92200 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC014_SIZE 64
+#define NBL_SEC014_ADDR 0x92300
+#define NBL_SEC014_REGI(i) (0x92300 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC015_SIZE 1
+#define NBL_SEC015_ADDR 0x8c214
+#define NBL_SEC016_SIZE 1
+#define NBL_SEC016_ADDR 0x8c220
+#define NBL_SEC017_SIZE 1
+#define NBL_SEC017_ADDR 0x8c224
+#define NBL_SEC018_SIZE 1
+#define NBL_SEC018_ADDR 0x8c228
+#define NBL_SEC019_SIZE 1
+#define NBL_SEC019_ADDR 0x8c22c
+#define NBL_SEC020_SIZE 1
+#define NBL_SEC020_ADDR 0x8c1f0
+#define NBL_SEC021_SIZE 1
+#define NBL_SEC021_ADDR 0x8c1f8
+#define NBL_SEC022_SIZE 256
+#define NBL_SEC022_ADDR 0x85f000
+#define NBL_SEC022_REGI(i) (0x85f000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC023_SIZE 128
+#define NBL_SEC023_ADDR 0x85f800
+#define NBL_SEC023_REGI(i) (0x85f800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC024_SIZE 512
+#define NBL_SEC024_ADDR 0x860000
+#define NBL_SEC024_REGI(i) (0x860000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC025_SIZE 1024
+#define NBL_SEC025_ADDR 0x864000
+#define NBL_SEC025_REGI(i) (0x864000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC026_SIZE 256
+#define NBL_SEC026_ADDR 0x866000
+#define NBL_SEC026_REGI(i) (0x866000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC027_SIZE 512
+#define NBL_SEC027_ADDR 0x861000
+#define NBL_SEC027_REGI(i) (0x861000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC028_SIZE 64
+#define NBL_SEC028_ADDR 0x862000
+#define NBL_SEC028_REGI(i) (0x862000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC029_SIZE 32
+#define NBL_SEC029_ADDR 0x862200
+#define NBL_SEC029_REGI(i) (0x862200 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC030_SIZE 32
+#define NBL_SEC030_ADDR 0x862300
+#define NBL_SEC030_REGI(i) (0x862300 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC031_SIZE 1
+#define NBL_SEC031_ADDR 0x85c214
+#define NBL_SEC032_SIZE 1
+#define NBL_SEC032_ADDR 0x85c220
+#define NBL_SEC033_SIZE 1
+#define NBL_SEC033_ADDR 0x85c224
+#define NBL_SEC034_SIZE 1
+#define NBL_SEC034_ADDR 0x85c228
+#define NBL_SEC035_SIZE 1
+#define NBL_SEC035_ADDR 0x85c22c
+#define NBL_SEC036_SIZE 1
+#define NBL_SEC036_ADDR 0xb04200
+#define NBL_SEC037_SIZE 1
+#define NBL_SEC037_ADDR 0xb04230
+#define NBL_SEC038_SIZE 1
+#define NBL_SEC038_ADDR 0xb04234
+#define NBL_SEC039_SIZE 64
+#define NBL_SEC039_ADDR 0xb05800
+#define NBL_SEC039_REGI(i) (0xb05800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC040_SIZE 32
+#define NBL_SEC040_ADDR 0xb05400
+#define NBL_SEC040_REGI(i) (0xb05400 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC041_SIZE 16
+#define NBL_SEC041_ADDR 0xb05500
+#define NBL_SEC041_REGI(i) (0xb05500 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC042_SIZE 1
+#define NBL_SEC042_ADDR 0xb14148
+#define NBL_SEC043_SIZE 1
+#define NBL_SEC043_ADDR 0xb14104
+#define NBL_SEC044_SIZE 1
+#define NBL_SEC044_ADDR 0xb1414c
+#define NBL_SEC045_SIZE 1
+#define NBL_SEC045_ADDR 0xb14150
+#define NBL_SEC046_SIZE 256
+#define NBL_SEC046_ADDR 0xb15000
+#define NBL_SEC046_REGI(i) (0xb15000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC047_SIZE 32
+#define NBL_SEC047_ADDR 0xb15800
+#define NBL_SEC047_REGI(i) (0xb15800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC048_SIZE 1
+#define NBL_SEC048_ADDR 0xb24148
+#define NBL_SEC049_SIZE 1
+#define NBL_SEC049_ADDR 0xb24104
+#define NBL_SEC050_SIZE 1
+#define NBL_SEC050_ADDR 0xb2414c
+#define NBL_SEC051_SIZE 1
+#define NBL_SEC051_ADDR 0xb24150
+#define NBL_SEC052_SIZE 256
+#define NBL_SEC052_ADDR 0xb25000
+#define NBL_SEC052_REGI(i) (0xb25000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC053_SIZE 32
+#define NBL_SEC053_ADDR 0xb25800
+#define NBL_SEC053_REGI(i) (0xb25800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC054_SIZE 1
+#define NBL_SEC054_ADDR 0xb34148
+#define NBL_SEC055_SIZE 1
+#define NBL_SEC055_ADDR 0xb34104
+#define NBL_SEC056_SIZE 1
+#define NBL_SEC056_ADDR 0xb3414c
+#define NBL_SEC057_SIZE 1
+#define NBL_SEC057_ADDR 0xb34150
+#define NBL_SEC058_SIZE 256
+#define NBL_SEC058_ADDR 0xb35000
+#define NBL_SEC058_REGI(i) (0xb35000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC059_SIZE 32
+#define NBL_SEC059_ADDR 0xb35800
+#define NBL_SEC059_REGI(i) (0xb35800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC060_SIZE 1
+#define NBL_SEC060_ADDR 0xe74630
+#define NBL_SEC061_SIZE 1
+#define NBL_SEC061_ADDR 0xe74634
+#define NBL_SEC062_SIZE 64
+#define NBL_SEC062_ADDR 0xe75000
+#define NBL_SEC062_REGI(i) (0xe75000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC063_SIZE 32
+#define NBL_SEC063_ADDR 0xe75480
+#define NBL_SEC063_REGI(i) (0xe75480 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC064_SIZE 16
+#define NBL_SEC064_ADDR 0xe75980
+#define NBL_SEC064_REGI(i) (0xe75980 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC065_SIZE 32
+#define NBL_SEC065_ADDR 0x15f000
+#define NBL_SEC065_REGI(i) (0x15f000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC066_SIZE 32
+#define NBL_SEC066_ADDR 0x75f000
+#define NBL_SEC066_REGI(i) (0x75f000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC067_SIZE 1
+#define NBL_SEC067_ADDR 0xb64108
+#define NBL_SEC068_SIZE 1
+#define NBL_SEC068_ADDR 0xb6410c
+#define NBL_SEC069_SIZE 1
+#define NBL_SEC069_ADDR 0xb64140
+#define NBL_SEC070_SIZE 1
+#define NBL_SEC070_ADDR 0xb64144
+#define NBL_SEC071_SIZE 512
+#define NBL_SEC071_ADDR 0xb65000
+#define NBL_SEC071_REGI(i) (0xb65000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC072_SIZE 32
+#define NBL_SEC072_ADDR 0xb65800
+#define NBL_SEC072_REGI(i) (0xb65800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC073_SIZE 1
+#define NBL_SEC073_ADDR 0x8c210
+#define NBL_SEC074_SIZE 1
+#define NBL_SEC074_ADDR 0x85c210
+#define NBL_SEC075_SIZE 4
+#define NBL_SEC075_ADDR 0x8c1b0
+#define NBL_SEC075_REGI(i) (0x8c1b0 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC076_SIZE 4
+#define NBL_SEC076_ADDR 0x8c1c0
+#define NBL_SEC076_REGI(i) (0x8c1c0 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC077_SIZE 4
+#define NBL_SEC077_ADDR 0x85c1b0
+#define NBL_SEC077_REGI(i) (0x85c1b0 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC078_SIZE 1
+#define NBL_SEC078_ADDR 0x85c1ec
+#define NBL_SEC079_SIZE 1
+#define NBL_SEC079_ADDR 0x8c1ec
+#define NBL_SEC080_SIZE 1
+#define NBL_SEC080_ADDR 0xb04440
+#define NBL_SEC081_SIZE 1
+#define NBL_SEC081_ADDR 0xb04448
+#define NBL_SEC082_SIZE 1
+#define NBL_SEC082_ADDR 0xb14450
+#define NBL_SEC083_SIZE 1
+#define NBL_SEC083_ADDR 0xb24450
+#define NBL_SEC084_SIZE 1
+#define NBL_SEC084_ADDR 0xb34450
+#define NBL_SEC085_SIZE 1
+#define NBL_SEC085_ADDR 0xa04188
+#define NBL_SEC086_SIZE 1
+#define NBL_SEC086_ADDR 0xe74218
+#define NBL_SEC087_SIZE 1
+#define NBL_SEC087_ADDR 0xe7421c
+#define NBL_SEC088_SIZE 1
+#define NBL_SEC088_ADDR 0xe74220
+#define NBL_SEC089_SIZE 1
+#define NBL_SEC089_ADDR 0xe74224
+#define NBL_SEC090_SIZE 1
+#define NBL_SEC090_ADDR 0x75c22c
+#define NBL_SEC091_SIZE 1
+#define NBL_SEC091_ADDR 0x75c230
+#define NBL_SEC092_SIZE 1
+#define NBL_SEC092_ADDR 0x75c238
+#define NBL_SEC093_SIZE 1
+#define NBL_SEC093_ADDR 0x75c244
+#define NBL_SEC094_SIZE 1
+#define NBL_SEC094_ADDR 0x75c248
+#define NBL_SEC095_SIZE 1
+#define NBL_SEC095_ADDR 0x75c250
+#define NBL_SEC096_SIZE 1
+#define NBL_SEC096_ADDR 0x15c230
+#define NBL_SEC097_SIZE 1
+#define NBL_SEC097_ADDR 0x15c234
+#define NBL_SEC098_SIZE 1
+#define NBL_SEC098_ADDR 0x15c238
+#define NBL_SEC099_SIZE 1
+#define NBL_SEC099_ADDR 0x15c23c
+#define NBL_SEC100_SIZE 1
+#define NBL_SEC100_ADDR 0x15c244
+#define NBL_SEC101_SIZE 1
+#define NBL_SEC101_ADDR 0x15c248
+#define NBL_SEC102_SIZE 1
+#define NBL_SEC102_ADDR 0xb6432c
+#define NBL_SEC103_SIZE 1
+#define NBL_SEC103_ADDR 0xb64220
+#define NBL_SEC104_SIZE 1
+#define NBL_SEC104_ADDR 0xb44804
+#define NBL_SEC105_SIZE 1
+#define NBL_SEC105_ADDR 0xb44a00
+#define NBL_SEC106_SIZE 1
+#define NBL_SEC106_ADDR 0xe84210
+#define NBL_SEC107_SIZE 1
+#define NBL_SEC107_ADDR 0xe84214
+#define NBL_SEC108_SIZE 1
+#define NBL_SEC108_ADDR 0xe64228
+#define NBL_SEC109_SIZE 1
+#define NBL_SEC109_ADDR 0x65413c
+#define NBL_SEC110_SIZE 1
+#define NBL_SEC110_ADDR 0x984144
+#define NBL_SEC111_SIZE 1
+#define NBL_SEC111_ADDR 0x114130
+#define NBL_SEC112_SIZE 1
+#define NBL_SEC112_ADDR 0x714138
+#define NBL_SEC113_SIZE 1
+#define NBL_SEC113_ADDR 0x114134
+#define NBL_SEC114_SIZE 1
+#define NBL_SEC114_ADDR 0x71413c
+#define NBL_SEC115_SIZE 1
+#define NBL_SEC115_ADDR 0x90437c
+#define NBL_SEC116_SIZE 32
+#define NBL_SEC116_ADDR 0xb05000
+#define NBL_SEC116_REGI(i) (0xb05000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC117_SIZE 1
+#define NBL_SEC117_ADDR 0xb043e0
+#define NBL_SEC118_SIZE 1
+#define NBL_SEC118_ADDR 0xb043f0
+#define NBL_SEC119_SIZE 5
+#define NBL_SEC119_ADDR 0x8c230
+#define NBL_SEC119_REGI(i) (0x8c230 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC120_SIZE 1
+#define NBL_SEC120_ADDR 0x8c1f4
+#define NBL_SEC121_SIZE 1
+#define NBL_SEC121_ADDR 0x2046c4
+#define NBL_SEC122_SIZE 1
+#define NBL_SEC122_ADDR 0x85c1f4
+#define NBL_SEC123_SIZE 1
+#define NBL_SEC123_ADDR 0x75c194
+#define NBL_SEC124_SIZE 256
+#define NBL_SEC124_ADDR 0xa05000
+#define NBL_SEC124_REGI(i) (0xa05000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC125_SIZE 256
+#define NBL_SEC125_ADDR 0xa06000
+#define NBL_SEC125_REGI(i) (0xa06000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC126_SIZE 256
+#define NBL_SEC126_ADDR 0xa07000
+#define NBL_SEC126_REGI(i) (0xa07000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC127_SIZE 1
+#define NBL_SEC127_ADDR 0x75c204
+#define NBL_SEC128_SIZE 1
+#define NBL_SEC128_ADDR 0x15c204
+#define NBL_SEC129_SIZE 1
+#define NBL_SEC129_ADDR 0x75c208
+#define NBL_SEC130_SIZE (1)
+#define NBL_SEC130_ADDR (0x15c208)
+#define NBL_SEC131_SIZE 1
+#define NBL_SEC131_ADDR 0x75c20c
+#define NBL_SEC132_SIZE 1
+#define NBL_SEC132_ADDR 0x15c20c
+#define NBL_SEC133_SIZE (1)
+#define NBL_SEC133_ADDR (0x75c210)
+#define NBL_SEC134_SIZE 1
+#define NBL_SEC134_ADDR 0x15c210
+#define NBL_SEC135_SIZE 1
+#define NBL_SEC135_ADDR 0x75c214
+#define NBL_SEC136_SIZE 1
+#define NBL_SEC136_ADDR 0x15c214
+#define NBL_SEC137_SIZE 32
+#define NBL_SEC137_ADDR 0x15d000
+#define NBL_SEC137_REGI(i) (0x15d000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC138_SIZE 32
+#define NBL_SEC138_ADDR 0x75d000
+#define NBL_SEC138_REGI(i) (0x75d000 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC139_SIZE 1
+#define NBL_SEC139_ADDR 0x75c310
+#define NBL_SEC140_SIZE 1
+#define NBL_SEC140_ADDR 0x75c314
+#define NBL_SEC141_SIZE 1
+#define NBL_SEC141_ADDR 0x75c340
+#define NBL_SEC142_SIZE 1
+#define NBL_SEC142_ADDR (0x75c344)
+#define NBL_SEC143_SIZE 1
+#define NBL_SEC143_ADDR 0x75c348
+#define NBL_SEC144_SIZE 1
+#define NBL_SEC144_ADDR 0x75c34c
+#define NBL_SEC145_SIZE 32
+#define NBL_SEC145_ADDR 0xb15800
+#define NBL_SEC145_REGI(i) (0xb15800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC146_SIZE 32
+#define NBL_SEC146_ADDR 0xb25800
+#define NBL_SEC146_REGI(i) (0xb25800 + NBL_BYTES_IN_REG * (i))
+#define NBL_SEC147_SIZE 32
+#define NBL_SEC147_ADDR 0xb35800
+#define NBL_SEC147_REGI(i) (0xb35800 + NBL_BYTES_IN_REG * (i))
+
+static const u32 nbl_sec046_1p_data[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000,
+ 0x00077c2b, 0x005c0000, 0x00000000, 0x00008100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00073029, 0x00480000,
+ 0x00000000, 0x00008100, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x20000000, 0x00073029, 0x00480000, 0x70000000, 0x00000020,
+ 0x24140000, 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000,
+ 0x00000009, 0x00000000, 0x00000000, 0x00002100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xb0000000, 0x00000009, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x70000000, 0x00000000, 0x20140000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x70000000, 0x00000000,
+ 0x20140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x38430000, 0x70000006, 0x00000020, 0x24140000, 0x00000020,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x98cb1180, 0x6e36d469, 0x9d8eb91c, 0x87e3ef47, 0xa2931288, 0x08405c5a,
+ 0x73865086, 0x00000080, 0x30140000, 0x00000080, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xb0000000, 0x000b3849, 0x38430000, 0x00000006, 0x0000c100,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xb0000000,
+ 0x00133889, 0x08400000, 0x03865086, 0x4c016100, 0x00000014, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec071_1p_data[] = {
+ 0x00000000, 0x00000000, 0x00113d00, 0x00000000, 0x00000000, 0x00000000,
+ 0xe7029b00, 0x00000000, 0x00000000, 0x43000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x51e00000, 0x00000c9c, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00293d00, 0x00000000,
+ 0x00000000, 0x00000000, 0x67089b00, 0x00000002, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0xb1e00000, 0x0000189c,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00213d00, 0x00000000, 0x00000000, 0x00000000, 0xe7069b00, 0x00000001,
+ 0x00000000, 0x43000000, 0x014b0c70, 0x00000000, 0x00000000, 0x00000000,
+ 0x92600000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00213d00, 0x00000000, 0x00000000, 0x00000000,
+ 0xe7069b00, 0x00000001, 0x00000000, 0x43000000, 0x015b0c70, 0x00000000,
+ 0x00000000, 0x00000000, 0x92600000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00553d00, 0x00000000,
+ 0x00000000, 0x00000000, 0xe6d29a00, 0x000149c4, 0x00000000, 0x4b000000,
+ 0x00000004, 0x00000000, 0x80000000, 0x00022200, 0x62600000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00553d00, 0x00000000, 0x00000000, 0x00000000, 0xe6d2c000, 0x000149c4,
+ 0x00000000, 0x5b000000, 0x00000004, 0x00000000, 0x80000000, 0x00022200,
+ 0x62600000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, 0x00000000, 0x00000000,
+ 0x64d49200, 0x5e556945, 0xc666d89a, 0x4b0001a9, 0x00004c84, 0x00000000,
+ 0x80000000, 0x00022200, 0xc2600000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x006d3d00, 0x00000000,
+ 0x00000000, 0x00000000, 0x6ed4ba00, 0x5ef56bc5, 0xc666d8c0, 0x5b0001a9,
+ 0x00004dc4, 0x00000000, 0x80000000, 0x00022200, 0xc2600000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00700000, 0x00000000, 0x08028000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec046_2p_data[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000,
+ 0x00077c2b, 0x005c0000, 0x00000000, 0x00008100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00073029, 0x00480000,
+ 0x00000000, 0x00008100, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x20000000, 0x00073029, 0x00480000, 0x70000000, 0x00000020,
+ 0x04140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000,
+ 0x00000009, 0x00000000, 0x00000000, 0x00002100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xb0000000, 0x00000009, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x70000000, 0x00000000, 0x00140000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x70000000, 0x00000000,
+ 0x00140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x38430000, 0x70000006, 0x00000020, 0x04140000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x98cb1180, 0x6e36d469, 0x9d8eb91c, 0x87e3ef47, 0xa2931288, 0x08405c5a,
+ 0x73865086, 0x00000080, 0x10140000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xb0000000, 0x000b3849, 0x38430000, 0x00000006, 0x0000c100,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xb0000000,
+ 0x00133889, 0x08400000, 0x03865086, 0x4c016100, 0x00000014, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec071_2p_data[] = {
+ 0x00000000, 0x00000000, 0x00113d00, 0x00000000, 0x00000000, 0x00000000,
+ 0xe7029b00, 0x00000000, 0x00000000, 0x43000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x51e00000, 0x00000c9c, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00293d00, 0x00000000,
+ 0x00000000, 0x00000000, 0x67089b00, 0x00000002, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0xb1e00000, 0x0000189c,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00213d00, 0x00000000, 0x00000000, 0x00000000, 0xe7069b00, 0x00000001,
+ 0x00000000, 0x43000000, 0x014b0c70, 0x00000000, 0x00000000, 0x00000000,
+ 0x92600000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00213d00, 0x00000000, 0x00000000, 0x00000000,
+ 0xe7069b00, 0x00000001, 0x00000000, 0x43000000, 0x015b0c70, 0x00000000,
+ 0x00000000, 0x00000000, 0x92600000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00553d00, 0x00000000,
+ 0x00000000, 0x00000000, 0xe6d29a00, 0x000149c4, 0x00000000, 0x4b000000,
+ 0x00000004, 0x00000000, 0x80000000, 0x00022200, 0x62600000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00553d00, 0x00000000, 0x00000000, 0x00000000, 0xe6d2c000, 0x000149c4,
+ 0x00000000, 0x5b000000, 0x00000004, 0x00000000, 0x80000000, 0x00022200,
+ 0x62600000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, 0x00000000, 0x00000000,
+ 0x64d49200, 0x5e556945, 0xc666d89a, 0x4b0001a9, 0x00004c84, 0x00000000,
+ 0x80000000, 0x00022200, 0xc2600000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x006d3d00, 0x00000000,
+ 0x00000000, 0x00000000, 0x6ed4ba00, 0x5ef56bc5, 0xc666d8c0, 0x5b0001a9,
+ 0x00004dc4, 0x00000000, 0x80000000, 0x00022200, 0xc2600000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00700000, 0x00000000, 0x00028000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec006_data[] = {
+ 0x81008100, 0x00000001, 0x88a88100, 0x00000001, 0x810088a8, 0x00000001,
+ 0x88a888a8, 0x00000001, 0x81000000, 0x00000001, 0x88a80000, 0x00000001,
+ 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x08004000, 0x00000001, 0x86dd6000, 0x00000001,
+ 0x81000000, 0x00000001, 0x88a80000, 0x00000001, 0x08060000, 0x00000001,
+ 0x80350000, 0x00000001, 0x88080000, 0x00000001, 0x88f70000, 0x00000001,
+ 0x88cc0000, 0x00000001, 0x88090000, 0x00000001, 0x89150000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x11006000, 0x00000001,
+ 0x06006000, 0x00000001, 0x02006000, 0x00000001, 0x3a006000, 0x00000001,
+ 0x2f006000, 0x00000001, 0x84006000, 0x00000001, 0x32006000, 0x00000001,
+ 0x2c006000, 0x00000001, 0x3c006000, 0x00000001, 0x2b006000, 0x00000001,
+ 0x00006000, 0x00000001, 0x00004000, 0x00000001, 0x00004000, 0x00000001,
+ 0x20004000, 0x00000001, 0x40004000, 0x00000001, 0x00000000, 0x00000001,
+ 0x11000000, 0x00000001, 0x06000000, 0x00000001, 0x02000000, 0x00000001,
+ 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, 0x84000000, 0x00000001,
+ 0x32000000, 0x00000001, 0x2c000000, 0x00000001, 0x2b000000, 0x00000001,
+ 0x3c000000, 0x00000001, 0x3b000000, 0x00000001, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x11000000, 0x00000001, 0x06000000, 0x00000001,
+ 0x02000000, 0x00000001, 0x3a000000, 0x00000001, 0x2f000000, 0x00000001,
+ 0x84000000, 0x00000001, 0x32000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x2c000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x2b000000, 0x00000001, 0x3c000000, 0x00000001,
+ 0x3b000000, 0x00000001, 0x00000000, 0x00000001, 0x06001072, 0x00000001,
+ 0x06000000, 0x00000001, 0x110017c1, 0x00000001, 0x110012b7, 0x00000001,
+ 0x110012b5, 0x00000001, 0x01000000, 0x00000001, 0x02000000, 0x00000001,
+ 0x3a000000, 0x00000001, 0x11000043, 0x00000001, 0x11000044, 0x00000001,
+ 0x11000222, 0x00000001, 0x11000000, 0x00000001, 0x2f006558, 0x00000001,
+ 0x32000000, 0x00000001, 0x84000000, 0x00000001, 0x00000000, 0x00000001,
+ 0x65582000, 0x00000001, 0x65583000, 0x00000001, 0x6558a000, 0x00000001,
+ 0x6558b000, 0x00000001, 0x65580000, 0x00000001, 0x12b50000, 0x00000001,
+ 0x02000102, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x65580000, 0x00000001, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x81008100, 0x00000001,
+ 0x88a88100, 0x00000001, 0x810088a8, 0x00000001, 0x88a888a8, 0x00000001,
+ 0x81000000, 0x00000001, 0x88a80000, 0x00000001, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x08004000, 0x00000001, 0x86dd6000, 0x00000001, 0x81000000, 0x00000001,
+ 0x88a80000, 0x00000001, 0x08060000, 0x00000001, 0x80350000, 0x00000001,
+ 0x88080000, 0x00000001, 0x88f70000, 0x00000001, 0x88cc0000, 0x00000001,
+ 0x88090000, 0x00000001, 0x89150000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000001, 0x11006000, 0x00000001, 0x06006000, 0x00000001,
+ 0x02006000, 0x00000001, 0x3a006000, 0x00000001, 0x2f006000, 0x00000001,
+ 0x84006000, 0x00000001, 0x32006000, 0x00000001, 0x2c006000, 0x00000001,
+ 0x3c006000, 0x00000001, 0x2b006000, 0x00000001, 0x00006000, 0x00000001,
+ 0x00004000, 0x00000001, 0x00004000, 0x00000001, 0x20004000, 0x00000001,
+ 0x40004000, 0x00000001, 0x00000000, 0x00000001, 0x11000000, 0x00000001,
+ 0x06000000, 0x00000001, 0x02000000, 0x00000001, 0x3a000000, 0x00000001,
+ 0x2f000000, 0x00000001, 0x84000000, 0x00000001, 0x32000000, 0x00000001,
+ 0x2c000000, 0x00000001, 0x2b000000, 0x00000001, 0x3c000000, 0x00000001,
+ 0x3b000000, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x11000000, 0x00000001, 0x06000000, 0x00000001, 0x02000000, 0x00000001,
+ 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, 0x84000000, 0x00000001,
+ 0x32000000, 0x00000001, 0x00000000, 0x00000000, 0x2c000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x2b000000, 0x00000001, 0x3c000000, 0x00000001, 0x3b000000, 0x00000001,
+ 0x00000000, 0x00000001, 0x06001072, 0x00000001, 0x06000000, 0x00000001,
+ 0x110012b7, 0x00000001, 0x01000000, 0x00000001, 0x02000000, 0x00000001,
+ 0x3a000000, 0x00000001, 0x32000000, 0x00000001, 0x84000000, 0x00000001,
+ 0x11000043, 0x00000001, 0x11000044, 0x00000001, 0x11000222, 0x00000001,
+ 0x11000000, 0x00000001, 0x2f006558, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec007_data[] = {
+ 0x10001000, 0x00001000, 0x10000000, 0x00000000, 0x1000ffff, 0x0000ffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000fff, 0x00000fff,
+ 0x1000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff,
+ 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff,
+ 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x10ff0fff,
+ 0xffff0fff, 0x00000fff, 0x1fff0fff, 0x1fff0fff, 0x1fff0fff, 0xffffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff,
+ 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0xffffffff, 0x00ff0000, 0x00ffffff, 0x00ff0000, 0x00ff0000,
+ 0x00ff0000, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ff0000, 0x00ff0000,
+ 0x00ff0001, 0x00ffffff, 0x00ff0000, 0x00ffffff, 0x00ffffff, 0xffffffff,
+ 0x00000fff, 0x00000fff, 0x00000fff, 0x00000fff, 0x00000fff, 0x0000ffff,
+ 0xc0ff0000, 0xc0ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000ffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x10001000, 0x00001000, 0x10000000, 0x00000000,
+ 0x1000ffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00000fff, 0x00000fff, 0x1000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff,
+ 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ff0fff, 0x00ff0fff,
+ 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff,
+ 0x00ff0fff, 0x10ff0fff, 0xffff0fff, 0x00000fff, 0x1fff0fff, 0x1fff0fff,
+ 0x1fff0fff, 0xffffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0xffffffff, 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff, 0x00ff0000, 0x00ffffff,
+ 0x00ff0000, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ff0000, 0x00ff0000, 0x00ff0001, 0x00ffffff, 0x00ff0000, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+};
+
+static const u32 nbl_sec008_data[] = {
+ 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00809190, 0x16009496,
+ 0x00000100, 0x00000000, 0x00809190, 0x16009496, 0x00000100, 0x00000000,
+ 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00800090, 0x12009092,
+ 0x00000100, 0x00000000, 0x00800090, 0x12009092, 0x00000100, 0x00000000,
+ 0x00800000, 0x0e008c8e, 0x00000100, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08909581, 0x00008680,
+ 0x00000200, 0x00000000, 0x10900082, 0x28008680, 0x00000200, 0x00000000,
+ 0x809b0093, 0x00000000, 0x00000100, 0x00000000, 0x809b0093, 0x00000000,
+ 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000,
+ 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000,
+ 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000,
+ 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000,
+ 0x00000100, 0x00000000, 0x009b0000, 0x00000000, 0x00000100, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x009b0000, 0x00000000,
+ 0x00000100, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00ab0085, 0x08000000, 0x00000200, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000200, 0x00000000, 0x00ab0000, 0x00000000, 0x00000200, 0x00000000,
+ 0x40000000, 0x01c180c2, 0x00000300, 0x00000000, 0x00000000, 0x00a089c2,
+ 0x000005f0, 0x00000000, 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000,
+ 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000, 0x00000000, 0x00a089c2,
+ 0x000005f0, 0x00000000, 0x000b0000, 0x00000000, 0x00000200, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00ab0085, 0x08000000,
+ 0x00000300, 0x00000000, 0x00ab0000, 0x00000000, 0x00000300, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000300, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000300, 0x00000000, 0x40000000, 0x01c180c2, 0x00000400, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00ab0085, 0x08000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000400, 0x00000000, 0x00ab0000, 0x00000000, 0x00000400, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000400, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000400, 0x00000000, 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000,
+ 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000, 0x02a00084, 0x08008890,
+ 0x00000600, 0x00000000, 0x02ab848a, 0x08000000, 0x00000500, 0x00000000,
+ 0x02a00084, 0x10008200, 0x00000600, 0x00000000, 0x00ab8f8e, 0x04000000,
+ 0x00000500, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000,
+ 0x00ab8f8e, 0x04000000, 0x00000500, 0x00000000, 0x02ab848f, 0x08000000,
+ 0x00000500, 0x00000000, 0x02ab848f, 0x08000000, 0x00000500, 0x00000000,
+ 0x02ab848f, 0x08000000, 0x00000500, 0x00000000, 0x02ab0084, 0x08000000,
+ 0x00000500, 0x00000000, 0x00a00000, 0x04008280, 0x00000600, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, 0x04ab8e84, 0x0c000000,
+ 0x00000500, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000,
+ 0x00000000, 0x0400ccd0, 0x00000800, 0x00000000, 0x00000000, 0x0800ccd0,
+ 0x00000800, 0x00000000, 0x00000000, 0x0800ccd0, 0x00000800, 0x00000000,
+ 0x00000000, 0x0c00ccd0, 0x00000800, 0x00000000, 0x00000000, 0x0000ccd0,
+ 0x00000800, 0x00000000, 0x00000000, 0x0000ccd0, 0x00000800, 0x00000000,
+ 0x00000000, 0x10008200, 0x00000700, 0x00000000, 0x00000000, 0x08008200,
+ 0x00000700, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ccd0,
+ 0x00000800, 0x00000000, 0x00000000, 0x0000ccd0, 0x00000800, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00808786, 0x16009496, 0x00000900, 0x00000000,
+ 0x00808786, 0x16009496, 0x00000900, 0x00000000, 0x00808786, 0x16009496,
+ 0x00000900, 0x00000000, 0x00808786, 0x16009496, 0x00000900, 0x00000000,
+ 0x00800086, 0x12009092, 0x00000900, 0x00000000, 0x00800086, 0x12009092,
+ 0x00000900, 0x00000000, 0x00800000, 0x0e008c8e, 0x00000900, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x08908192, 0x00008680, 0x00000a00, 0x00000000, 0x10908292, 0x28008680,
+ 0x00000a00, 0x00000000, 0x809b9392, 0x00000000, 0x00000900, 0x00000000,
+ 0x809b9392, 0x00000000, 0x00000900, 0x00000000, 0x009b8f92, 0x00000000,
+ 0x00000900, 0x00000000, 0x009b8f92, 0x00000000, 0x00000900, 0x00000000,
+ 0x009b8f92, 0x00000000, 0x00000900, 0x00000000, 0x009b8f92, 0x00000000,
+ 0x00000900, 0x00000000, 0x009b8f92, 0x00000000, 0x00000900, 0x00000000,
+ 0x009b8f92, 0x00000000, 0x00000900, 0x00000000, 0x009b0092, 0x00000000,
+ 0x00000900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x009b0092, 0x00000000, 0x00000900, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000d00, 0x00000000, 0x00ab0085, 0x08000000, 0x00000a00, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000a00, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000a00, 0x00000000, 0x40000000, 0x01c180c2, 0x00000b00, 0x00000000,
+ 0x00000000, 0x00a089c2, 0x00000df0, 0x00000000, 0x000b0085, 0x00a00000,
+ 0x00000af0, 0x00000000, 0x000b0085, 0x00a00000, 0x00000af0, 0x00000000,
+ 0x00000000, 0x00a089c2, 0x00000df0, 0x00000000, 0x000b0000, 0x00000000,
+ 0x00000a00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000,
+ 0x00ab0085, 0x08000000, 0x00000b00, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000b00, 0x00000000, 0x00ab0000, 0x00000000, 0x00000b00, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000b00, 0x00000000, 0x40000000, 0x01c180c2,
+ 0x00000c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00ab0085, 0x08000000, 0x00000c00, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000c00, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000c00, 0x00000000, 0x00ab0000, 0x00000000, 0x00000c00, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000c00, 0x00000000, 0x01ab0083, 0x0ca00000,
+ 0x00000d0f, 0x00000000, 0x01ab0083, 0x0ca00000, 0x00000d0f, 0x00000000,
+ 0x02ab8a84, 0x08000000, 0x00000d00, 0x00000000, 0x00ab8f8e, 0x04000000,
+ 0x00000d00, 0x00000000, 0x00ab0000, 0x00000000, 0x00000d00, 0x00000000,
+ 0x00ab8f8e, 0x04000000, 0x00000d00, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000d00, 0x00000000, 0x04ab8e84, 0x0c000000, 0x00000d00, 0x00000000,
+ 0x02ab848f, 0x08000000, 0x00000d00, 0x00000000, 0x02ab848f, 0x08000000,
+ 0x00000d00, 0x00000000, 0x02ab848f, 0x08000000, 0x00000d00, 0x00000000,
+ 0x02ab0084, 0x08000000, 0x00000d00, 0x00000000, 0x00ab0000, 0x04000000,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000d00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec009_data[] = {
+ 0x00000000, 0x00000060, 0x00000000, 0x00000090, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000050, 0x00000000, 0x000000a0,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000a0,
+ 0x00000000, 0x00000050, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000800, 0x00000000, 0x00000700, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000900, 0x00000000, 0x00000600,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00008000,
+ 0x00000000, 0x00007000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00009000, 0x00000000, 0x00006000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x0000a000, 0x00000000, 0x00005000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000c0000,
+ 0x00000000, 0x00030000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000d0000, 0x00000000, 0x00020000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x000e0000, 0x00000000, 0x00010000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040,
+ 0x00000000, 0x000000b0, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000070, 0x00000000, 0x00000080, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000090, 0x00000000, 0x00000060,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000080,
+ 0x00000000, 0x00000070, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000700, 0x00000000, 0x00000800, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00007000, 0x00000000, 0x00008000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000,
+ 0x00000000, 0x00070000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000c00, 0x00000000, 0x00000300, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000d00, 0x00000000, 0x00000200,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00600000,
+ 0x00000000, 0x00900000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00d00000, 0x00000000, 0x00200000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00500000, 0x00000000, 0x00a00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00700000,
+ 0x00000000, 0x00800000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00e00000, 0x00000000, 0x00100000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00f00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00f00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00100000, 0x00000000, 0x00e00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00300000, 0x00000000, 0x00c00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000,
+ 0x00000000, 0x00700000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00900000, 0x00000000, 0x00600000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00a00000, 0x00000000, 0x00500000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00b00000,
+ 0x00000000, 0x00400000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000060, 0x00400000, 0x00000090, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000050, 0x00400000, 0x000000a0, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000000a0, 0x00400000,
+ 0x00000050, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000800, 0x00400000, 0x00000700, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000900, 0x00400000, 0x00000600, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00400000,
+ 0x00007000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00009000, 0x00400000, 0x00006000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x0000a000, 0x00400000, 0x00005000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x00400000,
+ 0x00030000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x000d0000, 0x00400000, 0x00020000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x000e0000, 0x00400000, 0x00010000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000070, 0x00400000,
+ 0x00000080, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000700, 0x00400000, 0x00000800, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00007000, 0x00400000, 0x00008000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00400000,
+ 0x00070000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000c00, 0x00400000, 0x00000300, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000d00, 0x00400000, 0x00000200, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00400000,
+ 0x000000b0, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000090, 0x00400000, 0x00000060, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000080, 0x00400000, 0x00000070, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000060, 0x06000000,
+ 0x00000090, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000060, 0x07000000, 0x00000090, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000050, 0x06000000, 0x000000a0, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000050, 0x07000000,
+ 0x000000a0, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x000000a0, 0x06000000, 0x00000050, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x000000a0, 0x07000000, 0x00000050, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000800, 0x06000000,
+ 0x00000700, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000900, 0x06000000, 0x00000600, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00008000, 0x06000000, 0x00007000, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00009000, 0x06000000,
+ 0x00006000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x0000a000, 0x06000000, 0x00005000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x000c0000, 0x06000000, 0x00030000, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000d0000, 0x06000000,
+ 0x00020000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x000e0000, 0x06000000, 0x00010000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000800, 0x07000000, 0x00000700, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000900, 0x07000000,
+ 0x00000600, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00008000, 0x07000000, 0x00007000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00009000, 0x07000000, 0x00006000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x0000a000, 0x07000000,
+ 0x00005000, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x000c0000, 0x07000000, 0x00030000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x000d0000, 0x07000000, 0x00020000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000e0000, 0x07000000,
+ 0x00010000, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000070, 0x06000000, 0x00000080, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000070, 0x07000000, 0x00000080, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000700, 0x06000000,
+ 0x00000800, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00007000, 0x06000000, 0x00008000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00080000, 0x06000000, 0x00070000, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x06000000,
+ 0x00000300, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000d00, 0x06000000, 0x00000200, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000700, 0x07000000, 0x00000800, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00007000, 0x07000000,
+ 0x00008000, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00080000, 0x07000000, 0x00070000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000c00, 0x07000000, 0x00000300, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000d00, 0x07000000,
+ 0x00000200, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000040, 0x06000000, 0x000000b0, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000040, 0x07000000, 0x000000b0, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000090, 0x06000000,
+ 0x00000060, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000090, 0x07000000, 0x00000060, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000080, 0x06000000, 0x00000070, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000080, 0x07000000,
+ 0x00000070, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000060, 0x00c00000, 0x00000090, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000050, 0x00c00000, 0x000000a0, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000000a0, 0x00c00000,
+ 0x00000050, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000800, 0x00c00000, 0x00000700, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000900, 0x00c00000, 0x00000600, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00c00000,
+ 0x00007000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00009000, 0x00c00000, 0x00006000, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x0000a000, 0x00c00000, 0x00005000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x00c00000,
+ 0x00030000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x000d0000, 0x00c00000, 0x00020000, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x000e0000, 0x00c00000, 0x00010000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000070, 0x00c00000,
+ 0x00000080, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000700, 0x00c00000, 0x00000800, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00007000, 0x00c00000, 0x00008000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00c00000,
+ 0x00070000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000c00, 0x00c00000, 0x00000300, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000d00, 0x00c00000, 0x00000200, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00c00000,
+ 0x000000b0, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000090, 0x00c00000, 0x00000060, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000080, 0x00c00000, 0x00000070, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00400000,
+ 0x00b00000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00600000, 0x00400000, 0x00900000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00300000, 0x00400000, 0x00c00000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00500000, 0x00400000,
+ 0x00a00000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00700000, 0x00400000, 0x00800000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00200000, 0x00400000, 0x00d00000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00400000,
+ 0x00700000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00900000, 0x00400000, 0x00600000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00a00000, 0x00400000, 0x00500000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00b00000, 0x00400000,
+ 0x00400000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00400000, 0x00f00000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00f00000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00400000,
+ 0x00e00000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00400000, 0x06000000, 0x00b00000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00400000, 0x07000000, 0x00b00000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00600000, 0x06000000,
+ 0x00900000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00600000, 0x07000000, 0x00900000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00300000, 0x06000000, 0x00c00000, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00300000, 0x07000000,
+ 0x00c00000, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00500000, 0x06000000, 0x00a00000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00500000, 0x07000000, 0x00a00000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00700000, 0x06000000,
+ 0x00800000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00700000, 0x07000000, 0x00800000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00200000, 0x06000000, 0x00d00000, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x07000000,
+ 0x00d00000, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00800000, 0x06000000, 0x00700000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00900000, 0x06000000, 0x00600000, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00a00000, 0x06000000,
+ 0x00500000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00b00000, 0x06000000, 0x00400000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00800000, 0x07000000, 0x00700000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00900000, 0x07000000,
+ 0x00600000, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00a00000, 0x07000000, 0x00500000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00b00000, 0x07000000, 0x00400000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06000000,
+ 0x00f00000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x07000000, 0x00f00000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x00f00000, 0x09000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x06000000,
+ 0x00e00000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x07000000, 0x00f00000, 0x08000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00100000, 0x07000000, 0x00e00000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00c00000,
+ 0x00b00000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00600000, 0x00c00000, 0x00900000, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00300000, 0x00c00000, 0x00c00000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00500000, 0x00c00000,
+ 0x00a00000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00700000, 0x00c00000, 0x00800000, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00200000, 0x00c00000, 0x00d00000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00c00000,
+ 0x00700000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00900000, 0x00c00000, 0x00600000, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00a00000, 0x00c00000, 0x00500000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00b00000, 0x00c00000,
+ 0x00400000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00c00000, 0x00f00000, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x00f00000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00c00000,
+ 0x00e00000, 0x00300000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x000f0000, 0x00400000, 0x00000000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00f00000, 0x00400000, 0x00000000, 0x00b00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000f0000, 0x06000000,
+ 0x00000000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00f00000, 0x06000000, 0x00000000, 0x09000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x000f0000, 0x07000000, 0x00000000, 0x08000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00f00000, 0x07000000,
+ 0x00000000, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x000f0000, 0x00c00000, 0x00000000, 0x00300000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00f00000, 0x00c00000, 0x00000000, 0x00300000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000f0000,
+ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00f00000, 0x00000000, 0x00000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec010_data[] = {
+ 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a,
+ 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x00000000,
+ 0x0000000b, 0x00000008, 0x00000009, 0x0000000f, 0x0000000f, 0x0000000f,
+ 0x0000000f, 0x0000000f, 0x0000000c, 0x0000000d, 0x00000001, 0x00000001,
+ 0x0000000e, 0x00000005, 0x00000002, 0x00000002, 0x00000004, 0x00000003,
+ 0x00000003, 0x00000003, 0x00000003, 0x00000040, 0x00000040, 0x00000040,
+ 0x00000040, 0x00000040, 0x00000040, 0x00000040, 0x00000040, 0x00000040,
+ 0x00000040, 0x00000040, 0x00000045, 0x00000044, 0x00000044, 0x00000044,
+ 0x00000044, 0x00000044, 0x00000041, 0x00000042, 0x00000043, 0x00000046,
+ 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046,
+ 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046,
+ 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046,
+ 0x00000046, 0x00000046, 0x00000046, 0x0000004b, 0x0000004b, 0x0000004a,
+ 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a,
+ 0x0000004a, 0x0000004a, 0x0000004a, 0x00000047, 0x00000047, 0x00000048,
+ 0x00000048, 0x00000049, 0x00000049, 0x0000004c, 0x0000004c, 0x0000004c,
+ 0x0000004c, 0x0000004c, 0x0000004c, 0x0000004c, 0x0000004c, 0x0000004c,
+ 0x0000004c, 0x0000004c, 0x00000051, 0x00000050, 0x00000050, 0x00000050,
+ 0x00000050, 0x00000050, 0x0000004d, 0x0000004e, 0x0000004f, 0x00000052,
+ 0x00000053, 0x00000054, 0x00000054, 0x00000055, 0x00000056, 0x00000057,
+ 0x00000057, 0x00000057, 0x00000057, 0x00000058, 0x00000059, 0x00000059,
+ 0x0000005a, 0x0000005a, 0x0000005b, 0x0000005b, 0x0000005c, 0x0000005c,
+ 0x0000005c, 0x0000005c, 0x0000005d, 0x0000005d, 0x0000005e, 0x0000005e,
+ 0x0000005f, 0x0000005f, 0x0000005f, 0x0000005f, 0x0000005f, 0x0000005f,
+ 0x0000005f, 0x0000005f, 0x00000060, 0x00000060, 0x00000061, 0x00000061,
+ 0x00000061, 0x00000061, 0x00000062, 0x00000063, 0x00000064, 0x00000064,
+ 0x00000065, 0x00000066, 0x00000067, 0x00000067, 0x00000067, 0x00000067,
+ 0x00000068, 0x00000069, 0x00000069, 0x00000040, 0x00000040, 0x00000046,
+ 0x00000046, 0x00000046, 0x00000046, 0x0000004c, 0x0000004c, 0x0000000a,
+ 0x0000000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec011_data[] = {
+ 0x0008002c, 0x00080234, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00080230, 0x00080332, 0x0008063c, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0008002c, 0x00080234,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080230,
+ 0x00080332, 0x00080738, 0x0008083c, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0008002c, 0x00080234, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00080230, 0x00080332, 0x00080738,
+ 0x0008093a, 0x00080a3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00080020, 0x00080228, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00080224, 0x00080326, 0x00080634, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080020, 0x00080228,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080224,
+ 0x00080326, 0x00080730, 0x00080834, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00080020, 0x00080228, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00080224, 0x00080326, 0x00080730,
+ 0x00080932, 0x00080a34, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00090200, 0x00090304, 0x00090408, 0x0009050c,
+ 0x00090610, 0x00090714, 0x00090818, 0x0009121c, 0x0009131e, 0x00000000,
+ 0x00000000, 0x00000000, 0x00090644, 0x00000000, 0x000d8045, 0x000d4145,
+ 0x0009030c, 0x0009041c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00090145, 0x00090944, 0x00000000, 0x00000000, 0x0009061c, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009033a,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00090200, 0x00090304, 0x00090408, 0x0009050c,
+ 0x00090610, 0x00090714, 0x00090818, 0x0009121c, 0x0009131e, 0x00000000,
+ 0x00000000, 0x00000000, 0x0009063d, 0x00090740, 0x000d803f, 0x000d413f,
+ 0x0009030c, 0x0009041c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x0009013f, 0x00090840, 0x000dc93d, 0x000d093d, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0324, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a003e,
+ 0x000a0140, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x000a0324, 0x000a0520, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x000a003e, 0x000a0140, 0x000a0842,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x000a0124, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0224, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x000a003c, 0x000a0037, 0x000ec139, 0x000e0139,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000a0036, 0x000a0138, 0x000a0742, 0x00000000, 0x00000000,
+ 0x000a0d41, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0036,
+ 0x000a0138, 0x00000000, 0x00000000, 0x00000000, 0x000a0d3e, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000a0036, 0x000a0138, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0037, 0x000a0139,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00080020, 0x00080228, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00080224, 0x00080326, 0x00080634,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00080020, 0x00080228, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00080224, 0x00080326, 0x00080730, 0x00080834, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080020, 0x00080228,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080224,
+ 0x00080326, 0x00080730, 0x00080932, 0x00080a34, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009061c, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009033a,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00090200, 0x00090304, 0x00090408, 0x0009050c,
+ 0x00090610, 0x00090714, 0x00090818, 0x0009121c, 0x0009131e, 0x00000000,
+ 0x00000000, 0x00000000, 0x0009063d, 0x00090740, 0x000d803f, 0x000d413f,
+ 0x0009030c, 0x0009041c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x0009013f, 0x00090840, 0x000dc93d, 0x000d093d, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x000a003c, 0x000a0037, 0x000ec139, 0x000e0139, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0036,
+ 0x000a0138, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x000a0036, 0x000a0138, 0x000a0742,
+ 0x00000000, 0x00000000, 0x000a0d41, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000a0036, 0x000a0138, 0x00000000, 0x00000000, 0x00000000,
+ 0x000a0d3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0037, 0x000a0139,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec012_data[] = {
+ 0x00000006, 0x00000001, 0x00000004, 0x00000001, 0x00000006, 0x00000001,
+ 0x00000000, 0x00000001, 0x00000004, 0x00000001, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010, 0x00000001,
+ 0x00000000, 0x00000001, 0x00000040, 0x00000001, 0x00000010, 0x00000001,
+ 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x06200000, 0x00000001, 0x00c00000, 0x00000001,
+ 0x02c00000, 0x00000001, 0x00200000, 0x00000001, 0x00400000, 0x00000001,
+ 0x00700000, 0x00000001, 0x00300000, 0x00000001, 0x00000000, 0x00000001,
+ 0x00a00000, 0x00000001, 0x00b00000, 0x00000001, 0x00e00000, 0x00000001,
+ 0x00500000, 0x00000001, 0x00800000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000001,
+ 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000040, 0x00000001, 0x00000010, 0x00000001,
+ 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00500000, 0x00000001, 0x00700000, 0x00000001, 0x00a00000, 0x00000001,
+ 0x00b00000, 0x00000001, 0x00200000, 0x00000001, 0x00000000, 0x00000001,
+ 0x00300000, 0x00000001, 0x00800000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec013_data[] = {
+ 0xf7fffff0, 0xf7fffff1, 0xfffffff0, 0xf7fffff3, 0xfffffff1, 0xfffffff3,
+ 0xffffffff, 0xffffffff, 0xf7ffff0f, 0xf7ffff0f, 0xffffff0f, 0xffffff0f,
+ 0xffffff0f, 0xffffffff, 0xffffffff, 0xffffffff, 0x100fffff, 0xf10fffff,
+ 0xf10fffff, 0xf70fffff, 0xf70fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff,
+ 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xfffffff1, 0xfffffff3, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff0f, 0xffffff0f,
+ 0xffffff0f, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff,
+ 0xff0fffff, 0xff1fffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+};
+
+static const u32 nbl_sec014_data[] = {
+ 0x00000000, 0x00000001, 0x00000003, 0x00000002, 0x00000004, 0x00000005,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000002, 0x00000003,
+ 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000002,
+ 0x00000003, 0x00000000, 0x00000000, 0x00000004, 0x00000005, 0x00000006,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000001, 0x00000002, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000001, 0x00000001, 0x00000001, 0x00000002, 0x00000003,
+ 0x00000004, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec022_data[] = {
+ 0x81008100, 0x00000001, 0x88a88100, 0x00000001, 0x810088a8, 0x00000001,
+ 0x88a888a8, 0x00000001, 0x81000000, 0x00000001, 0x88a80000, 0x00000001,
+ 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x08004000, 0x00000001, 0x86dd6000, 0x00000001,
+ 0x81000000, 0x00000001, 0x88a80000, 0x00000001, 0x08060000, 0x00000001,
+ 0x80350000, 0x00000001, 0x88080000, 0x00000001, 0x88f70000, 0x00000001,
+ 0x88cc0000, 0x00000001, 0x88090000, 0x00000001, 0x89150000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x11006000, 0x00000001,
+ 0x06006000, 0x00000001, 0x02006000, 0x00000001, 0x3a006000, 0x00000001,
+ 0x2f006000, 0x00000001, 0x84006000, 0x00000001, 0x32006000, 0x00000001,
+ 0x2c006000, 0x00000001, 0x3c006000, 0x00000001, 0x2b006000, 0x00000001,
+ 0x00006000, 0x00000001, 0x00004000, 0x00000001, 0x00004000, 0x00000001,
+ 0x20004000, 0x00000001, 0x40004000, 0x00000001, 0x00000000, 0x00000001,
+ 0x11000000, 0x00000001, 0x06000000, 0x00000001, 0x02000000, 0x00000001,
+ 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, 0x84000000, 0x00000001,
+ 0x32000000, 0x00000001, 0x2c000000, 0x00000001, 0x2b000000, 0x00000001,
+ 0x3c000000, 0x00000001, 0x3b000000, 0x00000001, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x11000000, 0x00000001, 0x06000000, 0x00000001,
+ 0x02000000, 0x00000001, 0x3a000000, 0x00000001, 0x2f000000, 0x00000001,
+ 0x84000000, 0x00000001, 0x32000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x2c000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x2b000000, 0x00000001, 0x3c000000, 0x00000001,
+ 0x3b000000, 0x00000001, 0x00000000, 0x00000001, 0x06001072, 0x00000001,
+ 0x06000000, 0x00000001, 0x110012b7, 0x00000001, 0x01000000, 0x00000001,
+ 0x02000000, 0x00000001, 0x3a000000, 0x00000001, 0x32000000, 0x00000001,
+ 0x84000000, 0x00000001, 0x11000043, 0x00000001, 0x11000044, 0x00000001,
+ 0x11000222, 0x00000001, 0x11000000, 0x00000001, 0x2f006558, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec023_data[] = {
+ 0x10001000, 0x00001000, 0x10000000, 0x00000000, 0x1000ffff, 0x0000ffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000fff, 0x00000fff,
+ 0x1000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff,
+ 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff,
+ 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x10ff0fff,
+ 0xffff0fff, 0x00000fff, 0x1fff0fff, 0x1fff0fff, 0x1fff0fff, 0xffffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff,
+ 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff,
+ 0x00ffffff, 0xffffffff, 0x00ff0000, 0x00ffffff, 0x00ff0000, 0x00ffffff,
+ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ff0000, 0x00ff0000,
+ 0x00ff0001, 0x00ffffff, 0x00ff0000, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff,
+};
+
+static const u32 nbl_sec024_data[] = {
+ 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00809190, 0x16009496,
+ 0x00000100, 0x00000000, 0x00809190, 0x16009496, 0x00000100, 0x00000000,
+ 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00800090, 0x12009092,
+ 0x00000100, 0x00000000, 0x00800090, 0x12009092, 0x00000100, 0x00000000,
+ 0x00800000, 0x0e008c8e, 0x00000100, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08900081, 0x00008680,
+ 0x00000200, 0x00000000, 0x10900082, 0x28008680, 0x00000200, 0x00000000,
+ 0x809b0093, 0x00000000, 0x00000100, 0x00000000, 0x809b0093, 0x00000000,
+ 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000,
+ 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000,
+ 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000,
+ 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000,
+ 0x00000100, 0x00000000, 0x009b0000, 0x00000000, 0x00000100, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x009b0000, 0x00000000,
+ 0x00000100, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00ab0085, 0x08000000, 0x00000200, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000200, 0x00000000, 0x00ab0000, 0x00000000, 0x00000200, 0x00000000,
+ 0x40000000, 0x01c180c2, 0x00000300, 0x00000000, 0x00000000, 0x00a089c2,
+ 0x000005f0, 0x00000000, 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000,
+ 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000, 0x00000000, 0x00a089c2,
+ 0x000005f0, 0x00000000, 0x000b0000, 0x00000000, 0x00000200, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00ab0085, 0x08000000,
+ 0x00000300, 0x00000000, 0x00ab0000, 0x00000000, 0x00000300, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000300, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000300, 0x00000000, 0x40000000, 0x01c180c2, 0x00000400, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00ab0085, 0x08000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000400, 0x00000000, 0x00ab0000, 0x00000000, 0x00000400, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000400, 0x00000000, 0x00ab0000, 0x00000000,
+ 0x00000400, 0x00000000, 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000,
+ 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000, 0x02ab848a, 0x08000000,
+ 0x00000500, 0x00000000, 0x00ab8f8e, 0x04000000, 0x00000500, 0x00000000,
+ 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, 0x00ab8f8e, 0x04000000,
+ 0x00000500, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000,
+ 0x04ab8e84, 0x0c000000, 0x00000500, 0x00000000, 0x02ab848f, 0x08000000,
+ 0x00000500, 0x00000000, 0x02ab848f, 0x08000000, 0x00000500, 0x00000000,
+ 0x02ab848f, 0x08000000, 0x00000500, 0x00000000, 0x02ab0084, 0x08000000,
+ 0x00000500, 0x00000000, 0x00ab0000, 0x04000000, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec025_data[] = {
+ 0x00000060, 0x00000090, 0x00000001, 0x00000000, 0x00000050, 0x000000a0,
+ 0x00000001, 0x00000000, 0x000000a0, 0x00000050, 0x00000001, 0x00000000,
+ 0x00000800, 0x00000700, 0x00000001, 0x00000000, 0x00000900, 0x00000600,
+ 0x00000001, 0x00000000, 0x00008000, 0x00007000, 0x00000001, 0x00000000,
+ 0x00009000, 0x00006000, 0x00000001, 0x00000000, 0x0000a000, 0x00005000,
+ 0x00000001, 0x00000000, 0x000c0000, 0x00030000, 0x00000001, 0x00000000,
+ 0x000d0000, 0x00020000, 0x00000001, 0x00000000, 0x000e0000, 0x00010000,
+ 0x00000001, 0x00000000, 0x00000040, 0x000000b0, 0x00000001, 0x00000000,
+ 0x00000070, 0x00000080, 0x00000001, 0x00000000, 0x00000090, 0x00000060,
+ 0x00000001, 0x00000000, 0x00000080, 0x00000070, 0x00000001, 0x00000000,
+ 0x00000700, 0x00000800, 0x00000001, 0x00000000, 0x00007000, 0x00008000,
+ 0x00000001, 0x00000000, 0x00080000, 0x00070000, 0x00000001, 0x00000000,
+ 0x00000c00, 0x00000300, 0x00000001, 0x00000000, 0x00000d00, 0x00000200,
+ 0x00000001, 0x00000000, 0x00400000, 0x00b00000, 0x00000001, 0x00000000,
+ 0x00600000, 0x00900000, 0x00000001, 0x00000000, 0x00300000, 0x00c00000,
+ 0x00000001, 0x00000000, 0x00500000, 0x00a00000, 0x00000001, 0x00000000,
+ 0x00700000, 0x00800000, 0x00000001, 0x00000000, 0x00000000, 0x00f00000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00f00000, 0x00000001, 0x00000000,
+ 0x00100000, 0x00e00000, 0x00000001, 0x00000000, 0x00200000, 0x00d00000,
+ 0x00000001, 0x00000000, 0x00800000, 0x00700000, 0x00000001, 0x00000000,
+ 0x00900000, 0x00600000, 0x00000001, 0x00000000, 0x00a00000, 0x00500000,
+ 0x00000001, 0x00000000, 0x00b00000, 0x00400000, 0x00000001, 0x00000000,
+ 0x000f0000, 0x00000000, 0x00000001, 0x00000000, 0x00f00000, 0x00000000,
+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec026_data[] = {
+ 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a,
+ 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x00000000,
+ 0x0000000b, 0x00000008, 0x00000009, 0x0000000f, 0x0000000f, 0x0000000f,
+ 0x0000000f, 0x0000000f, 0x0000000c, 0x0000000d, 0x00000001, 0x00000001,
+ 0x0000000e, 0x00000005, 0x00000002, 0x00000002, 0x00000004, 0x00000003,
+ 0x00000003, 0x00000003, 0x00000003, 0x0000000a, 0x0000000a, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec027_data[] = {
+ 0x00080020, 0x00080228, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00080224, 0x00080326, 0x00080634, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080020, 0x00080228,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080224,
+ 0x00080326, 0x00080730, 0x00080834, 0x0008082e, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00080020, 0x00080228, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00080224, 0x00080326, 0x00080730,
+ 0x00080932, 0x00080a34, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0009061c, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x0009033a, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00090200, 0x00090304, 0x00090408, 0x0009050c, 0x00090610, 0x00090714,
+ 0x00090818, 0x0009121c, 0x0009131e, 0x00000000, 0x00000000, 0x00000000,
+ 0x0009063d, 0x00090740, 0x000d803f, 0x000d413f, 0x0009030c, 0x0009041c,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009013f, 0x00090840,
+ 0x000dc93d, 0x000d093d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a003c, 0x000a0037,
+ 0x000ec139, 0x000e0139, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x000a0036, 0x000a0138, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000a0036, 0x000a0138, 0x000a0742, 0x00000000, 0x00000000,
+ 0x000a0d41, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0036,
+ 0x000a0138, 0x00000000, 0x00000000, 0x00000000, 0x000a0d3e, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x000a0037, 0x000a0139, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec028_data[] = {
+ 0x00000006, 0x00000001, 0x00000004, 0x00000001, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00000001,
+ 0x00000010, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00500000, 0x00000001, 0x00700000, 0x00000001,
+ 0x00a00000, 0x00000001, 0x00b00000, 0x00000001, 0x00200000, 0x00000001,
+ 0x00000000, 0x00000001, 0x00300000, 0x00000001, 0x00800000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec029_data[] = {
+ 0xfffffff0, 0xfffffff1, 0xfffffff3, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffff0f, 0xffffff0f, 0xffffff0f, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xff0fffff, 0xff0fffff,
+ 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff, 0xff0fffff, 0xff1fffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff,
+};
+
+static const u32 nbl_sec030_data[] = {
+ 0x00000000, 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000002, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec039_data[] = {
+ 0xfef80000, 0x00000002, 0x000002e0, 0x00000000, 0xfef8013e, 0x00000002,
+ 0x000002e0, 0x00000000, 0x6660013e, 0x726e6802, 0x02224e42, 0x00000000,
+ 0x6660013e, 0x726e6802, 0x02224e42, 0x00000000, 0x66600000, 0x726e6802,
+ 0x02224e42, 0x00000000, 0x66600000, 0x726e6802, 0x02224e42, 0x00000000,
+ 0x66600000, 0x00026802, 0x02224e40, 0x00000000, 0x66627800, 0x00026802,
+ 0x02224e40, 0x00000000, 0x66600000, 0x00026a76, 0x02224e40, 0x00000000,
+ 0x66600000, 0x00026802, 0x00024e40, 0x00000000, 0x66600000, 0x00026802,
+ 0x00024e40, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec040_data[] = {
+ 0x0040fb3f, 0x00000001, 0x0440fb3f, 0x00000001, 0x0502fa00, 0x00000001,
+ 0x0602f900, 0x00000001, 0x0903e600, 0x00000001, 0x0a03e500, 0x00000001,
+ 0x1101e600, 0x00000001, 0x1201e500, 0x00000001, 0x0000ff00, 0x00000001,
+ 0x0008ff07, 0x00000001, 0x00ffff00, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec046_4p_data[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000,
+ 0x00077c2b, 0x005c0000, 0x00000000, 0x00008100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00073029, 0x00480000,
+ 0x00000000, 0x00008100, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x20000000, 0x00073029, 0x00480000, 0x70000000, 0x00000020,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000,
+ 0x00000009, 0x00000000, 0x00000000, 0x00002100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xb0000000, 0x00000009, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x70000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x70000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x38430000, 0x70000006, 0x00000020, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x98cb1180, 0x6e36d469, 0x9d8eb91c, 0x87e3ef47, 0xa2931288, 0x08405c5a,
+ 0x73865086, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xb0000000, 0x000b3849, 0x38430000, 0x00000006, 0x0000c100,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xb0000000,
+ 0x00133889, 0x08400000, 0x03865086, 0x4c016100, 0x00000014, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec047_data[] = {
+ 0x2040dc3f, 0x00000001, 0x2000dcff, 0x00000001, 0x2200dcff, 0x00000001,
+ 0x0008dc01, 0x00000001, 0x0001de00, 0x00000001, 0x2900c4ff, 0x00000001,
+ 0x3100c4ff, 0x00000001, 0x2b00c4ff, 0x00000001, 0x3300c4ff, 0x00000001,
+ 0x2700d8ff, 0x00000001, 0x2300d8ff, 0x00000001, 0x2502d800, 0x00000001,
+ 0x2102d800, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec052_data[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000,
+ 0x000b844c, 0xc8580000, 0x00000006, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0xb0d3668b, 0xb0555e12,
+ 0x03b055c6, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x20000000, 0xa64b3449, 0x405a3cc1, 0x00000006, 0x3d2d3300,
+ 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+ 0x26473429, 0x00482cc1, 0x00000000, 0x00ccd300, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec053_data[] = {
+ 0x0840f03f, 0x00000001, 0x0040f03f, 0x00000001, 0x0140fa3f, 0x00000001,
+ 0x0100fa0f, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec058_data[] = {
+ 0x00000000, 0x00000000, 0x59f89400, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00470000, 0x00000000, 0x3c000000, 0xa2e40006, 0x00000017,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x19fa1400, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x28440000,
+ 0x038e5186, 0x3c000000, 0xa8e40012, 0x00000047, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0001f3d0, 0x00000000,
+ 0x00000000, 0xb0000000, 0x00133889, 0x38c30000, 0x0000000a, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x0001f3d0, 0x00000000, 0x00000000, 0xb0000000,
+ 0x00133889, 0x38c30000, 0x0000000a, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x000113d0, 0x00000000, 0x00000000, 0xb0000000, 0x00073829, 0x00430000,
+ 0x00000000, 0x3c000000, 0x0000000a, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000293d0, 0x00000000,
+ 0x00000000, 0xb0000000, 0x00133889, 0x08400000, 0x03865086, 0x3c000000,
+ 0x00000016, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec059_data[] = {
+ 0x0200e4ff, 0x00000001, 0x0400e2ff, 0x00000001, 0x1300ecff, 0x00000001,
+ 0x1500eaff, 0x00000001, 0x0300e4ff, 0x00000001, 0x0500e2ff, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec062_data[] = {
+ 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b,
+ 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000,
+ 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b,
+ 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000,
+ 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b,
+ 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000,
+ 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b,
+ 0x0000013d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec063_data[] = {
+ 0x0500e2ff, 0x00000001, 0x0900e2ff, 0x00000001, 0x1900e2ff, 0x00000001,
+ 0x1100e2ff, 0x00000001, 0x0100e2ff, 0x00000001, 0x0600e1ff, 0x00000001,
+ 0x0a00e1ff, 0x00000001, 0x1a00e1ff, 0x00000001, 0x1200e1ff, 0x00000001,
+ 0x0200e1ff, 0x00000001, 0x0000fcff, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec065_data[] = {
+ 0x006e120c, 0x006e1210, 0x006e4208, 0x006e4218, 0x00200b02, 0x00200b00,
+ 0x000e1900, 0x000e1906, 0x00580208, 0x00580204, 0x004c0208, 0x004c0207,
+ 0x0002110c, 0x0002110c, 0x0012010c, 0x00100110, 0x0010010c, 0x000a010c,
+ 0x0008010c, 0x00060000, 0x00160000, 0x00140000, 0x001e0000, 0x001e0000,
+ 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000,
+ 0x001e0000, 0x001e0000,
+};
+
+static const u32 nbl_sec066_data[] = {
+ 0x006e120c, 0x006e1210, 0x006e4208, 0x006e4218, 0x00200b02, 0x00200b00,
+ 0x000e1900, 0x000e1906, 0x00580208, 0x00580204, 0x004c0208, 0x004c0207,
+ 0x0002110c, 0x0002110c, 0x0012010c, 0x00100110, 0x0010010c, 0x000a010c,
+ 0x0008010c, 0x00060000, 0x00160000, 0x00140000, 0x001e0000, 0x001e0000,
+ 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000,
+ 0x001e0000, 0x001e0000,
+};
+
+static const u32 nbl_sec071_4p_data[] = {
+ 0x00000000, 0x00000000, 0x00113d00, 0x00000000, 0x00000000, 0x00000000,
+ 0xe7029b00, 0x00000000, 0x00000000, 0x43000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x51e00000, 0x00000c9c, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00293d00, 0x00000000,
+ 0x00000000, 0x00000000, 0x67089b00, 0x00000002, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0xb1e00000, 0x0000189c,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00213d00, 0x00000000, 0x00000000, 0x00000000, 0xe7069b00, 0x00000001,
+ 0x00000000, 0x43000000, 0x014b0c70, 0x00000000, 0x00000000, 0x00000000,
+ 0x92600000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00213d00, 0x00000000, 0x00000000, 0x00000000,
+ 0xe7069b00, 0x00000001, 0x00000000, 0x43000000, 0x015b0c70, 0x00000000,
+ 0x00000000, 0x00000000, 0x92600000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00553d00, 0x00000000,
+ 0x00000000, 0x00000000, 0xe6d29a00, 0x000149c4, 0x00000000, 0x4b000000,
+ 0x00000004, 0x00000000, 0x80000000, 0x00022200, 0x62600000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00553d00, 0x00000000, 0x00000000, 0x00000000, 0xe6d2c000, 0x000149c4,
+ 0x00000000, 0x5b000000, 0x00000004, 0x00000000, 0x80000000, 0x00022200,
+ 0x62600000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, 0x00000000, 0x00000000,
+ 0x64d49200, 0x5e556945, 0xc666d89a, 0x4b0001a9, 0x00004c84, 0x00000000,
+ 0x80000000, 0x00022200, 0xc2600000, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x006d3d00, 0x00000000,
+ 0x00000000, 0x00000000, 0x6ed4ba00, 0x5ef56bc5, 0xc666d8c0, 0x5b0001a9,
+ 0x00004dc4, 0x00000000, 0x80000000, 0x00022200, 0xc2600000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00700000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec072_data[] = {
+ 0x84006aff, 0x00000001, 0x880066ff, 0x00000001, 0x140040ff, 0x00000001,
+ 0x70000cff, 0x00000001, 0x180040ff, 0x00000001, 0x30000cff, 0x00000001,
+ 0x10004cff, 0x00000001, 0x30004cff, 0x00000001, 0x0100ecff, 0x00000001,
+ 0x0300ecff, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec116_data[] = {
+ 0x00000000, 0x00000000, 0x3fff8000, 0x00000007, 0x3fff8000, 0x00000007,
+ 0x3fff8000, 0x00000007, 0x3fff8000, 0x00000003, 0x3fff8000, 0x00000003,
+ 0x3fff8000, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec124_data[] = {
+ 0xfffffffc, 0xffffffff, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000500, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff,
+ 0x00300010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000500, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, 0x00300010, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000500, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfffffffc, 0xffffffff, 0x00300fff, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000580, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff,
+ 0x00301fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000580, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, 0x0030ffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000580, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfffffffc, 0xffffffff, 0x0030ffff, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000580, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff,
+ 0x0030ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000580, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, 0x0030ffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000580, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfffffffc, 0xffffffff, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000500, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000fffe, 0x00000000,
+ 0x00300000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000480, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfffffffc, 0x00ffffff, 0x00300000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000480, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfffffffe, 0x0000000f, 0x00300000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000580, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec125_data[] = {
+ 0xfffffffc, 0x01ffffff, 0x00300000, 0x70000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000480, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x00000001,
+ 0x00300000, 0x70000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000540, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfffffffe, 0x011003ff, 0x00300000, 0x70000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000005c0, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfffffffc, 0x103fffff, 0x00300001, 0x70000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000480, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec126_data[] = {
+ 0xfffffffc, 0xffffffff, 0x00300001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000500, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x000001ff,
+ 0x00300000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x000005c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00002013, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00002013, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0x01ffffff,
+ 0x00300000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000480, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0xfffffffe, 0x00000001, 0x00300000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000540, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const u32 nbl_sec137_data[] = {
+ 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x00000080,
+ 0x00000024, 0x0000017a, 0x0000017a, 0x00000191, 0x00000035, 0x0000017a,
+ 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x000000d2,
+ 0x00000066, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a,
+ 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x0000017a,
+ 0x0000017a, 0x0000017a,
+};
+
+static const u32 nbl_sec138_data[] = {
+ 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x00000080,
+ 0x00000024, 0x0000017a, 0x0000017a, 0x00000191, 0x00000035, 0x0000017a,
+ 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x000000d2,
+ 0x00000066, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a,
+ 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x0000017a,
+ 0x0000017a, 0x0000017a,
+};
+
+void nbl_write_all_regs(struct nbl_hw_mgt *hw_mgt)
+{
+ struct nbl_common_info *common = hw_mgt->common;
+ u8 eth_mode = common->eth_mode;
+ const u32 *nbl_sec046_data;
+ const u32 *nbl_sec071_data;
+ u32 i;
+
+ switch (eth_mode) {
+ case 1:
+ nbl_sec046_data = nbl_sec046_1p_data;
+ nbl_sec071_data = nbl_sec071_1p_data;
+ break;
+ case 2:
+ nbl_sec046_data = nbl_sec046_2p_data;
+ nbl_sec071_data = nbl_sec071_2p_data;
+ break;
+ case 4:
+ nbl_sec046_data = nbl_sec046_4p_data;
+ nbl_sec071_data = nbl_sec071_4p_data;
+ break;
+ default:
+ nbl_sec046_data = nbl_sec046_2p_data;
+ nbl_sec071_data = nbl_sec071_2p_data;
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC006_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC006_REGI(i), nbl_sec006_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC007_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC007_REGI(i), nbl_sec007_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC008_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC008_REGI(i), nbl_sec008_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC009_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC009_REGI(i), nbl_sec009_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC010_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC010_REGI(i), nbl_sec010_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC011_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC011_REGI(i), nbl_sec011_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC012_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC012_REGI(i), nbl_sec012_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC013_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC013_REGI(i), nbl_sec013_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC014_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC014_REGI(i), nbl_sec014_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC022_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC022_REGI(i), nbl_sec022_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC023_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC023_REGI(i), nbl_sec023_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC024_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC024_REGI(i), nbl_sec024_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC025_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC025_REGI(i), nbl_sec025_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC026_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC026_REGI(i), nbl_sec026_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC027_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC027_REGI(i), nbl_sec027_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC028_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC028_REGI(i), nbl_sec028_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC029_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC029_REGI(i), nbl_sec029_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC030_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC030_REGI(i), nbl_sec030_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC039_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC039_REGI(i), nbl_sec039_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC040_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC040_REGI(i), nbl_sec040_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC046_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC046_REGI(i), nbl_sec046_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC047_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC047_REGI(i), nbl_sec047_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC052_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC052_REGI(i), nbl_sec052_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC053_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC053_REGI(i), nbl_sec053_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC058_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC058_REGI(i), nbl_sec058_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC059_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC059_REGI(i), nbl_sec059_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC062_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC062_REGI(i), nbl_sec062_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC063_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC063_REGI(i), nbl_sec063_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC065_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC065_REGI(i), nbl_sec065_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC066_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC066_REGI(i), nbl_sec066_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC071_SIZE; i++) {
+ if ((i + 1) % NBL_SEC_BLOCK_SIZE == 0)
+ nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG);
+
+ nbl_hw_wr32(hw_mgt, NBL_SEC071_REGI(i), nbl_sec071_data[i]);
+ }
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC072_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC072_REGI(i), nbl_sec072_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC116_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC116_REGI(i), nbl_sec116_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC124_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC124_REGI(i), nbl_sec124_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC125_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC125_REGI(i), nbl_sec125_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC126_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC126_REGI(i), nbl_sec126_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC137_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC137_REGI(i), nbl_sec137_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ for (i = 0; i < NBL_SEC138_SIZE; i++)
+ nbl_hw_wr32(hw_mgt, NBL_SEC138_REGI(i), nbl_sec138_data[i]);
+
+ nbl_flush_writes(hw_mgt);
+ nbl_hw_wr32(hw_mgt, NBL_SEC000_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC001_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC002_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC003_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC004_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC005_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC015_ADDR, 0x000f0908);
+ nbl_hw_wr32(hw_mgt, NBL_SEC016_ADDR, 0x10110607);
+ nbl_hw_wr32(hw_mgt, NBL_SEC017_ADDR, 0x383a3032);
+ nbl_hw_wr32(hw_mgt, NBL_SEC018_ADDR, 0x0201453f);
+ nbl_hw_wr32(hw_mgt, NBL_SEC019_ADDR, 0x00000a41);
+ nbl_hw_wr32(hw_mgt, NBL_SEC020_ADDR, 0x000000c8);
+ nbl_hw_wr32(hw_mgt, NBL_SEC021_ADDR, 0x00000400);
+ nbl_hw_wr32(hw_mgt, NBL_SEC031_ADDR, 0x000f0908);
+ nbl_hw_wr32(hw_mgt, NBL_SEC032_ADDR, 0x00001011);
+ nbl_hw_wr32(hw_mgt, NBL_SEC033_ADDR, 0x00003032);
+ nbl_hw_wr32(hw_mgt, NBL_SEC034_ADDR, 0x0201003f);
+ nbl_hw_wr32(hw_mgt, NBL_SEC035_ADDR, 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC036_ADDR, 0x00001701);
+ nbl_hw_wr32(hw_mgt, NBL_SEC037_ADDR, 0x009238a1);
+ nbl_hw_wr32(hw_mgt, NBL_SEC038_ADDR, 0x0000002e);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(0), 0x00000200);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(1), 0x00000300);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(2), 0x00000105);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(3), 0x00000106);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(4), 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(5), 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(6), 0x00000041);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(7), 0x00000082);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(8), 0x00000020);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(9), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(10), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(11), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(12), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(13), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(14), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(15), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC042_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC043_ADDR, 0x00000002);
+ nbl_hw_wr32(hw_mgt, NBL_SEC044_ADDR, 0x28212000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC045_ADDR, 0x00002b29);
+ nbl_hw_wr32(hw_mgt, NBL_SEC048_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC049_ADDR, 0x00000002);
+ nbl_hw_wr32(hw_mgt, NBL_SEC050_ADDR, 0x352b2000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC051_ADDR, 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC054_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC055_ADDR, 0x00000002);
+ nbl_hw_wr32(hw_mgt, NBL_SEC056_ADDR, 0x2b222100);
+ nbl_hw_wr32(hw_mgt, NBL_SEC057_ADDR, 0x00000038);
+ nbl_hw_wr32(hw_mgt, NBL_SEC060_ADDR, 0x24232221);
+ nbl_hw_wr32(hw_mgt, NBL_SEC061_ADDR, 0x0000002e);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(0), 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(1), 0x00000005);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(2), 0x00000011);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(3), 0x00000005);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(4), 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(5), 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(6), 0x00000006);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(7), 0x00000012);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(8), 0x00000006);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(9), 0x00000002);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(10), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(11), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(12), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(13), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(14), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(15), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC067_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC068_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC069_ADDR, 0x22212000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC070_ADDR, 0x3835322b);
+ nbl_hw_wr32(hw_mgt, NBL_SEC073_ADDR, 0x0316a5ff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC074_ADDR, 0x0316a5ff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(0), 0x08802080);
+ nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(1), 0x12a05080);
+ nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(2), 0xffffffff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(3), 0xffffffff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(0), 0x08802080);
+ nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(1), 0x12a05080);
+ nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(2), 0xffffffff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(3), 0xffffffff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(0), 0x08802080);
+ nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(1), 0x12a05080);
+ nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(2), 0xffffffff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(3), 0xffffffff);
+ nbl_hw_wr32(hw_mgt, NBL_SEC078_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC079_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC080_ADDR, 0x0014a248);
+ nbl_hw_wr32(hw_mgt, NBL_SEC081_ADDR, 0x00000d33);
+ nbl_hw_wr32(hw_mgt, NBL_SEC082_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC083_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC084_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC085_ADDR, 0x000144d2);
+ nbl_hw_wr32(hw_mgt, NBL_SEC086_ADDR, 0x31322e2f);
+ nbl_hw_wr32(hw_mgt, NBL_SEC087_ADDR, 0x0a092d2c);
+ nbl_hw_wr32(hw_mgt, NBL_SEC088_ADDR, 0x33050804);
+ nbl_hw_wr32(hw_mgt, NBL_SEC089_ADDR, 0x14131535);
+ nbl_hw_wr32(hw_mgt, NBL_SEC090_ADDR, 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC091_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC092_ADDR, 0x00000008);
+ nbl_hw_wr32(hw_mgt, NBL_SEC093_ADDR, 0x0000000e);
+ nbl_hw_wr32(hw_mgt, NBL_SEC094_ADDR, 0x0000000f);
+ nbl_hw_wr32(hw_mgt, NBL_SEC095_ADDR, 0x00000015);
+ nbl_hw_wr32(hw_mgt, NBL_SEC096_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC097_ADDR, 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC098_ADDR, 0x00000008);
+ nbl_hw_wr32(hw_mgt, NBL_SEC099_ADDR, 0x00000011);
+ nbl_hw_wr32(hw_mgt, NBL_SEC100_ADDR, 0x00000013);
+ nbl_hw_wr32(hw_mgt, NBL_SEC101_ADDR, 0x00000014);
+ nbl_hw_wr32(hw_mgt, NBL_SEC102_ADDR, 0x00000010);
+ nbl_hw_wr32(hw_mgt, NBL_SEC103_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC104_ADDR, 0x0000004d);
+ nbl_hw_wr32(hw_mgt, NBL_SEC105_ADDR, 0x08020a09);
+ nbl_hw_wr32(hw_mgt, NBL_SEC106_ADDR, 0x00000005);
+ nbl_hw_wr32(hw_mgt, NBL_SEC107_ADDR, 0x00000006);
+ nbl_hw_wr32(hw_mgt, NBL_SEC108_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC109_ADDR, 0x00110a09);
+ nbl_hw_wr32(hw_mgt, NBL_SEC110_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC111_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC112_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC113_ADDR, 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC114_ADDR, 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC115_ADDR, 0x00000009);
+ nbl_hw_wr32(hw_mgt, NBL_SEC117_ADDR, 0x0000000a);
+ nbl_hw_wr32(hw_mgt, NBL_SEC118_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(0), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(1), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(2), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(3), 0x00000000);
+ nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(4), 0x00000100);
+ nbl_hw_wr32(hw_mgt, NBL_SEC120_ADDR, 0x0000003c);
+ nbl_hw_wr32(hw_mgt, NBL_SEC121_ADDR, 0x00000003);
+ nbl_hw_wr32(hw_mgt, NBL_SEC122_ADDR, 0x000000bc);
+ nbl_hw_wr32(hw_mgt, NBL_SEC123_ADDR, 0x0000023b);
+ nbl_hw_wr32(hw_mgt, NBL_SEC127_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC128_ADDR, 0x00000001);
+ nbl_hw_wr32(hw_mgt, NBL_SEC129_ADDR, 0x00000002);
+ nbl_hw_wr32(hw_mgt, NBL_SEC130_ADDR, 0x00000002);
+ nbl_hw_wr32(hw_mgt, NBL_SEC131_ADDR, 0x00000003);
+ nbl_hw_wr32(hw_mgt, NBL_SEC132_ADDR, 0x00000003);
+ nbl_hw_wr32(hw_mgt, NBL_SEC133_ADDR, 0x00000004);
+ nbl_hw_wr32(hw_mgt, NBL_SEC134_ADDR, 0x00000004);
+ nbl_hw_wr32(hw_mgt, NBL_SEC135_ADDR, 0x0000000e);
+ nbl_hw_wr32(hw_mgt, NBL_SEC136_ADDR, 0x0000000e);
+ nbl_flush_writes(hw_mgt);
+}
diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h
new file mode 100644
index 000000000000..7df5739904b0
--- /dev/null
+++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Nebula Matrix Limited.
+ */
+
+#ifndef _NBL_HW_LEONIS_REGS_H_
+#define _NBL_HW_LEONIS_REGS_H_
+
+void nbl_write_all_regs(struct nbl_hw_mgt *hw_mgt);
+
+#endif
--
2.47.3
^ permalink raw reply related
* [PATCH v11 net-next 00/11] nbl driver for Nebulamatrix NICs
From: illusion.wang @ 2026-04-08 9:37 UTC (permalink / raw)
To: dimon.zhao, illusion.wang, alvin.wang, sam.chen, netdev
Cc: andrew+netdev, corbet, kuba, linux-doc, lorenzo, pabeni, horms,
vadim.fedorenko, lukas.bulwahn, edumazet, enelsonmoore, skhan,
hkallweit1, open list
This patch series represents the first phase. We plan to integrate it in
two phases: the first phase covers mailbox and chip configuration,
while the second phase involves net dev configuration.
Together, they will provide basic PF-based Ethernet port transmission and
reception capabilities.
After that, we will consider other features, such as ethtool support,
flow management, adminq messaging, VF support, debugfs support, etc.
changes v10->v11
Link to v10:https://lore.kernel.org/netdev/20260401022318.28550-1-illusion.wang@nebula-matrix.com/
1.Issues found by Mohsin
2.AI review issues
changes v9->v10
Link to v9:https://lore.kernel.org/netdev/20260325040048.2313-1-illusion.wang@nebula-matrix.com/
1.Issues found by Jakub
2.AI review issue
changes v8->v9
Link to v8:https://lore.kernel.org/netdev/20260317034533.5600-1-illusion.wang@nebula-matrix.com/
1.Issues found by Jakub
2.AI review issue
Changes v7→v8
Link to v7:https://lore.kernel.org/netdev/20260310120959.22015-1-illusion.wang@nebula-matrix.com/
1.Issues found by Paolo
Changes v6->v7
Link to v6:https://lore.kernel.org/netdev/20260306033451.5196-1-illusion.wang@nebula-matrix.com/
1.Issue found by Jakub
2.AI review issue
Changes v5->v6
Link to V5:https://lore.kernel.org/netdev/20260226073840.3222-1-illusion.wang@nebula-matrix.com/
1.put all standard linux includes files the .c file which needs it & others
--Andrew
2.AI review issue
Changes v4->v5
Link to V4:https://lore.kernel.org/netdev/20260206021608.85381-1-illusion.wang@nebula-matrix.com/
1.change nbl_core to nbl & change ** pointers to *pointers & others
--Andrew
2.AI review issue
Changes v3->v4
Link to v3: https://lore.kernel.org/netdev/20260123011804.31263-1-illusion.wang@nebula-matrix.com
1.cut down to part of a mini driver(mailbox and chip init)
--Jakub Kicinski Simon Horman(some sort of staged approached)
2.modify issues found by ai.
3. Reverse Christmas tree/nbl_err/devm_kfree/remove some macros/
void type to real type/others
--Andrew Lunn
4.change deprecated pci_enable_msix_range to pci_alloc_irq_vectors
5.delete service layer
6.the style of kconfig---Randy Dunlap
7.add to Documentation/networking/device_drivers/ethernet/index.rst
--Simon Horman
Changes v2 →v3
Link to v2: https://lore.kernel.org/netdev/20260109100146.63569-1-illusion.wang@nebula-matrix.com/
1.cut down to a mini driver:
delete vf support
use promisc mode to cut down flow management
drop patch15 in v2
delete adminq msg
delete abnormal handling
delete some unimportant interfaces
2.modify issues found by ai review
Changes v1->v2
Link to v1: https://lore.kernel.org/netdev/20251223035113.31122-1-illusion.wang@nebula-matrix.com/
1.Format Issues and Compilation Issues
- Paolo Abeni
2.add sysfs patch and drop coexisting patch
- Andrew Lunn
3.delete some unimportant ndo operations
4.add machine generated headers patch
5.Modify the issues found in patch1-2 and apply the same fixes to other
patches
6.modify issues found by nipa
illusion.wang (11):
net/nebula-matrix: add minimum nbl build framework
net/nebula-matrix: add our driver architecture
net/nebula-matrix: add chip related definitions
net/nebula-matrix: channel msg value and msg struct
net/nebula-matrix: add channel layer
net/nebula-matrix: add common resource implementation
net/nebula-matrix: add intr resource implementation
net/nebula-matrix: add vsi resource implementation
net/nebula-matrix: add Dispatch layer implementation
net/nebula-matrix: add common/ctrl dev init/reinit operation
net/nebula-matrix: add common dev start/stop operation
.../device_drivers/ethernet/index.rst | 1 +
.../ethernet/nebula-matrix/nbl.rst | 27 +
MAINTAINERS | 10 +
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/nebula-matrix/Kconfig | 34 +
drivers/net/ethernet/nebula-matrix/Makefile | 6 +
.../net/ethernet/nebula-matrix/nbl/Makefile | 16 +
.../nbl/nbl_channel/nbl_channel.c | 843 +++++
.../nbl/nbl_channel/nbl_channel.h | 163 +
.../nebula-matrix/nbl/nbl_common/nbl_common.c | 212 ++
.../nebula-matrix/nbl/nbl_common/nbl_common.h | 34 +
.../net/ethernet/nebula-matrix/nbl/nbl_core.h | 59 +
.../nebula-matrix/nbl/nbl_core/nbl_dev.c | 439 +++
.../nebula-matrix/nbl/nbl_core/nbl_dev.h | 58 +
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.c | 485 +++
.../nebula-matrix/nbl/nbl_core/nbl_dispatch.h | 56 +
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 819 +++++
.../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 493 +++
.../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c | 2901 +++++++++++++++++
.../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h | 11 +
.../nbl_hw_leonis/nbl_resource_leonis.c | 258 ++
.../nbl_hw_leonis/nbl_resource_leonis.h | 10 +
.../nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h | 68 +
.../nebula-matrix/nbl/nbl_hw/nbl_interrupt.c | 246 ++
.../nebula-matrix/nbl/nbl_hw/nbl_interrupt.h | 12 +
.../nebula-matrix/nbl/nbl_hw/nbl_resource.c | 118 +
.../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 116 +
.../nebula-matrix/nbl/nbl_hw/nbl_vsi.c | 51 +
.../nebula-matrix/nbl/nbl_hw/nbl_vsi.h | 11 +
.../nbl/nbl_include/nbl_def_channel.h | 362 ++
.../nbl/nbl_include/nbl_def_common.h | 80 +
.../nbl/nbl_include/nbl_def_dev.h | 16 +
.../nbl/nbl_include/nbl_def_dispatch.h | 43 +
.../nbl/nbl_include/nbl_def_hw.h | 54 +
.../nbl/nbl_include/nbl_def_resource.h | 36 +
.../nbl/nbl_include/nbl_include.h | 79 +
.../nbl/nbl_include/nbl_product_base.h | 18 +
.../net/ethernet/nebula-matrix/nbl/nbl_main.c | 320 ++
39 files changed, 8567 insertions(+)
create mode 100644 Documentation/networking/device_drivers/ethernet/nebula-matrix/nbl.rst
create mode 100644 drivers/net/ethernet/nebula-matrix/Kconfig
create mode 100644 drivers/net/ethernet/nebula-matrix/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/Makefile
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resource_leonis.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.c
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_base.h
create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c
--
2.47.3
^ permalink raw reply
* Re: [PATCH] docs: proc: document ProtectionKey in smaps
From: David Hildenbrand (Arm) @ 2026-04-08 7:54 UTC (permalink / raw)
To: Kevin Brodsky, Randy Dunlap, Dave Hansen, linux-doc
Cc: linux-kernel, Yury Khrustalev, Jonathan Corbet, Shuah Khan,
Dave Hansen, Andrew Morton, Lorenzo Stoakes, Vlastimil Babka,
Mark Rutland, linux-fsdevel, linux-mm
In-Reply-To: <971a511a-f311-4e2f-8b10-85d11e07bb0a@arm.com>
On 4/8/26 09:50, Kevin Brodsky wrote:
> On 08/04/2026 09:39, David Hildenbrand (Arm) wrote:
>> On 4/8/26 09:15, Kevin Brodsky wrote:
>>> Of course that's also possible, "hardware" has to be interpreted in the
>>> context of virtualisation... But granted it is possible to hide features
>>> even on the host with the right kernel parameter, on arm64 at least.
>>>
>>> "If the kernel supports protection keys (pkeys) and the hardware feature
>>> is detected"? Still vague but a little more accurate.
>> Can we just talk about CPU support, to avoid using "system" or "hardware" ?
>
> I'm not sure how this addresses your concern with virtualisation though,
> unless "CPU" is understood as whatever CPU is virtualised? But then the
> same logic could apply to "hardware"...
>
> Either way, I'm really not all that picky about it, I don't mind: "If
> both the kernel and the CPU support protection keys"
LGTM
--
Cheers,
David
^ permalink raw reply
* Re: [PATCH] docs: proc: document ProtectionKey in smaps
From: Kevin Brodsky @ 2026-04-08 7:50 UTC (permalink / raw)
To: David Hildenbrand (Arm), Randy Dunlap, Dave Hansen, linux-doc
Cc: linux-kernel, Yury Khrustalev, Jonathan Corbet, Shuah Khan,
Dave Hansen, Andrew Morton, Lorenzo Stoakes, Vlastimil Babka,
Mark Rutland, linux-fsdevel, linux-mm
In-Reply-To: <efb2dda7-144c-4e00-bd5c-0b57a1244fb1@kernel.org>
On 08/04/2026 09:39, David Hildenbrand (Arm) wrote:
> On 4/8/26 09:15, Kevin Brodsky wrote:
>> On 08/04/2026 09:05, David Hildenbrand (Arm) wrote:
>>>> I think that "system" is too nebulous there, so I would prefer to see
>>>> "hardware" instead.
>>> What if you're running in a VM where the feature is hidden ... ?
>> Of course that's also possible, "hardware" has to be interpreted in the
>> context of virtualisation... But granted it is possible to hide features
>> even on the host with the right kernel parameter, on arm64 at least.
>>
>> "If the kernel supports protection keys (pkeys) and the hardware feature
>> is detected"? Still vague but a little more accurate.
> Can we just talk about CPU support, to avoid using "system" or "hardware" ?
I'm not sure how this addresses your concern with virtualisation though,
unless "CPU" is understood as whatever CPU is virtualised? But then the
same logic could apply to "hardware"...
Either way, I'm really not all that picky about it, I don't mind: "If
both the kernel and the CPU support protection keys"
- Kevin
^ permalink raw reply
* Re: [PATCH] crash: Support high memory reservation for range syntax
From: Youling Tang @ 2026-04-08 7:41 UTC (permalink / raw)
To: Sourabh Jain, Andrew Morton, Baoquan He, Jonathan Corbet
Cc: Vivek Goyal, Dave Young, kexec, linux-kernel, linux-doc,
Youling Tang
In-Reply-To: <d584d383-1862-417d-9251-153d9bcf5626@linux.ibm.com>
Hi, Sourabh
On 4/8/26 12:31, Sourabh Jain wrote:
> Hello Youling,
>
> On 04/04/26 13:11, Youling Tang wrote:
>> From: Youling Tang <tangyouling@kylinos.cn>
>>
>> The crashkernel range syntax (range1:size1[,range2:size2,...]) allows
>> automatic size selection based on system RAM, but it always reserves
>> from low memory. When a large crashkernel is selected, this can
>> consume most of the low memory, causing subsequent hardware
>> hotplug or drivers requiring low memory to fail due to allocation
>> failures.
>
>
> Support for high crashkernel reservation has been added to
> address the above problem.
>
> However, high crashkernel reservation is not supported with
> range-based crashkernel kernel command-line arguments.
> For example: crashkernel=0M-1G:100M,1G-4G:160M,4G-8G:192M
>
> Many users, including some distributions, use range-based
> crashkernel configuration. So, adding support for high crashkernel
> reservation with range-based configuration would be useful.
>
>>
>> Add a new optional conditional suffix ",>boundary" to the crashkernel
>> range syntax. When the selected crashkernel size exceeds the specified
>> boundary, the kernel will automatically apply the same reservation
>> policy as "crashkernel=size,high" - preferring high memory first
>> and reserving the default low memory area.
>
> I think the approach to enable high crashkernel reservation
> with range-based configuration makes the crashkernel kernel
> argument more complex.
>
> If the goal is to support high crashkernel reservation with
> range-based kernel command-line arguments, how about:
>
> crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset],high
>
> instead of using >boundary?
This approach defaults all reservations to high memory. For example,
0M-2G:100M on a 1GB machine reserves 100M + DEFAULT_CRASH_KERNEL_LOW_SIZE,
which wastes memory on small systems.
I prefer small reservations defaulting to low memory, while large
reservations start from high memory (with a default-sized segment
reserved in low memory). This provides better flexibility for
distributions to handle diverse system configurations.
Thanks,
Youling.
>
>>
>> Syntax:
>> crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset],>boundary
>>
>> Example:
>> crashkernel=2G-16G:512M,16G-:1G,>512M
>>
>> This means:
>> - For 2G-16G RAM: reserve 512M normally
>> - For >16G RAM: reserve 1G with high memory preference (since 1G >
>> 512M)
>>
>> For systems with >16G RAM, 1G is selected which exceeds 512M, so it
>> will be reserved from high memory instead of consuming 1G of
>> precious low memory.
>>
>> Signed-off-by: Youling Tang <tangyouling@kylinos.cn>
>> ---
>> Documentation/admin-guide/kdump/kdump.rst | 25 ++++++++-
>> .../admin-guide/kernel-parameters.txt | 2 +-
>> kernel/crash_reserve.c | 56 ++++++++++++++++---
>> 3 files changed, 73 insertions(+), 10 deletions(-)
>>
>> diff --git a/Documentation/admin-guide/kdump/kdump.rst
>> b/Documentation/admin-guide/kdump/kdump.rst
>> index 7587caadbae1..b5ae4556e9ca 100644
>> --- a/Documentation/admin-guide/kdump/kdump.rst
>> +++ b/Documentation/admin-guide/kdump/kdump.rst
>> @@ -293,7 +293,28 @@ crashkernel syntax
>> 2) if the RAM size is between 512M and 2G (exclusive), then
>> reserve 64M
>> 3) if the RAM size is larger than 2G, then reserve 128M
>> -3) crashkernel=size,high and crashkernel=size,low
>> +3) range1:size1[,range2:size2,...][@offset],>boundary
>> + Optionally, the range list can be followed by a conditional suffix
>> + `,>boundary`. When the selected crashkernel size matches the
>> + condition, the kernel will reserve memory using the same policy as
>> + `crashkernel=size,high` (i.e. prefer high memory first and
>> reserve the
>> + default low memory area).
>> +
>> + The syntax is::
>> +
>> + crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset],>boundary
>> + range=start-[end]
>> +
>> + For example::
>> +
>> + crashkernel=2G-16G:512M,16G-:1G,>512M
>> +
>> + This would mean:
>> + 1) if the RAM size is between 2G and 16G (exclusive), then
>> reserve 512M.
>> + 2) if the RAM size is larger than 16G, allocation will behave
>> like
>> + `crashkernel=1G,high`.
>> +
>> +4) crashkernel=size,high and crashkernel=size,low
>> If memory above 4G is preferred, crashkernel=size,high can be
>> used to
>> fulfill that. With it, physical memory is allowed to be
>> allocated from top,
>> @@ -311,7 +332,7 @@ crashkernel syntax
>> crashkernel=0,low
>> -4) crashkernel=size,cma
>> +5) crashkernel=size,cma
>> Reserve additional crash kernel memory from CMA. This
>> reservation is
>> usable by the first system's userspace memory and kernel movable
>> diff --git a/Documentation/admin-guide/kernel-parameters.txt
>> b/Documentation/admin-guide/kernel-parameters.txt
>> index 03a550630644..b2e1892ab4d8 100644
>> --- a/Documentation/admin-guide/kernel-parameters.txt
>> +++ b/Documentation/admin-guide/kernel-parameters.txt
>> @@ -1087,7 +1087,7 @@ Kernel parameters
>> 4G when '@offset' hasn't been specified.
>> See Documentation/admin-guide/kdump/kdump.rst for
>> further details.
>> - crashkernel=range1:size1[,range2:size2,...][@offset]
>> + crashkernel=range1:size1[,range2:size2,...][@offset][,>boundary]
>> [KNL] Same as above, but depends on the memory
>> in the running system. The syntax of range is
>> start-[end] where start and end are both
>> diff --git a/kernel/crash_reserve.c b/kernel/crash_reserve.c
>> index 62e60e0223cf..917738412390 100644
>> --- a/kernel/crash_reserve.c
>> +++ b/kernel/crash_reserve.c
>> @@ -254,15 +254,47 @@ static __init char *get_last_crashkernel(char
>> *cmdline,
>> return ck_cmdline;
>> }
>> +/*
>> + * This function parses command lines in the format
>> + *
>> + * crashkernel=ramsize-range:size[,...][@offset],>boundary
>> + */
>> +static void __init parse_crashkernel_boundary(char *ck_cmdline,
>> + unsigned long long *boundary)
>> +{
>> + char *cur = ck_cmdline, *next;
>> + char *first_gt = false;
>> +
>> + first_gt = strchr(cur, '>');
>> + if (!first_gt)
>> + return;
>> +
>> + cur = first_gt + 1;
>> + if (*cur == '\0' || *cur == ' ' || *cur == ',') {
>> + pr_warn("crashkernel: '>' specified without boundary size,
>> ignoring\n");
>> + return;
>> + }
>> +
>> + *boundary = memparse(cur, &next);
>> + if (cur == next) {
>> + pr_warn("crashkernel: invalid boundary size after '>'\n");
>> + return;
>> + }
>> +}
>> +
>> static int __init __parse_crashkernel(char *cmdline,
>> unsigned long long system_ram,
>> unsigned long long *crash_size,
>> unsigned long long *crash_base,
>> - const char *suffix)
>> + const char *suffix,
>> + bool *high,
>> + unsigned long long *low_size)
>> {
>> char *first_colon, *first_space;
>> char *ck_cmdline;
>> char *name = "crashkernel=";
>> + unsigned long long boundary = 0;
>> + int ret;
>> BUG_ON(!crash_size || !crash_base);
>> *crash_size = 0;
>> @@ -283,10 +315,20 @@ static int __init __parse_crashkernel(char
>> *cmdline,
>> */
>> first_colon = strchr(ck_cmdline, ':');
>> first_space = strchr(ck_cmdline, ' ');
>> - if (first_colon && (!first_space || first_colon < first_space))
>> - return parse_crashkernel_mem(ck_cmdline, system_ram,
>> + if (first_colon && (!first_space || first_colon < first_space)) {
>> + ret = parse_crashkernel_mem(ck_cmdline, system_ram,
>> crash_size, crash_base);
>> + /* Handle optional ',>boundary' condition for range ':'
>> syntax only. */
>> + parse_crashkernel_boundary(ck_cmdline, &boundary);
>> + if (!ret && *crash_size > boundary) {
>> + *high = true;
>> + *low_size = DEFAULT_CRASH_KERNEL_LOW_SIZE;
>> + }
>> +
>> + return ret;
>> + }
>> +
>> return parse_crashkernel_simple(ck_cmdline, crash_size,
>> crash_base);
>> }
>> @@ -310,7 +352,7 @@ int __init parse_crashkernel(char *cmdline,
>> /* crashkernel=X[@offset] */
>> ret = __parse_crashkernel(cmdline, system_ram, crash_size,
>> - crash_base, NULL);
>> + crash_base, NULL, high, low_size);
>> #ifdef CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
>> /*
>> * If non-NULL 'high' passed in and no normal crashkernel
>> @@ -318,7 +360,7 @@ int __init parse_crashkernel(char *cmdline,
>> */
>> if (high && ret == -ENOENT) {
>> ret = __parse_crashkernel(cmdline, 0, crash_size,
>> - crash_base, suffix_tbl[SUFFIX_HIGH]);
>> + crash_base, suffix_tbl[SUFFIX_HIGH], high, low_size);
>> if (ret || !*crash_size)
>> return -EINVAL;
>> @@ -327,7 +369,7 @@ int __init parse_crashkernel(char *cmdline,
>> * is not allowed.
>> */
>> ret = __parse_crashkernel(cmdline, 0, low_size,
>> - crash_base, suffix_tbl[SUFFIX_LOW]);
>> + crash_base, suffix_tbl[SUFFIX_LOW], high, low_size);
>> if (ret == -ENOENT) {
>> *low_size = DEFAULT_CRASH_KERNEL_LOW_SIZE;
>> ret = 0;
>> @@ -344,7 +386,7 @@ int __init parse_crashkernel(char *cmdline,
>> */
>> if (cma_size)
>> __parse_crashkernel(cmdline, 0, cma_size,
>> - &cma_base, suffix_tbl[SUFFIX_CMA]);
>> + &cma_base, suffix_tbl[SUFFIX_CMA], high, low_size);
>> #endif
>> if (!*crash_size)
>> ret = -EINVAL;
>
^ permalink raw reply
* Re: [PATCH v10 07/21] gpu: nova-core: mm: Add TLB flush support
From: Alexandre Courbot @ 2026-04-08 7:40 UTC (permalink / raw)
To: Matthew Brost
Cc: Joel Fernandes, linux-kernel, Miguel Ojeda, Boqun Feng, Gary Guo,
Bjorn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Dave Airlie, Daniel Almeida,
Koen Koning, dri-devel, rust-for-linux, Nikola Djukic,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Jonathan Corbet, Alex Deucher, Christian Koenig,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
Huang Rui, Matthew Auld, Lucas De Marchi, Thomas Hellstrom,
Helge Deller, Alex Gaynor, Boqun Feng, John Hubbard,
Alistair Popple, Timur Tabi, Edwin Peer, Andrea Righi,
Andy Ritger, Zhi Wang, Balbir Singh, Philipp Stanner,
Elle Rhumsaa, alexeyi, Eliot Courtney, joel, linux-doc, amd-gfx,
intel-gfx, intel-xe, linux-fbdev
In-Reply-To: <adSSrZp6a551xNTu@gsse-cloud1.jf.intel.com>
On Tue Apr 7, 2026 at 2:14 PM JST, Matthew Brost wrote:
> On Mon, Apr 06, 2026 at 06:10:07PM -0400, Joel Fernandes wrote:
>>
>>
>> On 4/6/2026 5:24 PM, Joel Fernandes wrote:
>> >
>> >
>> > On 4/2/2026 1:59 AM, Matthew Brost wrote:
>> >> On Tue, Mar 31, 2026 at 05:20:34PM -0400, Joel Fernandes wrote:
>> >>> Add TLB (Translation Lookaside Buffer) flush support for GPU MMU.
>> >>>
>> >>> After modifying page table entries, the GPU's TLB must be invalidated
>> >>> to ensure the new mappings take effect. The Tlb struct provides flush
>> >>> functionality through BAR0 registers.
>> >>>
>> >>> The flush operation writes the page directory base address and triggers
>> >>> an invalidation, polling for completion with a 2 second timeout matching
>> >>> the Nouveau driver.
>> >>>
>> >>> Cc: Nikola Djukic <ndjukic@nvidia.com>
>> >>> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
>> >>> ---
>> >>> drivers/gpu/nova-core/mm.rs | 1 +
>> >>> drivers/gpu/nova-core/mm/tlb.rs | 95 +++++++++++++++++++++++++++++++++
>> >>> drivers/gpu/nova-core/regs.rs | 42 +++++++++++++++
>> >>> 3 files changed, 138 insertions(+)
>> >>> create mode 100644 drivers/gpu/nova-core/mm/tlb.rs
>> >>>
>> >>> diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs
>> >>> index 8f3089a5fa88..cfe9cbe11d57 100644
>> >>> --- a/drivers/gpu/nova-core/mm.rs
>> >>> +++ b/drivers/gpu/nova-core/mm.rs
>> >>> @@ -5,6 +5,7 @@
>> >>> #![expect(dead_code)]
>> >>>
>> >>> pub(crate) mod pramin;
>> >>> +pub(crate) mod tlb;
>> >>>
>> >>> use kernel::sizes::SZ_4K;
>> >>>
>> >>> diff --git a/drivers/gpu/nova-core/mm/tlb.rs b/drivers/gpu/nova-core/mm/tlb.rs
>> >>> new file mode 100644
>> >>> index 000000000000..cd3cbcf4c739
>> >>> --- /dev/null
>> >>> +++ b/drivers/gpu/nova-core/mm/tlb.rs
>> >>> @@ -0,0 +1,95 @@
>> >>> +// SPDX-License-Identifier: GPL-2.0
>> >>> +
>> >>> +//! TLB (Translation Lookaside Buffer) flush support for GPU MMU.
>> >>> +//!
>> >>> +//! After modifying page table entries, the GPU's TLB must be flushed to
>> >>> +//! ensure the new mappings take effect. This module provides TLB flush
>> >>> +//! functionality for virtual memory managers.
>> >>> +//!
>> >>> +//! # Example
>> >>> +//!
>> >>> +//! ```ignore
>> >>> +//! use crate::mm::tlb::Tlb;
>> >>> +//!
>> >>> +//! fn page_table_update(tlb: &Tlb, pdb_addr: VramAddress) -> Result<()> {
>> >>> +//! // ... modify page tables ...
>> >>> +//!
>> >>> +//! // Flush TLB to make changes visible (polls for completion).
>> >>> +//! tlb.flush(pdb_addr)?;
>> >>> +//!
>> >>> +//! Ok(())
>> >>> +//! }
>> >>> +//! ```
>> >>> +
>> >>> +use kernel::{
>> >>> + devres::Devres,
>> >>> + io::poll::read_poll_timeout,
>> >>> + io::Io,
>> >>> + new_mutex,
>> >>> + prelude::*,
>> >>> + sync::{
>> >>> + Arc,
>> >>> + Mutex, //
>> >>> + },
>> >>> + time::Delta, //
>> >>> +};
>> >>> +
>> >>> +use crate::{
>> >>> + driver::Bar0,
>> >>> + mm::VramAddress,
>> >>> + regs, //
>> >>> +};
>> >>> +
>> >>> +/// TLB manager for GPU translation buffer operations.
>> >>> +#[pin_data]
>> >>> +pub(crate) struct Tlb {
>> >>> + bar: Arc<Devres<Bar0>>,
>> >>> + /// TLB flush serialization lock: This lock is acquired during the
>> >>> + /// DMA fence signalling critical path. It must NEVER be held across any
>> >>> + /// reclaimable CPU memory allocations because the memory reclaim path can
>> >>> + /// call `dma_fence_wait()`, which would deadlock with this lock held.
>> >>> + #[pin]
>> >>> + lock: Mutex<()>,
>> >>> +}
>> >>> +
>> >>> +impl Tlb {
>> >>> + /// Create a new TLB manager.
>> >>> + pub(super) fn new(bar: Arc<Devres<Bar0>>) -> impl PinInit<Self> {
>> >>> + pin_init!(Self {
>> >>> + bar,
>> >>> + lock <- new_mutex!((), "tlb_flush"),
>> >>> + })
>> >>> + }
>> >>> +
>> >>> + /// Flush the GPU TLB for a specific page directory base.
>> >>> + ///
>> >>> + /// This invalidates all TLB entries associated with the given PDB address.
>> >>> + /// Must be called after modifying page table entries to ensure the GPU sees
>> >>> + /// the updated mappings.
>> >>> + pub(crate) fn flush(&self, pdb_addr: VramAddress) -> Result {
>> >>
>> >> This landed on my list randomly, so I took a look.
>> >>
>> >> Wouldn’t you want to virtualize the invalidation based on your device?
>> >> For example, what if you need to register interface changes on future hardware?
>> >
>> > Good point, for future hardware it indeed makes sense. I will do that.
>> Actually, at least in the future as far as I can see, the register definitions
>> are the same for TLB invalidation are the same, so we are good and I will not be
>> making any change in this regard.
>>
>> But, thanks for raising the point and forcing me to double check!
>>
>
> Not my driver, but this looks like a classic “works now” change that may
> not hold up later, which is why I replied to something that isn’t really
> my business.
>
> Again, not my area, but I’ve been through this before. Generally,
> getting the abstractions right up front pays off.
Our policy so far has been to introduce abstractions when there is a
justifiable hardware difference within the (reduced) set of GPUs that we
support. Adding HALs imply using virtual calls, which are harder to
trace, or monomorphization using generic types, which complicate the
code (and are hard to justify when there is only one implementation).
`Tlb` is already an abstraction of sorts; the register accesses are
well-contained within this leaf module, so if the need arises to support
a different scheme this can be done transparently to callers, which is
what matter imho.
^ permalink raw reply
* Re: [PATCH] docs: proc: document ProtectionKey in smaps
From: David Hildenbrand (Arm) @ 2026-04-08 7:39 UTC (permalink / raw)
To: Kevin Brodsky, Randy Dunlap, Dave Hansen, linux-doc
Cc: linux-kernel, Yury Khrustalev, Jonathan Corbet, Shuah Khan,
Dave Hansen, Andrew Morton, Lorenzo Stoakes, Vlastimil Babka,
Mark Rutland, linux-fsdevel, linux-mm
In-Reply-To: <fee59f61-cf62-4a60-9d8a-4543a02a9c48@arm.com>
On 4/8/26 09:15, Kevin Brodsky wrote:
> On 08/04/2026 09:05, David Hildenbrand (Arm) wrote:
>>> I think that "system" is too nebulous there, so I would prefer to see
>>> "hardware" instead.
>> What if you're running in a VM where the feature is hidden ... ?
>
> Of course that's also possible, "hardware" has to be interpreted in the
> context of virtualisation... But granted it is possible to hide features
> even on the host with the right kernel parameter, on arm64 at least.
>
> "If the kernel supports protection keys (pkeys) and the hardware feature
> is detected"? Still vague but a little more accurate.
Can we just talk about CPU support, to avoid using "system" or "hardware" ?
--
Cheers,
David
^ permalink raw reply
* Re: [PATCH v10 01/21] gpu: nova-core: gsp: Return GspStaticInfo from boot()
From: Alexandre Courbot @ 2026-04-08 7:34 UTC (permalink / raw)
To: Joel Fernandes
Cc: linux-kernel, Miguel Ojeda, Boqun Feng, Gary Guo, Bjorn Roy Baron,
Benno Lossin, Andreas Hindborg, Alice Ryhl, Trevor Gross,
Danilo Krummrich, Dave Airlie, Daniel Almeida, Koen Koning,
dri-devel, rust-for-linux, Nikola Djukic, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Jonathan Corbet, Alex Deucher, Christian Koenig, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Huang Rui,
Matthew Auld, Matthew Brost, Lucas De Marchi, Thomas Hellstrom,
Helge Deller, Alex Gaynor, Boqun Feng, John Hubbard,
Alistair Popple, Timur Tabi, Edwin Peer, Andrea Righi,
Andy Ritger, Zhi Wang, Balbir Singh, Philipp Stanner,
Elle Rhumsaa, alexeyi, Eliot Courtney, joel, linux-doc, amd-gfx,
intel-gfx, intel-xe, linux-fbdev
In-Reply-To: <20260331212048.2229260-2-joelagnelf@nvidia.com>
On Wed Apr 1, 2026 at 6:20 AM JST, Joel Fernandes wrote:
> Refactor the GSP boot function to return only the GspStaticInfo,
> removing the FbLayout from the return tuple.
We are not returning the `FbLayout` - that bit was introduced from an
earlier revision of this series and is not in the original code.
^ permalink raw reply
* Re: [PATCH v10 02/21] gpu: nova-core: gsp: Extract usable FB region from GSP
From: Alexandre Courbot @ 2026-04-08 7:33 UTC (permalink / raw)
To: Joel Fernandes
Cc: linux-kernel, Miguel Ojeda, Boqun Feng, Gary Guo, Bjorn Roy Baron,
Benno Lossin, Andreas Hindborg, Alice Ryhl, Trevor Gross,
Danilo Krummrich, Dave Airlie, Daniel Almeida, Koen Koning,
dri-devel, rust-for-linux, Nikola Djukic, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Jonathan Corbet, Alex Deucher, Christian Koenig, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Huang Rui,
Matthew Auld, Matthew Brost, Lucas De Marchi, Thomas Hellstrom,
Helge Deller, Alex Gaynor, Boqun Feng, John Hubbard,
Alistair Popple, Timur Tabi, Edwin Peer, Andrea Righi,
Andy Ritger, Zhi Wang, Balbir Singh, Philipp Stanner,
Elle Rhumsaa, alexeyi, Eliot Courtney, joel, linux-doc, amd-gfx,
intel-gfx, intel-xe, linux-fbdev
In-Reply-To: <20260331212048.2229260-3-joelagnelf@nvidia.com>
On Wed Apr 1, 2026 at 6:20 AM JST, Joel Fernandes wrote:
> Add first_usable_fb_region() to GspStaticConfigInfo to extract the first
> usable FB region from GSP's fbRegionInfoParams. Usable regions are those
> that are not reserved or protected.
>
> The extracted region is stored in GetGspStaticInfoReply and exposed as
> usable_fb_region field for use by the memory subsystem.
>
> Cc: Nikola Djukic <ndjukic@nvidia.com>
> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
> ---
> drivers/gpu/nova-core/gsp/commands.rs | 11 ++++--
> drivers/gpu/nova-core/gsp/fw/commands.rs | 44 +++++++++++++++++++++++-
> 2 files changed, 52 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
> index c89c7b57a751..41742c1633c8 100644
> --- a/drivers/gpu/nova-core/gsp/commands.rs
> +++ b/drivers/gpu/nova-core/gsp/commands.rs
> @@ -4,6 +4,7 @@
> array,
> convert::Infallible,
> ffi::FromBytesUntilNulError,
> + ops::Range,
> str::Utf8Error, //
> };
>
> @@ -189,22 +190,28 @@ fn init(&self) -> impl Init<Self::Command, Self::InitError> {
> }
> }
>
> -/// The reply from the GSP to the [`GetGspInfo`] command.
> +/// The reply from the GSP to the [`GetGspStaticInfo`] command.
> pub(crate) struct GetGspStaticInfoReply {
> gpu_name: [u8; 64],
> + /// Usable FB (VRAM) region for driver memory allocation.
> + #[expect(dead_code)]
> + pub(crate) usable_fb_region: Range<u64>,
Let's print the region when creating the GPU (using `dev_info` or
`dev_dbg`) - this can be useful to the user, and lets us remove this
`dead_code`.
^ permalink raw reply
* Re: [PATCH] docs: proc: document ProtectionKey in smaps
From: Kevin Brodsky @ 2026-04-08 7:15 UTC (permalink / raw)
To: David Hildenbrand (Arm), Randy Dunlap, Dave Hansen, linux-doc
Cc: linux-kernel, Yury Khrustalev, Jonathan Corbet, Shuah Khan,
Dave Hansen, Andrew Morton, Lorenzo Stoakes, Vlastimil Babka,
Mark Rutland, linux-fsdevel, linux-mm
In-Reply-To: <8a5e4afd-cd0a-400a-8624-79c1dc9e3ff3@kernel.org>
On 08/04/2026 09:05, David Hildenbrand (Arm) wrote:
>>>> To me "system" is a bit ambiguous here but _can_ refer to the whole
>>>> hardware/software system as a whole. To avoid redundancy, I'd say either:
>>>>
>>>> If both the kernel and the processor support protection keys...
>>>>
>>>> or
>>>>
>>>> If the system supports protection keys...
>>> I see your point. By "system" I essentially mean the hardware (the SoC).
>>> In general I would tend to avoid "processor" because not all CPUs in a
>>> system necessarily have the same features, and some features require
>>> hardware support beyond the CPU itself. Terminology is hard...
>>>
>>> Happy to replace "system" with "hardware" if that's clearer 🙂
>> I think that "system" is too nebulous there, so I would prefer to see
>> "hardware" instead.
> What if you're running in a VM where the feature is hidden ... ?
Of course that's also possible, "hardware" has to be interpreted in the
context of virtualisation... But granted it is possible to hide features
even on the host with the right kernel parameter, on arm64 at least.
"If the kernel supports protection keys (pkeys) and the hardware feature
is detected"? Still vague but a little more accurate.
- Kevin
^ permalink raw reply
* Re: [PATCH] docs: proc: document ProtectionKey in smaps
From: Kevin Brodsky @ 2026-04-08 7:06 UTC (permalink / raw)
To: Randy Dunlap, Dave Hansen, linux-doc
Cc: linux-kernel, Yury Khrustalev, Jonathan Corbet, Shuah Khan,
Dave Hansen, Andrew Morton, Lorenzo Stoakes, Vlastimil Babka,
David Hildenbrand, Mark Rutland, linux-fsdevel, linux-mm
In-Reply-To: <18e2042c-d414-40fb-8819-5e930d5b1584@infradead.org>
On 07/04/2026 20:58, Randy Dunlap wrote:
>>> To me "system" is a bit ambiguous here but _can_ refer to the whole
>>> hardware/software system as a whole. To avoid redundancy, I'd say either:
>>>
>>> If both the kernel and the processor support protection keys...
>>>
>>> or
>>>
>>> If the system supports protection keys...
>> I see your point. By "system" I essentially mean the hardware (the SoC).
>> In general I would tend to avoid "processor" because not all CPUs in a
>> system necessarily have the same features, and some features require
>> hardware support beyond the CPU itself. Terminology is hard...
>>
>> Happy to replace "system" with "hardware" if that's clearer 🙂
> I think that "system" is too nebulous there, so I would prefer to see
> "hardware" instead.
Ack, will send a v2.
- Kevin
^ permalink raw reply
* Re: [PATCH] docs: proc: document ProtectionKey in smaps
From: David Hildenbrand (Arm) @ 2026-04-08 7:05 UTC (permalink / raw)
To: Randy Dunlap, Kevin Brodsky, Dave Hansen, linux-doc
Cc: linux-kernel, Yury Khrustalev, Jonathan Corbet, Shuah Khan,
Dave Hansen, Andrew Morton, Lorenzo Stoakes, Vlastimil Babka,
Mark Rutland, linux-fsdevel, linux-mm
In-Reply-To: <18e2042c-d414-40fb-8819-5e930d5b1584@infradead.org>
On 4/7/26 20:58, Randy Dunlap wrote:
>
>
> On 4/7/26 8:12 AM, Kevin Brodsky wrote:
>> On 07/04/2026 16:42, Dave Hansen wrote:
>>> I think you're trying to get across the point here that the kernel needs
>>> to know about protection keys, have it enabled, and be running on a CPU
>>> with pkey support.
>>
>> Indeed.
>>
>>> To me "system" is a bit ambiguous here but _can_ refer to the whole
>>> hardware/software system as a whole. To avoid redundancy, I'd say either:
>>>
>>> If both the kernel and the processor support protection keys...
>>>
>>> or
>>>
>>> If the system supports protection keys...
>>
>> I see your point. By "system" I essentially mean the hardware (the SoC).
>> In general I would tend to avoid "processor" because not all CPUs in a
>> system necessarily have the same features, and some features require
>> hardware support beyond the CPU itself. Terminology is hard...
>>
>> Happy to replace "system" with "hardware" if that's clearer :)
>
> I think that "system" is too nebulous there, so I would prefer to see
> "hardware" instead.
What if you're running in a VM where the feature is hidden ... ?
--
Cheers,
David
^ permalink raw reply
* Re: [PATCH v10 12/21] gpu: nova-core: mm: Add unified page table entry wrapper enums
From: Alexandre Courbot @ 2026-04-08 7:03 UTC (permalink / raw)
To: Joel Fernandes
Cc: Eliot Courtney, linux-kernel, Miguel Ojeda, Boqun Feng, Gary Guo,
Bjorn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Dave Airlie, Daniel Almeida,
Koen Koning, dri-devel, rust-for-linux, Nikola Djukic,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Jonathan Corbet, Alex Deucher, Christian Koenig,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
Huang Rui, Matthew Auld, Matthew Brost, Lucas De Marchi,
Thomas Hellstrom, Helge Deller, Alex Gaynor, Boqun Feng,
John Hubbard, Alistair Popple, Timur Tabi, Edwin Peer,
Andrea Righi, Andy Ritger, Zhi Wang, Balbir Singh,
Philipp Stanner, Elle Rhumsaa, alexeyi, joel, linux-doc, amd-gfx,
intel-gfx, intel-xe, linux-fbdev
In-Reply-To: <537a8c5a-3885-4c47-99f6-963b48ddf87d@nvidia.com>
On Tue Apr 7, 2026 at 10:59 PM JST, Joel Fernandes wrote:
> Hi Eliot,
>
> On 4/7/2026 9:42 AM, Eliot Courtney wrote:
>> On Tue Apr 7, 2026 at 6:55 AM JST, Joel Fernandes wrote:
>>>>> + /// Compute upper bound on page table pages needed for `num_virt_pages`.
>>>>> + ///
>>>>> + /// Walks from PTE level up through PDE levels, accumulating the tree.
>>>>> + pub(crate) fn pt_pages_upper_bound(&self, num_virt_pages: usize) -> usize {
>>>>> + let mut total = 0;
>>>>> +
>>>>> + // PTE pages at the leaf level.
>>>>> + let pte_epp = self.entries_per_page(self.pte_level());
>>>>> + let mut pages_at_level = num_virt_pages.div_ceil(pte_epp);
>>>>> + total += pages_at_level;
>>>>> +
>>>>> + // Walk PDE levels bottom-up (reverse of pde_levels()).
>>>>> + for &level in self.pde_levels().iter().rev() {
>>>>> + let epp = self.entries_per_page(level);
>>>>> +
>>>>> + // How many pages at this level do we need to point to
>>>>> + // the previous pages_at_level?
>>>>> + pages_at_level = pages_at_level.div_ceil(epp);
>>>>> + total += pages_at_level;
>>>>> + }
>>>>> +
>>>>> + total
>>>>> + }
>>>>> +}
>>>>> +
>>>>
>>>> We have a lot of matches on the MMU version here (and below in Pte, Pde,
>>>> DualPde). What about making MmuVersion into a trait (e.g. Mmu) with
>>>> associated types for Pte, Pde, DualPde which can implement traits
>>>> defining their common operations too?
>>>
>>> I coded this up and it did not look pretty, there's not much LOC savings and the
>>> code becomes harder to read because of parametrization of several functions. Also:
>>
>> Thanks for looking into it. Sorry to be a bother, but would you have a
>> branch around with the code? I'm curious what didn't look good about it.
>
> Sorry but I already mentioned that above, the parameterizing of dozens of
> function call sites, 3-4 new traits (because each struct like
> Pte/Pde/DualPde etc each need their own trait which different MMU versions
> implement) etc. The code because hard to read and readability is the top
> critical criteria for me - I am personally strictly against "Lets use shiny
> features in language at the cost of making code unreadable". Because that
> translates into bugs and nightmare for maintainability.
After a quick look I'd say that having a trait here would actually be
*good* for correctness and maintainability.
The current design implies that every operation on a page table (most
likely using the walker) goes through a branching point. Just looking at
`PtWalk::read_pte_at_level`, there are already at least 6
`if version == 2 { } else { }` branches that all resolve to the same
result. Include walking down the PDEs and you have at least a dozen of
these just to resolve a virtual address. I know CPUs are fast, but this
is still wasted cycles for no good reason.
If you use a trait here, and make `PtWalk` generic against it, you can
optimize this away. We had a similar situation when we introduced Turing
support and the v2 ucode header, and tried both approaches: the
trait-based one was slightly shorter, and arguably more readable.
But the main argument to use a trait here IMO is that it enables
associated types and constants. That's particularly critical since some
equivalent fields have different lengths between v2 and v3. An
associated `Bounded` type for these would force the caller to validate
the length of these fields before calling a non-fallible operation,
which is exactly the level of caution that we want when dealing with
page tables.
In order to fully benefit from it, we will need the bitfield macro from
the `kernel` crate so the PDE/PTE fields can be `Bounded`, I will try to
make it available quickly in a patch that you can depend on.
But long story short, and although I need to dive deeper into the code,
this looks like a good candidate for using a trait and associated types.
^ permalink raw reply
* [PATCH 0/4] docs/zh_CN: update rust/ subsystem translations
From: Ben Guo @ 2026-04-08 5:05 UTC (permalink / raw)
To: Alex Shi, Yanteng Si, Dongliang Mu, Jonathan Corbet
Cc: linux-doc, linux-kernel, rust-for-linux, Ben Guo
Update Chinese translations for the Rust subsystem documentation,
syncing with the latest upstream changes.
- arch-support.rst: add ARM (ARMv7) support, update RISC-V and UM notes
- coding-guidelines.rst: add imports formatting, private item docs,
C FFI types, and Lints sections
- quick-start.rst: add distro-specific install instructions, update
rustc/bindgen sections, remove cargo section
- index.rst: remove experimental notice and genindex
Ben Guo (4):
docs/zh_CN: update rust/arch-support.rst translation
docs/zh_CN: update rust/coding-guidelines.rst translation
docs/zh_CN: update rust/quick-start.rst translation
docs/zh_CN: update rust/index.rst translation
.../translations/zh_CN/rust/arch-support.rst | 9 +-
.../zh_CN/rust/coding-guidelines.rst | 262 +++++++++++++++++-
.../translations/zh_CN/rust/index.rst | 17 --
.../translations/zh_CN/rust/quick-start.rst | 190 ++++++++++---
4 files changed, 401 insertions(+), 77 deletions(-)
--
2.53.0
^ permalink raw reply
* [PATCH 4/4] docs/zh_CN: update rust/index.rst translation
From: Ben Guo @ 2026-04-08 5:05 UTC (permalink / raw)
To: Alex Shi, Yanteng Si, Dongliang Mu, Jonathan Corbet
Cc: linux-doc, linux-kernel, rust-for-linux, Ben Guo
In-Reply-To: <cover.1775619061.git.ben.guo@openatom.club>
Update the translation of .../rust/index.rst into Chinese.
Update the translation through commit a592a36e4937
("Documentation: use a source-read extension for the index link boilerplate")
Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
Signed-off-by: Ben Guo <ben.guo@openatom.club>
---
Documentation/translations/zh_CN/rust/index.rst | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/Documentation/translations/zh_CN/rust/index.rst b/Documentation/translations/zh_CN/rust/index.rst
index 5347d472958..138e057bee4 100644
--- a/Documentation/translations/zh_CN/rust/index.rst
+++ b/Documentation/translations/zh_CN/rust/index.rst
@@ -12,16 +12,6 @@ Rust
与内核中的Rust有关的文档。若要开始在内核中使用Rust，请阅读 quick-start.rst 指南。
-Rust 实验
----------
-Rust 支持在 v6.1 版本中合并到主线，以帮助确定 Rust 作为一种语言是否适合内核，
-即是否值得进行权衡。
-
-目前，Rust 支持主要面向对 Rust 支持感兴趣的内核开发人员和维护者，
-以便他们可以开始处理抽象和驱动程序，并帮助开发基础设施和工具。
-
-如果您是终端用户，请注意，目前没有适合或旨在生产使用的内置驱动程序或模块，
-并且 Rust 支持仍处于开发/实验阶段，尤其是对于特定内核配置。
代码文档
--------
@@ -50,10 +40,3 @@ Rust 支持在 v6.1 版本中合并到主线，以帮助确定 Rust 作为一种
testing
你还可以在 :doc:`../../../process/kernel-docs` 中找到 Rust 的学习材料。
-
-.. only:: subproject and html
-
- Indices
- =======
-
- * :ref:`genindex`
--
2.53.0
^ permalink raw reply related
* [PATCH 2/4] docs/zh_CN: update rust/coding-guidelines.rst translation
From: Ben Guo @ 2026-04-08 5:05 UTC (permalink / raw)
To: Alex Shi, Yanteng Si, Dongliang Mu, Jonathan Corbet
Cc: linux-doc, linux-kernel, rust-for-linux, Ben Guo
In-Reply-To: <cover.1775619061.git.ben.guo@openatom.club>
Update the translation of .../rust/coding-guidelines.rst into Chinese.
Update the translation through commit 4a9cb2eecc78
("docs: rust: add section on imports formatting")
Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
Signed-off-by: Ben Guo <ben.guo@openatom.club>
---
.../zh_CN/rust/coding-guidelines.rst | 262 +++++++++++++++++-
1 file changed, 248 insertions(+), 14 deletions(-)
diff --git a/Documentation/translations/zh_CN/rust/coding-guidelines.rst b/Documentation/translations/zh_CN/rust/coding-guidelines.rst
index 419143b938e..54b902322db 100644
--- a/Documentation/translations/zh_CN/rust/coding-guidelines.rst
+++ b/Documentation/translations/zh_CN/rust/coding-guidelines.rst
@@ -37,6 +37,73 @@
像内核其他部分的 ``clang-format`` 一样， ``rustfmt`` 在单个文件上工作，并且不需要
内核配置。有时，它甚至可以与破碎的代码一起工作。
+导入
+~~~~
+
+``rustfmt`` 默认会以一种在合并和变基时容易产生冲突的方式格式化导入，因为在某些情况下
+它会将多个条目合并到同一行。例如：
+
+.. code-block:: rust
+
+ // Do not use this style.
+ use crate::{
+ example1,
+ example2::{example3, example4, example5},
+ example6, example7,
+ example8::example9,
+ };
+
+相反，内核使用如下所示的垂直布局：
+
+.. code-block:: rust
+
+ use crate::{
+ example1,
+ example2::{
+ example3,
+ example4,
+ example5, //
+ },
+ example6,
+ example7,
+ example8::example9, //
+ };
+
+也就是说，每个条目占一行，只要列表中有多个条目就使用花括号。
+
+末尾的空注释可以保留这种格式。不仅如此， ``rustfmt`` 在添加空注释后实际上会将导入重
+新格式化为垂直布局。也就是说，可以通过对如下输入运行 ``rustfmt`` 来轻松地将原始示例
+重新格式化为预期的风格：
+
+.. code-block:: rust
+
+ // Do not use this style.
+ use crate::{
+ example1,
+ example2::{example3, example4, example5, //
+ },
+ example6, example7,
+ example8::example9, //
+ };
+
+末尾的空注释适用于嵌套导入（如上所示）以及单条目导入——这有助于最小化补丁系列中的差
+异：
+
+.. code-block:: rust
+
+ use crate::{
+ example1, //
+ };
+
+末尾的空注释可以放在花括号内的任何一行中，但建议放在最后一个条目上，因为这让人联想到其
+他格式化工具中的末尾逗号。有时在补丁系列中由于列表的变更，避免多次移动注释可能更简单。
+
+在某些情况下可能需要例外处理，即以上都不是硬性规则。也有一些代码尚未迁移到这种风格，但
+请不要引入其他风格的代码。
+
+最终目标是让 ``rustfmt`` 在稳定版本中自动支持这种格式化风格（或类似的风格），而无需
+末尾的空注释。因此，在某个时候，目标是移除这些注释。
+
注释
----
@@ -77,6 +144,16 @@
// ...
}
+这适用于公共和私有项目。这增加了与公共项目的一致性，允许在更改可见性时减少涉及的更改，
+并允许我们将来也为私有项目生成文档。换句话说，如果为私有项目编写了文档，那么仍然应该使
+用 ``///`` 。例如：
+
+.. code-block:: rust
+
+ /// My private function.
+ // TODO: ...
+ fn f() {}
+
一种特殊的注释是 ``// SAFETY:`` 注释。这些注释必须出现在每个 ``unsafe`` 块之前，它们
解释了为什么该块内的代码是正确/健全的，即为什么它在任何情况下都不会触发未定义行为，例如:
@@ -131,27 +208,27 @@ https://commonmark.org/help/
这个例子展示了一些 ``rustdoc`` 的特性和内核中遵循的一些惯例:
- - 第一段必须是一个简单的句子，简要地描述被记录的项目的作用。进一步的解释必须放在额
- 外的段落中。
+- 第一段必须是一个简单的句子，简要地描述被记录的项目的作用。进一步的解释必须放在额
+ 外的段落中。
- - 不安全的函数必须在 ``# Safety`` 部分记录其安全前提条件。
+- 不安全的函数必须在 ``# Safety`` 部分记录其安全前提条件。
- - 虽然这里没有显示，但如果一个函数可能会恐慌，那么必须在 ``# Panics`` 部分描述发
- 生这种情况的条件。
+- 虽然这里没有显示，但如果一个函数可能会恐慌，那么必须在 ``# Panics`` 部分描述发
+ 生这种情况的条件。
- 请注意，恐慌应该是非常少见的，只有在有充分理由的情况下才会使用。几乎在所有的情况下，
- 都应该使用一个可失败的方法，通常是返回一个 ``Result``。
+ 请注意，恐慌应该是非常少见的，只有在有充分理由的情况下才会使用。几乎在所有的情况下，
+ 都应该使用一个可失败的方法，通常是返回一个 ``Result``。
- - 如果提供使用实例对读者有帮助的话，必须写在一个叫做``# Examples``的部分。
+- 如果提供使用实例对读者有帮助的话，必须写在一个叫做``# Examples``的部分。
- - Rust项目（函数、类型、常量……）必须有适当的链接(``rustdoc`` 会自动创建一个
- 链接)。
+- Rust项目（函数、类型、常量……）必须有适当的链接(``rustdoc`` 会自动创建一个
+ 链接)。
- - 任何 ``unsafe`` 的代码块都必须在前面加上一个 ``// SAFETY:`` 的注释，描述里面
- 的代码为什么是正确的。
+- 任何 ``unsafe`` 的代码块都必须在前面加上一个 ``// SAFETY:`` 的注释，描述里面
+ 的代码为什么是正确的。
- 虽然有时原因可能看起来微不足道，但写这些注释不仅是记录已经考虑到的问题的好方法，
- 最重要的是，它提供了一种知道没有额外隐含约束的方法。
+ 虽然有时原因可能看起来微不足道，但写这些注释不仅是记录已经考虑到的问题的好方法，
+ 最重要的是，它提供了一种知道没有额外隐含约束的方法。
要了解更多关于如何编写Rust和拓展功能的文档，请看看 ``rustdoc`` 这本书，网址是:
@@ -170,6 +247,22 @@ https://commonmark.org/help/
/// [`struct mutex`]: srctree/include/linux/mutex.h
+C FFI 类型
+----------
+
+Rust 内核代码使用类型别名（如 ``c_int``）来引用 C 类型（如 ``int``），这些别名可
+以直接从 ``kernel`` 预导入（prelude）中获取。请不要使用 ``core::ffi`` 中的别
+名——它们可能无法映射到正确的类型。
+
+这些别名通常应该直接通过其标识符引用，即作为单段路径。例如：
+
+.. code-block:: rust
+
+ fn f(p: *const c_char) -> c_int {
+ // ...
+ }
+
+
命名
----
@@ -202,3 +295,144 @@ Rust内核代码遵循通常的Rust命名空间:
也就是说， ``GPIO_LINE_DIRECTION_IN`` 的等价物将被称为 ``gpio::LineDirection::In`` 。
特别是，它不应该被命名为 ``gpio::gpio_line_direction::GPIO_LINE_DIRECTION_IN`` 。
+
+
+代码检查提示（Lints）
+---------------------
+
+在 Rust 中，可以在局部 ``allow`` 特定的警告（诊断信息、代码检查提示（lint）），
+使编译器忽略给定函数、模块、代码块等中给定警告的实例。
+
+这类似于 C 中的 ``#pragma GCC diagnostic push`` + ``ignored`` + ``pop``
+[#]_：
+
+.. code-block:: c
+
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wunused-function"
+ static void f(void) {}
+ #pragma GCC diagnostic pop
+
+.. [#] 在这个特定情况下，可以使用内核的 ``__{always,maybe}_unused`` 属性
+ （C23 的 ``[[maybe_unused]]``）；然而，此示例旨在反映下文讨论的 Rust 中
+ 的等效代码检查提示。
+
+但要简洁得多：
+
+.. code-block:: rust
+
+ #[allow(dead_code)]
+ fn f() {}
+
+凭借这一点，可以更方便地默认启用更多诊断（即在 ``W=`` 级别之外）。特别是那些可能有
+一些误报但在其他方面非常有用的诊断，保持启用可以捕获潜在的错误。
+
+在此基础上，Rust 提供了 ``expect`` 属性，更进一步。如果警告没有产生，它会让编译器
+发出警告。例如，以下代码将确保当 ``f()`` 在某处被调用时，我们必须移除该属性：
+
+.. code-block:: rust
+
+ #[expect(dead_code)]
+ fn f() {}
+
+如果我们不这样做，编译器会发出警告::
+
+ warning: this lint expectation is unfulfilled
+ --> x.rs:3:10
+ |
+ 3 | #[expect(dead_code)]
+ | ^^^^^^^^^
+ |
+ = note: `#[warn(unfulfilled_lint_expectations)]` on by default
+
+这意味着 ``expect`` 不会在不需要时被遗忘，这可能发生在以下几种情况中：
+
+- 开发过程中添加的临时属性。
+
+- 编译器、Clippy 或自定义工具中代码检查提示的改进可能消除误报。
+
+- 当代码检查提示不再需要时，因为预期它会在某个时候被移除，例如上面的
+ ``dead_code`` 示例。
+
+这也增加了剩余 ``allow`` 的可见性，并减少了误用的可能性。
+
+因此，优先使用 ``expect`` 而不是 ``allow``，除非：
+
+- 条件编译在某些情况下触发警告，在其他情况下不触发。
+
+ 如果与总的相比，只有少数情况触发（或不触发）警告，那么可以考虑使用条件
+ ``expect``（即 ``cfg_attr(..., expect(...))``）。否则，使用 ``allow`` 可
+ 能更简单。
+
+- 在宏内部，不同的调用可能会创建在某些情况下触发警告而在其他情况下不触发的展开代码。
+
+- 当代码可能在某些架构上触发警告但在其他架构上不触发时，例如到 C FFI 类型的 ``as``
+ 转换。
+
+作为一个更详细的示例，考虑以下程序：
+
+.. code-block:: rust
+
+ fn g() {}
+
+ fn main() {
+ #[cfg(CONFIG_X)]
+ g();
+ }
+
+这里，如果 ``CONFIG_X`` 未设置，函数 ``g()`` 是死代码。我们可以在这里使用
+``expect`` 吗？
+
+.. code-block:: rust
+
+ #[expect(dead_code)]
+ fn g() {}
+
+ fn main() {
+ #[cfg(CONFIG_X)]
+ g();
+ }
+
+如果 ``CONFIG_X`` 被设置，这将产生代码检查提示，因为在该配置中它不是死代码。因
+此，在这种情况下，我们不能直接使用 ``expect``。
+
+一个简单的可能性是使用 ``allow``：
+
+.. code-block:: rust
+
+ #[allow(dead_code)]
+ fn g() {}
+
+ fn main() {
+ #[cfg(CONFIG_X)]
+ g();
+ }
+
+另一种方法是使用条件 ``expect``：
+
+.. code-block:: rust
+
+ #[cfg_attr(not(CONFIG_X), expect(dead_code))]
+ fn g() {}
+
+ fn main() {
+ #[cfg(CONFIG_X)]
+ g();
+ }
+
+这将确保如果有人在某处引入了对 ``g()`` 的另一个调用（例如无条件的），那么将会被发现
+它不再是死代码。然而， ``cfg_attr`` 比简单的 ``allow`` 更复杂。
+
+因此，当涉及多个配置或者代码检查提示可能由于非局部更改（如 ``dead_code``）而触发
+时，使用条件 ``expect`` 可能不值得。
+
+有关 Rust 中诊断的更多信息，请参阅：
+
+ https://doc.rust-lang.org/stable/reference/attributes/diagnostics.html
+
+错误处理
+--------
+
+有关 Rust for Linux 特定错误处理的背景和指南，请参阅：
+
+ https://rust.docs.kernel.org/kernel/error/type.Result.html#error-codes-in-c-and-rust
--
2.53.0
^ permalink raw reply related
* [PATCH 3/4] docs/zh_CN: update rust/quick-start.rst translation
From: Ben Guo @ 2026-04-08 5:05 UTC (permalink / raw)
To: Alex Shi, Yanteng Si, Dongliang Mu, Jonathan Corbet
Cc: linux-doc, linux-kernel, rust-for-linux, Ben Guo
In-Reply-To: <cover.1775619061.git.ben.guo@openatom.club>
Update the translation of .../rust/quick-start.rst into Chinese.
Update the translation through commit 5935461b4584
("docs: rust: quick-start: add Debian 13 (Trixie)")
Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
Signed-off-by: Ben Guo <ben.guo@openatom.club>
---
.../translations/zh_CN/rust/quick-start.rst | 190 ++++++++++++++----
1 file changed, 148 insertions(+), 42 deletions(-)
diff --git a/Documentation/translations/zh_CN/rust/quick-start.rst b/Documentation/translations/zh_CN/rust/quick-start.rst
index 8616556ae4d..5f0ece6411f 100644
--- a/Documentation/translations/zh_CN/rust/quick-start.rst
+++ b/Documentation/translations/zh_CN/rust/quick-start.rst
@@ -13,16 +13,138 @@
本文介绍了如何开始使用Rust进行内核开发。
+安装内核开发所需的 Rust 工具链有几种方式。一种简单的方式是使用 Linux 发行版的软件包
+（如果它们合适的话）——下面的第一节解释了这种方法。这种方法的一个优势是，通常发行版会
+匹配 Rust 和 Clang 所使用的 LLVM。
+
+另一种方式是使用 `kernel.org <https://kernel.org/pub/tools/llvm/rust/>`_ 上提
+供的预构建稳定版本的 LLVM+Rust。这些与 :ref:`获取 LLVM <zh_cn_getting_llvm>` 中的精
+简快速 LLVM 工具链相同，并添加了 Rust for Linux 支持的 Rust 版本。提供了两套工具
+链："最新 LLVM" 和 "匹配 LLVM"（请参阅链接了解更多信息）。
+
+或者，接下来的两个 "依赖" 章节将解释每个组件以及如何通过 ``rustup``、Rust 的独立
+安装程序或从源码构建来安装它们。
+
+本文档的其余部分解释了有关如何入门的其他方面。
+
+
+发行版
+------
+
+Arch Linux
+**********
+
+Arch Linux 提供较新的 Rust 版本，因此通常开箱即用，例如::
+
+ pacman -S rust rust-src rust-bindgen
+
+
+Debian
+******
+
+Debian 13（Trixie）以及 Testing 和 Debian Unstable（Sid）提供较新的 Rust 版
+本，因此通常开箱即用，例如::
+
+ apt install rustc rust-src bindgen rustfmt rust-clippy
+
+
+Fedora Linux
+************
+
+Fedora Linux 提供较新的 Rust 版本，因此通常开箱即用，例如::
+
+ dnf install rust rust-src bindgen-cli rustfmt clippy
+
+
+Gentoo Linux
+************
+
+Gentoo Linux（尤其是 testing 分支）提供较新的 Rust 版本，因此通常开箱即用，
+例如::
+
+ USE='rust-src rustfmt clippy' emerge dev-lang/rust dev-util/bindgen
+
+可能需要设置 ``LIBCLANG_PATH``。
+
+
+Nix
+***
+
+Nix（unstable 频道）提供较新的 Rust 版本，因此通常开箱即用，例如::
+
+ { pkgs ? import <nixpkgs> {} }:
+ pkgs.mkShell {
+ nativeBuildInputs = with pkgs; [ rustc rust-bindgen rustfmt clippy ];
+ RUST_LIB_SRC = "${pkgs.rust.packages.stable.rustPlatform.rustLibSrc}";
+ }
+
+
+openSUSE
+********
+
+openSUSE Slowroll 和 openSUSE Tumbleweed 提供较新的 Rust 版本，因此通常开箱
+即用，例如::
+
+ zypper install rust rust1.79-src rust-bindgen clang
+
+
+Ubuntu
+******
+
+25.04
+~~~~~
+
+最新的 Ubuntu 版本提供较新的 Rust 版本，因此通常开箱即用，例如::
+
+ apt install rustc rust-src bindgen rustfmt rust-clippy
+
+此外，需要设置 ``RUST_LIB_SRC``，例如::
+
+ RUST_LIB_SRC=/usr/src/rustc-$(rustc --version | cut -d' ' -f2)/library
+
+为方便起见，可以将 ``RUST_LIB_SRC`` 导出到全局环境中。
+
+
+24.04 LTS 及更早版本
+~~~~~~~~~~~~~~~~~~~~
+
+虽然 Ubuntu 24.04 LTS 及更早版本仍然提供较新的 Rust 版本，但它们需要一些额外的配
+置，使用带版本号的软件包，例如::
+
+ apt install rustc-1.80 rust-1.80-src bindgen-0.65 rustfmt-1.80 \
+ rust-1.80-clippy
+ ln -s /usr/lib/rust-1.80/bin/rustfmt /usr/bin/rustfmt-1.80
+ ln -s /usr/lib/rust-1.80/bin/clippy-driver /usr/bin/clippy-driver-1.80
+
+这些软件包都不会将其工具设置为默认值；因此应该显式指定它们，例如::
+
+ make LLVM=1 RUSTC=rustc-1.80 RUSTDOC=rustdoc-1.80 RUSTFMT=rustfmt-1.80 \
+ CLIPPY_DRIVER=clippy-driver-1.80 BINDGEN=bindgen-0.65
+
+或者，修改 ``PATH`` 变量将 Rust 1.80 的二进制文件放在前面，并将 ``bindgen`` 设
+置为默认值，例如::
+
+ PATH=/usr/lib/rust-1.80/bin:$PATH
+ update-alternatives --install /usr/bin/bindgen bindgen \
+ /usr/bin/bindgen-0.65 100
+ update-alternatives --set bindgen /usr/bin/bindgen-0.65
+
+使用带版本号的软件包时需要设置 ``RUST_LIB_SRC``，例如::
+
+ RUST_LIB_SRC=/usr/src/rustc-$(rustc-1.80 --version | cut -d' ' -f2)/library
+
+为方便起见，可以将 ``RUST_LIB_SRC`` 导出到全局环境中。
+
+此外， ``bindgen-0.65`` 在较新的版本（24.04 LTS 和 24.10）中可用，但在更早的版
+本（20.04 LTS 和 22.04 LTS）中可能不可用，因此可能需要手动构建 ``bindgen``
+（请参见下文）。
+
构建依赖
--------
本节描述了如何获取构建所需的工具。
-其中一些依赖也许可以从Linux发行版中获得，包名可能是 ``rustc`` , ``rust-src`` ,
-``rust-bindgen`` 等。然而，在写这篇文章的时候，它们很可能还不够新，除非发行版跟踪最
-新的版本。
-
为了方便检查是否满足要求，可以使用以下目标::
make LLVM=1 rustavailable
@@ -34,15 +156,14 @@
rustc
*****
-需要一个特定版本的Rust编译器。较新的版本可能会也可能不会工作，因为就目前而言，内核依赖
-于一些不稳定的Rust特性。
+需要一个较新版本的Rust编译器。
如果使用的是 ``rustup`` ，请进入内核编译目录（或者用 ``--path=<build-dir>`` 参数
-来 ``设置`` sub-command)并运行::
+来 ``设置`` sub-command)，例如运行::
- rustup override set $(scripts/min-tool-version.sh rustc)
+ rustup override set stable
-+这将配置你的工作目录使用正确版本的 ``rustc``，而不影响你的默认工具链。
+这将配置你的工作目录使用给定版本的 ``rustc``，而不影响你的默认工具链。
请注意覆盖应用当前的工作目录（和它的子目录）。
@@ -54,7 +175,7 @@ rustc
Rust标准库源代码
****************
-Rust标准库的源代码是必需的，因为构建系统会交叉编译 ``core`` 和 ``alloc`` 。
+Rust标准库的源代码是必需的，因为构建系统会交叉编译 ``core`` 。
如果正在使用 ``rustup`` ，请运行::
@@ -64,10 +185,10 @@ Rust标准库的源代码是必需的，因为构建系统会交叉编译 ``core
否则，如果使用独立的安装程序，可以将Rust源码树下载到安装工具链的文件夹中::
- curl -L "https://static.rust-lang.org/dist/rust-src-$(scripts/min-tool-version.sh rustc).tar.gz" |
- tar -xzf - -C "$(rustc --print sysroot)/lib" \
- "rust-src-$(scripts/min-tool-version.sh rustc)/rust-src/lib/" \
- --strip-components=3
+ curl -L "https://static.rust-lang.org/dist/rust-src-$(rustc --version | cut -d' ' -f2).tar.gz" |
+ tar -xzf - -C "$(rustc --print sysroot)/lib" \
+ "rust-src-$(rustc --version | cut -d' ' -f2)/rust-src/lib/" \
+ --strip-components=3
在这种情况下，以后升级Rust编译器版本需要手动更新这个源代码树（这可以通过移除
``$(rustc --print sysroot)/lib/rustlib/src/rust`` ，然后重新执行上
@@ -97,24 +218,21 @@ Linux发行版中可能会有合适的包，所以最好先检查一下。
bindgen
*******
-内核的C端绑定是在构建时使用 ``bindgen`` 工具生成的。这需要特定的版本。
-
-通过以下方式安装它（注意，这将从源码下载并构建该工具）::
-
- cargo install --locked --version $(scripts/min-tool-version.sh bindgen) bindgen-cli
+内核的C端绑定是在构建时使用 ``bindgen`` 工具生成的。
-``bindgen`` 需要找到合适的 ``libclang`` 才能工作。如果没有找到（或者找到的
-``libclang`` 与应该使用的 ``libclang`` 不同），则可以使用 ``clang-sys``
-理解的环境变量（Rust绑定创建的 ``bindgen`` 用来访问 ``libclang``）:
+例如，通过以下方式安装它（注意，这将从源码下载并构建该工具）::
+ cargo install --locked bindgen-cli
-* ``LLVM_CONFIG_PATH`` 可以指向一个 ``llvm-config`` 可执行文件。
+``bindgen`` 使用 ``clang-sys`` crate 来查找合适的 ``libclang`` （可以静态链
+接、动态链接或在运行时加载）。默认情况下，上面的 ``cargo`` 命令会生成一个在运行时
+加载 ``libclang`` 的 ``bindgen`` 二进制文件。如果没有找到（或者应该使用与找到的
+不同的 ``libclang``），可以调整该过程，例如使用 ``LIBCLANG_PATH`` 环境变量。详
+情请参阅 ``clang-sys`` 的文档：
-* 或者 ``LIBCLANG_PATH`` 可以指向 ``libclang`` 共享库或包含它的目录。
+ https://github.com/KyleMayes/clang-sys#linking
-* 或者 ``CLANG_PATH`` 可以指向 ``clang`` 可执行文件。
-
-详情请参阅 ``clang-sys`` 的文档:
+ https://github.com/KyleMayes/clang-sys#environment-variables
开发依赖
@@ -151,18 +269,6 @@ clippy
独立的安装程序也带有 ``clippy`` 。
-cargo
-*****
-
-``cargo`` 是Rust的本地构建系统。目前需要它来运行测试，因为它被用来构建一个自定义的标准
-库，其中包含了内核中自定义 ``alloc`` 所提供的设施。测试可以使用 ``rusttest`` Make 目标
-来运行。
-
-如果使用的是 ``rustup`` ，所有的配置文件都已经安装了该工具，因此不需要再做什么。
-
-独立的安装程序也带有 ``cargo`` 。
-
-
rustdoc
*******
@@ -223,7 +329,7 @@ Rust支持（CONFIG_RUST）需要在 ``General setup`` 菜单中启用。在其
如果使用的是GDB/Binutils，而Rust符号没有被demangled，原因是工具链还不支持Rust的新v0
mangling方案。有几个办法可以解决：
- - 安装一个较新的版本（GDB >= 10.2, Binutils >= 2.36）。
+- 安装一个较新的版本（GDB >= 10.2, Binutils >= 2.36）。
- - 一些版本的GDB（例如vanilla GDB 10.1）能够使用嵌入在调试信息(``CONFIG_DEBUG_INFO``)
- 中的pre-demangled的名字。
+- 一些版本的GDB（例如vanilla GDB 10.1）能够使用嵌入在调试信息(``CONFIG_DEBUG_INFO``)
+ 中的pre-demangled的名字。
--
2.53.0
^ permalink raw reply related
* [PATCH 1/4] docs/zh_CN: update rust/arch-support.rst translation
From: Ben Guo @ 2026-04-08 5:05 UTC (permalink / raw)
To: Alex Shi, Yanteng Si, Dongliang Mu, Jonathan Corbet
Cc: linux-doc, linux-kernel, rust-for-linux, Ben Guo
In-Reply-To: <cover.1775619061.git.ben.guo@openatom.club>
Update the translation of .../rust/arch-support.rst into Chinese.
Update the translation through commit ccb8ce526807
("ARM: 9441/1: rust: Enable Rust support for ARMv7")
Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
Signed-off-by: Ben Guo <ben.guo@openatom.club>
---
Documentation/translations/zh_CN/rust/arch-support.rst | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/translations/zh_CN/rust/arch-support.rst b/Documentation/translations/zh_CN/rust/arch-support.rst
index abd708d48f8..f5ae44588a5 100644
--- a/Documentation/translations/zh_CN/rust/arch-support.rst
+++ b/Documentation/translations/zh_CN/rust/arch-support.rst
@@ -19,9 +19,10 @@
============= ================ ==============================================
架构 支持水平 限制因素
============= ================ ==============================================
-``arm64`` Maintained 只有小端序
+``arm`` Maintained 仅 ARMv7 小端序。
+``arm64`` Maintained 仅小端序。
``loongarch`` Maintained \-
-``riscv`` Maintained 只有 ``riscv64``
-``um`` Maintained 只有 ``x86_64``
-``x86`` Maintained 只有 ``x86_64``
+``riscv`` Maintained 仅 ``riscv64``，且仅限 LLVM/Clang。
+``um`` Maintained \-
+``x86`` Maintained 仅 ``x86_64``。
============= ================ ==============================================
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v2 00/16] fs,x86/resctrl: Add kernel-mode (e.g., PLZA) support to the resctrl subsystem
From: Reinette Chatre @ 2026-04-08 4:45 UTC (permalink / raw)
To: Babu Moger, corbet@lwn.net, tony.luck@intel.com,
Dave.Martin@arm.com, james.morse@arm.com, tglx@kernel.org,
mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com
Cc: skhan@linuxfoundation.org, x86@kernel.org, hpa@zytor.com,
peterz@infradead.org, juri.lelli@redhat.com,
vincent.guittot@linaro.org, dietmar.eggemann@arm.com,
rostedt@goodmis.org, bsegall@google.com, mgorman@suse.de,
vschneid@redhat.com, kas@kernel.org, rick.p.edgecombe@intel.com,
akpm@linux-foundation.org, pmladek@suse.com,
rdunlap@infradead.org, dapeng1.mi@linux.intel.com,
kees@kernel.org, elver@google.com, paulmck@kernel.org,
lirongqing@baidu.com, safinaskar@gmail.com, fvdl@google.com,
seanjc@google.com, pawan.kumar.gupta@linux.intel.com,
xin@zytor.com, tiala@microsoft.com, Neeraj.Upadhyay@amd.com,
chang.seok.bae@intel.com, Lendacky, Thomas,
elena.reshetova@intel.com, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev,
kvm@vger.kernel.org, eranian@google.com, peternewman@google.com
In-Reply-To: <c6f574b7-fe5f-49ae-9865-0e4dbb2f9803@amd.com>
Hi Babu,
On 4/7/26 6:01 PM, Babu Moger wrote:
> Hi Reinette,
>
> On 4/7/26 12:48, Reinette Chatre wrote:
>> Hi Babu,
>>
>> On 4/6/26 3:45 PM, Babu Moger wrote:
>>> Hi Reinette,
>>>
>>> Sorry for the late response. I was trying to get confirmation about the use case.
>>
>> No problem. I appreciate that you did this so that we can make sure resctrl supports
>> needed use cases.
>>
>>>
>>> On 3/31/26 17:24, Reinette Chatre wrote:
>>>> On 3/30/26 11:46 AM, Babu Moger wrote:
>>>>> On 3/27/26 17:11, Reinette Chatre wrote:
>>>>>> On 3/26/26 10:12 AM, Babu Moger wrote:
>>>>>>> On 3/24/26 17:51, Reinette Chatre wrote:
>>>>>>>> On 3/12/26 1:36 PM, Babu Moger wrote:
>>
>>>> can have domains that span different CPUs. There thus seem to be a built in assumption of what a "domain"
>>>> means for PQR_PLZA_ASSOC so it sounds to me as though, instead of saying that "PQR_PLZA_ASSOC needs
>>>> to be the same in QoS domain" it may be more accurate to, for example, say that "PQR_PLZA_ASSOC has L3 scope"?
>>>
>>> Yes.
>>
>> Above is about L3 scope ...
>
> Yes. The scope for PQR_PLZA_ASSOC is L3.
>
> Is that what you are asking here?
I was trying to point out that there appears to be a mismatch between the actual scope and
the planned implementation. As highlighted below during the discussion about "global" this is
fine with me and I just wanted to confirm that this matches your intentions.
>
>>
>>>>
>>>> This seems to be what this implementation does since it hardcodes PQR_PLZA_ASSOC scope to the L3
>>>> resource but that creates dependency to the L3 resource that would make PLZA unusable if, for example,
>>>> the user boots with "rdt=!l3cat" while wanting to use PLZA to manage MBA allocations when in kernel?
>>>
>>> Yes. that is correct. It should not be attached to one resource. We need to change it to global scope.
>>
>> Can I interpret "global scope" as "all online CPUs"? Doing so will simplify
>
> Yes. That is correct.
>
>
>> supporting this feature. It does not sound practical for a user wanting to assign
>> different resource groups to kernel work done in different domains ... the guidance should
>> instead be to just set the allocations of one resource group to what is needed in the different
>> domains? There may be more flexibility when supporting per-domain RMIDs though but so far
>> it sounds as though the focus is global. We can consider what needs to be done to support
>> some type of "per-domain" assignment as exercise whether current interface could support it
>> in the future.
>
> Yes. Makes sense.
>
>>
...
>>> The PLZA MSR is updated when user changes the association to the
>>> file. No context switch code changes are needed. This will be
>>> dedicated group. The current resctrl group files, "cpus, cpus_list
>>
>> Why does this have to be a dedicated group? One of the conclusions from v1
>> discussion was that the "PLZA group" need *not* be a dedicated group. I repeated that
>> in my earlier response that I left quoted above. You did not respond to these
>> conclusions and statements in this regard while you keep coming back to this
>> needing to be a dedicated group without providing a motivation to do so.
>> Could you please elaborate why a dedicated group is required?
>
> If the same group applies identical limits to both user and kernel
> space, it essentially behaves like a current resctrl group. In that
> sense, it’s not really a PLZA group. PLZA’s key value is the ability
> to separate allocations between user space and kernel space. A
The plan has never been to force identical allocations for user and kernel
space since that would go against this feature entirely. Even so, just as
user and kernel space cannot be forced to have identical allocations they
also cannot be forced to have different allocations. Specifically,
a task *can* use the same CLOSID for user and kernel space work just as easily
as it can use *different* CLOSID for user and kernel space work. There
should not be any CLOSID reserved just for kernel work. Or am I missing something?
> single CPU can belong to two groups: one group manages the user-
> space allocation for that CPU, while another manages the kernel-mode
> allocation.
Exactly. This is why it is important to have two files for this CPU association
within a resource group. The cpus/cpus_list file continues to be used as today
while the new kernel_mode_cpus/kernel_mode_cpus_list is used for kernel work.
With this a task can be associated with any resource group for its user space
allocations but when it runs on one of the CPUs within kernel_mode_cpus then
its kernel work will be done with allocations of the resource group the
kernel_mode_cpus file belongs to, which may or may not be the same
resource group that the user space task belongs to.
> This approach also simplifies file handling, which is another reason
> I prefer it.
I *think* we have different interpretations of "dedicated group":
It sounds as though you interpret "dedicated group" as a way that enforces
the same allocations to user space and kernel work.
I interpret "dedicated group" essentially as a CLOSID reserved for kernel
work. Since I do not see that resctrl should dedicate a CLOSID/resource group
for kernel work I have been pushing against such "dedicated group".
> That said, I’m open to not having a dedicated group if we can still support all the features that PLZA provides without it.
I find that enabling user space to share CLOSID/RMID between user space
and kernel space to indeed support what PLZA provides. I think I am missing
something here since below proposal again attempts to isolate a resource group
(CLOSID) for kernel work.
>>> Add a file, "info/kmode_monitor", to describe how kmode is monitored.
>>>
>>> # cat info/kmode_monitor
>>> [inherit_ctrl_and_mon] <- Kernel uses the same CLOSID/RMID as user. Default option for the "global"
>>> assign_ctrl_inherit_mon <- One CLOSID for all kernel work; RMID inherited from user.
>>> assign_ctrl_assign_mon <- One resource group (CLOSID+RMID) for all kernel work. Default option for "cpu" type.
>>
>> My first thought is that the naming is confusing. resctrl has a very strong relationship between
>> "RMID" and "monitoring" so naming a file "monitor" that deals with allocation/ctrl/CLOSID is
>> potentially confusion.
>>
>> Apart from that, while I think I understand where you are going by separating the mode into
>> two files I am concerned about future complications needing to accommodate all different
>> combinations of the (now) essentially two modes. My preference is thus to keep this simple by
>> keeping the mode within one file.
>>
>> Even so, when stepping back, it does not really look like we need to separate the "global"
>> and "per CPU" modes. We could just have a single "per CPU" mode and the "global" is just
>> its default of "all CPUs", no?
>
> Yes. That correct.
>
>>
>> Consider, for example, the implementation just consisting of:
>>
>> # cat info/kernel_mode
>> [inherit_ctrl_and_mon]
>> global_assign_ctrl_inherit_mon_per_cpu
>> global_assign_ctrl_assign_mon_per_cpu
>>
>>>
>>> Rename “kernel_mode_assignment” to “kmode_group” to assign the specific group to kmode. This file usage is same as before.
>>>
>>> #cat info/kmode_groups (Renamed "kernel_mode_assignment")
>>> //
>>
>> Please consider the intent of this file when thinking about names. The idea is that "info/kernel_mode"
>> specifies the "mode" of how kernel work is handled and it determines the configuration files used in that
>> mode as well as the syntax when interacting with those files. By renaming "kernel_mode_assignment" to
>> "kmode_groups" it implicitly requires all future kernel mode enhancements to need some data related to "groups".
>>
>> In summary, I think this can be simplified by introducing just two new files in info/ that enables the
>> user to (a) select and (b) configure the "kernel mode". To start there can be just two modes,
>> global_assign_ctrl_inherit_mon_per_cpu and global_assign_ctrl_assign_mon_per_cpu.
>> global_assign_ctrl_inherit_mon_per_cpu mode requires a control group in kernel_mode_assignment while
>> global_assign_ctrl_assign_mon_per_cpu requires a control and monitoring group.
>>
>> The resource group in info/kernel_mode_assignment gets two additional files "kernel_mode_cpus" and
>> "kernel_mode_cpus_list" that contains the CPUs enabled with the kernel mode configuration, by default
>> it will be all online CPUs. The resource group can continue to be used to manage allocations of and
>> monitor user space tasks. Specifically, the "cpus", "cpus_list", and "tasks" files remain.
>>
>> A user wanting just "global" settings will get just that when writing the group to
>> info/kernel_mode_assignment. A user wanting "per CPU" settings can follow the
>> info/kernel_mode_assignment setting with changes to that resource group's kernel_mode_cpus/kernel_mode_cpus_list
>> files. Any task running on a CPU that is *not* in kernel_mode_cpus/kernel_mode_cpus_list can be
>> expected to inherit both CLOSID and RMID from user space for all kernel work.
>
> After further consideration, I don’t think the info/kernel_mode file
> is necessary. There’s no need to enforce a specific mode for all the
> PLZA groups. Avoiding this constraint makes the design more
> flexible, particularly as we move toward supporting multiple PLZA
> groups in the future. MPAM already appears capable of handling more
> than one group—for example, one group could use
> inherit_ctrl_and_mon, while another could use
> global_assign_ctrl_inherit_mon_per_cpu.
You are looking ahead at future capabilities for which we do not know all requirements
at this time. I think it is very good to consider how things may progress and your example
of MPAM is of course on point. I believe the current design does consider this progression.
Please see https://lore.kernel.org/lkml/2ab556af-095b-422b-9396-f845c6fd0342@intel.com/
(search for "per_group_assign_ctrl_assign_mon"). In that exploration per-group assignment
is actually accomplished with global files. I thus think we should not make such a big
architectural decision that does not benefit the immediate feature using partial information.
As it is, a "info/kernel_mode" gives the flexibility to expand to, if needed, configuration
files within a resource group. That is why the intention is to associate the mode within
info/kernel_mode with the presence/absence of info/kernel_mode_assignment (search for
"Visibility depends on active mode in info/kernel_mode" in linked email) since in the
future resctrl may need to enable a mode that needs configuration files within each
resource group and when enabling such mode the per-resource group files will appear
instead of the global info/kernel_mode_assignment.
>
> The mode can simply be determined on a per-group basis. We can introduce two new files—kernel_mode_cpus and kernel_mode_cpus_list—within each resctrl group when kmode (or PLZA) is supported.
I think having these files in every resource group is confusing since user can only interact
with these files in one resource group for current PLZA. Why not *just* have the files in the
resource group that matches the group in info/kernel_mode_assignment?
>
> The info/kernel_mode_assignment file would indicate which resctrl
> group(or groups) is used for PLZA. The files—kernel_mode_cpus and
> kernel_mode_cpus_list would indicate how the plza is applied which
> each group.
The "how PLZA is applied" should be learned from info/kernel_mode where user
space learns whether RMID is inherited or not. While I find kernel_mode_cpus
and kernel_mode_cpus_list to be just for configuration and just found in the
resource group listed in info/kernel_mode_assignment.
>
> Files and behavior:
> - cpus / cpus_list:
>
> CPUs listed here use the same allocation for both user and kernel space.
Both user and kernel space?
Monitoring would depend on info/kernel_mode_assignment ("inherit_mon")
and kernel space allocation would depend on whether the CPU on which the task runs
can be found in kernel_mode_cpus, no?
> There is no change to the current semantics of these files.
> If these files are empty, the group effectively becomes a PLZA-dedicated group.
I do not see it this way. If the cpu/cpus_list files are empty then it means that the
tasks in the group will use their own CLOSID/RMID for user space allocation and
monitoring. What allocations/monitoring is used by tasks when in kernel mode depends
on whether the CPU the task is running on can be found in a kernel_mode_cpus/kernel_mode_cpuslist
file. If the CPU the task is running on can be found in a kernel_mode_cpus/kernel_mode_cpuslist
file then it will inherit whatever the PQR_PLZA setting of that CPU which is the allocation
associated with the resource group to which that kernel_mode_cpus/kernel_mode_cpuslist belongs.
If the CPU the task is running on cannot be found in kernel_mode_cpus/kernel_mode_cpuslist
then its kernel work will inherit its user space allocations and monitoring.
>
> - kernel_mode_cpus / kernel_mode_cpus_list:
>
> These files determine whether a separate kernel allocation is applied.
> If empty, user and kernel share the same allocation.
> If non-empty, the kernel uses a separate allocation.
>
> The group can be CTL_MON or MON group. Based on type the group the CLOSID and RMID will be used to enable PLZA. If it is MON, then rmid_en = 1 when writing PLZA MSR.
This will be difficult to get right since CTRL_MON groups also have RMID assigned.
> Here’s the proposed flow:
>
> # mount -t resctrl resctrl /sys/fs/resctrl/
> # cd /sys/fs/resctrl/
> # cat info/kernel_mode_assignment
> //
>
> By default, the root (default) group is PLZA-enabled when resctrl is mounted. All CPUs use CLOSID 0 for both user and kernel-mode allocation.
>
> # cat cpus_list
> 1-64
> # cat kmode_cpus_list
> 1-64
>
> Next, create a new group for PLZA:
>
> # mkdir plza_group
>
> # echo "plza_group//" > info/kernel_mode_assignment
>
> At this point, plza_group becomes the new PLZA-enabled group, and the PLZA-related MSRs are updated accordingly.
It really looks like you are getting back to trying to dedicate a resource group to
kernel work and that is not something that resctrl should enforce.
>
> # cat plza_group/cpus_list
> <empty>
>
> # cat plza_group/kmode_cpus_list
> 1-64
>
> The user can then update kmode_cpus_list to apply PLZA only to a specific subset of CPUs, if desired.
>
>
> What do you think of this approach?
It is difficult to predict how the "next" PLZA will actually end up looking like and I find resctrl creating a complicated
interface to support this to be risky. Instead I would prefer to focus on efficiently supporting what PLZA can do today
and make it extensible. Apart from that I find the implicit interface, "If it is MON, then rmid_en = 1" to be too
architecture specific for a generic interface while also not able to accurately capture user's intent (i.e. user may
indeed, for example, want "a CTRL_MON group to have rmid_en = 1"). Finally, I am just so confused about why the implementations
keep needing to dedicate a resource group/CLOSID to kernel work.
Reinette
^ permalink raw reply
* Re: [PATCH] crash: Support high memory reservation for range syntax
From: Sourabh Jain @ 2026-04-08 4:31 UTC (permalink / raw)
To: Youling Tang, Andrew Morton, Baoquan He, Jonathan Corbet
Cc: Vivek Goyal, Dave Young, kexec, linux-kernel, linux-doc,
Youling Tang
In-Reply-To: <20260404074103.506793-1-youling.tang@linux.dev>
Hello Youling,
On 04/04/26 13:11, Youling Tang wrote:
> From: Youling Tang <tangyouling@kylinos.cn>
>
> The crashkernel range syntax (range1:size1[,range2:size2,...]) allows
> automatic size selection based on system RAM, but it always reserves
> from low memory. When a large crashkernel is selected, this can
> consume most of the low memory, causing subsequent hardware
> hotplug or drivers requiring low memory to fail due to allocation
> failures.
Support for high crashkernel reservation has been added to
address the above problem.
However, high crashkernel reservation is not supported with
range-based crashkernel kernel command-line arguments.
For example: crashkernel=0M-1G:100M,1G-4G:160M,4G-8G:192M
Many users, including some distributions, use range-based
crashkernel configuration. So, adding support for high crashkernel
reservation with range-based configuration would be useful.
>
> Add a new optional conditional suffix ",>boundary" to the crashkernel
> range syntax. When the selected crashkernel size exceeds the specified
> boundary, the kernel will automatically apply the same reservation
> policy as "crashkernel=size,high" - preferring high memory first
> and reserving the default low memory area.
I think the approach to enable high crashkernel reservation
with range-based configuration makes the crashkernel kernel
argument more complex.
If the goal is to support high crashkernel reservation with
range-based kernel command-line arguments, how about:
crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset],high
instead of using >boundary?
>
> Syntax:
> crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset],>boundary
>
> Example:
> crashkernel=2G-16G:512M,16G-:1G,>512M
>
> This means:
> - For 2G-16G RAM: reserve 512M normally
> - For >16G RAM: reserve 1G with high memory preference (since 1G > 512M)
>
> For systems with >16G RAM, 1G is selected which exceeds 512M, so it
> will be reserved from high memory instead of consuming 1G of
> precious low memory.
>
> Signed-off-by: Youling Tang <tangyouling@kylinos.cn>
> ---
> Documentation/admin-guide/kdump/kdump.rst | 25 ++++++++-
> .../admin-guide/kernel-parameters.txt | 2 +-
> kernel/crash_reserve.c | 56 ++++++++++++++++---
> 3 files changed, 73 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/admin-guide/kdump/kdump.rst b/Documentation/admin-guide/kdump/kdump.rst
> index 7587caadbae1..b5ae4556e9ca 100644
> --- a/Documentation/admin-guide/kdump/kdump.rst
> +++ b/Documentation/admin-guide/kdump/kdump.rst
> @@ -293,7 +293,28 @@ crashkernel syntax
> 2) if the RAM size is between 512M and 2G (exclusive), then reserve 64M
> 3) if the RAM size is larger than 2G, then reserve 128M
>
> -3) crashkernel=size,high and crashkernel=size,low
> +3) range1:size1[,range2:size2,...][@offset],>boundary
> + Optionally, the range list can be followed by a conditional suffix
> + `,>boundary`. When the selected crashkernel size matches the
> + condition, the kernel will reserve memory using the same policy as
> + `crashkernel=size,high` (i.e. prefer high memory first and reserve the
> + default low memory area).
> +
> + The syntax is::
> +
> + crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset],>boundary
> + range=start-[end]
> +
> + For example::
> +
> + crashkernel=2G-16G:512M,16G-:1G,>512M
> +
> + This would mean:
> + 1) if the RAM size is between 2G and 16G (exclusive), then reserve 512M.
> + 2) if the RAM size is larger than 16G, allocation will behave like
> + `crashkernel=1G,high`.
> +
> +4) crashkernel=size,high and crashkernel=size,low
>
> If memory above 4G is preferred, crashkernel=size,high can be used to
> fulfill that. With it, physical memory is allowed to be allocated from top,
> @@ -311,7 +332,7 @@ crashkernel syntax
>
> crashkernel=0,low
>
> -4) crashkernel=size,cma
> +5) crashkernel=size,cma
>
> Reserve additional crash kernel memory from CMA. This reservation is
> usable by the first system's userspace memory and kernel movable
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index 03a550630644..b2e1892ab4d8 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -1087,7 +1087,7 @@ Kernel parameters
> 4G when '@offset' hasn't been specified.
> See Documentation/admin-guide/kdump/kdump.rst for further details.
>
> - crashkernel=range1:size1[,range2:size2,...][@offset]
> + crashkernel=range1:size1[,range2:size2,...][@offset][,>boundary]
> [KNL] Same as above, but depends on the memory
> in the running system. The syntax of range is
> start-[end] where start and end are both
> diff --git a/kernel/crash_reserve.c b/kernel/crash_reserve.c
> index 62e60e0223cf..917738412390 100644
> --- a/kernel/crash_reserve.c
> +++ b/kernel/crash_reserve.c
> @@ -254,15 +254,47 @@ static __init char *get_last_crashkernel(char *cmdline,
> return ck_cmdline;
> }
>
> +/*
> + * This function parses command lines in the format
> + *
> + * crashkernel=ramsize-range:size[,...][@offset],>boundary
> + */
> +static void __init parse_crashkernel_boundary(char *ck_cmdline,
> + unsigned long long *boundary)
> +{
> + char *cur = ck_cmdline, *next;
> + char *first_gt = false;
> +
> + first_gt = strchr(cur, '>');
> + if (!first_gt)
> + return;
> +
> + cur = first_gt + 1;
> + if (*cur == '\0' || *cur == ' ' || *cur == ',') {
> + pr_warn("crashkernel: '>' specified without boundary size, ignoring\n");
> + return;
> + }
> +
> + *boundary = memparse(cur, &next);
> + if (cur == next) {
> + pr_warn("crashkernel: invalid boundary size after '>'\n");
> + return;
> + }
> +}
> +
> static int __init __parse_crashkernel(char *cmdline,
> unsigned long long system_ram,
> unsigned long long *crash_size,
> unsigned long long *crash_base,
> - const char *suffix)
> + const char *suffix,
> + bool *high,
> + unsigned long long *low_size)
> {
> char *first_colon, *first_space;
> char *ck_cmdline;
> char *name = "crashkernel=";
> + unsigned long long boundary = 0;
> + int ret;
>
> BUG_ON(!crash_size || !crash_base);
> *crash_size = 0;
> @@ -283,10 +315,20 @@ static int __init __parse_crashkernel(char *cmdline,
> */
> first_colon = strchr(ck_cmdline, ':');
> first_space = strchr(ck_cmdline, ' ');
> - if (first_colon && (!first_space || first_colon < first_space))
> - return parse_crashkernel_mem(ck_cmdline, system_ram,
> + if (first_colon && (!first_space || first_colon < first_space)) {
> + ret = parse_crashkernel_mem(ck_cmdline, system_ram,
> crash_size, crash_base);
>
> + /* Handle optional ',>boundary' condition for range ':' syntax only. */
> + parse_crashkernel_boundary(ck_cmdline, &boundary);
> + if (!ret && *crash_size > boundary) {
> + *high = true;
> + *low_size = DEFAULT_CRASH_KERNEL_LOW_SIZE;
> + }
> +
> + return ret;
> + }
> +
> return parse_crashkernel_simple(ck_cmdline, crash_size, crash_base);
> }
>
> @@ -310,7 +352,7 @@ int __init parse_crashkernel(char *cmdline,
>
> /* crashkernel=X[@offset] */
> ret = __parse_crashkernel(cmdline, system_ram, crash_size,
> - crash_base, NULL);
> + crash_base, NULL, high, low_size);
> #ifdef CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
> /*
> * If non-NULL 'high' passed in and no normal crashkernel
> @@ -318,7 +360,7 @@ int __init parse_crashkernel(char *cmdline,
> */
> if (high && ret == -ENOENT) {
> ret = __parse_crashkernel(cmdline, 0, crash_size,
> - crash_base, suffix_tbl[SUFFIX_HIGH]);
> + crash_base, suffix_tbl[SUFFIX_HIGH], high, low_size);
> if (ret || !*crash_size)
> return -EINVAL;
>
> @@ -327,7 +369,7 @@ int __init parse_crashkernel(char *cmdline,
> * is not allowed.
> */
> ret = __parse_crashkernel(cmdline, 0, low_size,
> - crash_base, suffix_tbl[SUFFIX_LOW]);
> + crash_base, suffix_tbl[SUFFIX_LOW], high, low_size);
> if (ret == -ENOENT) {
> *low_size = DEFAULT_CRASH_KERNEL_LOW_SIZE;
> ret = 0;
> @@ -344,7 +386,7 @@ int __init parse_crashkernel(char *cmdline,
> */
> if (cma_size)
> __parse_crashkernel(cmdline, 0, cma_size,
> - &cma_base, suffix_tbl[SUFFIX_CMA]);
> + &cma_base, suffix_tbl[SUFFIX_CMA], high, low_size);
> #endif
> if (!*crash_size)
> ret = -EINVAL;
^ permalink raw reply
* [PATCH net-next v04 4/6] hinic3: Add ethtool rss ops
From: Fan Gong @ 2026-04-08 4:03 UTC (permalink / raw)
To: Fan Gong, Zhu Yikai, netdev, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Andrew Lunn,
Ioana Ciornei, Mohsin Bashir
Cc: linux-kernel, linux-doc, luosifu, Xin Guo, Zhou Shuai, Wu Like,
Shi Jing, Zheng Jiezhen, Maxime Chevallier
In-Reply-To: <cover.1775618797.git.zhuyikai1@h-partners.com>
Implement following ethtool callback function:
.get_rxnfc
.set_rxnfc
.get_channels
.set_channels
.get_rxfh_indir_size
.get_rxfh_key_size
.get_rxfh
.set_rxfh
These callbacks allow users to utilize ethtool for detailed
RSS parameters configuration and monitoring.
Co-developed-by: Zhu Yikai <zhuyikai1@h-partners.com>
Signed-off-by: Zhu Yikai <zhuyikai1@h-partners.com>
Signed-off-by: Fan Gong <gongfan1@huawei.com>
---
.../ethernet/huawei/hinic3/hinic3_ethtool.c | 9 +
.../huawei/hinic3/hinic3_mgmt_interface.h | 2 +
| 487 +++++++++++++++++-
| 19 +
4 files changed, 515 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_ethtool.c b/drivers/net/ethernet/huawei/hinic3/hinic3_ethtool.c
index a4b2d5ba81f8..8cd7dd9da67b 100644
--- a/drivers/net/ethernet/huawei/hinic3/hinic3_ethtool.c
+++ b/drivers/net/ethernet/huawei/hinic3/hinic3_ethtool.c
@@ -15,6 +15,7 @@
#include "hinic3_hw_comm.h"
#include "hinic3_nic_dev.h"
#include "hinic3_nic_cfg.h"
+#include "hinic3_rss.h"
#define HINIC3_MGMT_VERSION_MAX_LEN 32
/* Coalesce time properties in microseconds */
@@ -1231,6 +1232,14 @@ static const struct ethtool_ops hinic3_ethtool_ops = {
.get_pause_stats = hinic3_get_pause_stats,
.get_coalesce = hinic3_get_coalesce,
.set_coalesce = hinic3_set_coalesce,
+ .get_rxnfc = hinic3_get_rxnfc,
+ .set_rxnfc = hinic3_set_rxnfc,
+ .get_channels = hinic3_get_channels,
+ .set_channels = hinic3_set_channels,
+ .get_rxfh_indir_size = hinic3_get_rxfh_indir_size,
+ .get_rxfh_key_size = hinic3_get_rxfh_key_size,
+ .get_rxfh = hinic3_get_rxfh,
+ .set_rxfh = hinic3_set_rxfh,
};
void hinic3_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h b/drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h
index 76c691f82703..3c1263ff99ff 100644
--- a/drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h
+++ b/drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h
@@ -282,6 +282,7 @@ enum l2nic_cmd {
L2NIC_CMD_SET_VLAN_FILTER_EN = 26,
L2NIC_CMD_SET_RX_VLAN_OFFLOAD = 27,
L2NIC_CMD_CFG_RSS = 60,
+ L2NIC_CMD_GET_RSS_CTX_TBL = 62,
L2NIC_CMD_CFG_RSS_HASH_KEY = 63,
L2NIC_CMD_CFG_RSS_HASH_ENGINE = 64,
L2NIC_CMD_SET_RSS_CTX_TBL = 65,
@@ -301,6 +302,7 @@ enum l2nic_ucode_cmd {
L2NIC_UCODE_CMD_MODIFY_QUEUE_CTX = 0,
L2NIC_UCODE_CMD_CLEAN_QUEUE_CTX = 1,
L2NIC_UCODE_CMD_SET_RSS_INDIR_TBL = 4,
+ L2NIC_UCODE_CMD_GET_RSS_INDIR_TBL = 6,
};
/* hilink mac group command */
--git a/drivers/net/ethernet/huawei/hinic3/hinic3_rss.c b/drivers/net/ethernet/huawei/hinic3/hinic3_rss.c
index 25db74d8c7dd..b40d5fa885c2 100644
--- a/drivers/net/ethernet/huawei/hinic3/hinic3_rss.c
+++ b/drivers/net/ethernet/huawei/hinic3/hinic3_rss.c
@@ -155,7 +155,7 @@ static int hinic3_set_rss_type(struct hinic3_hwdev *hwdev,
L2NIC_CMD_SET_RSS_CTX_TBL, &msg_params);
if (ctx_tbl.msg_head.status == MGMT_STATUS_CMD_UNSUPPORTED) {
- return MGMT_STATUS_CMD_UNSUPPORTED;
+ return -EOPNOTSUPP;
} else if (err || ctx_tbl.msg_head.status) {
dev_err(hwdev->dev, "mgmt Failed to set rss context offload, err: %d, status: 0x%x\n",
err, ctx_tbl.msg_head.status);
@@ -165,6 +165,39 @@ static int hinic3_set_rss_type(struct hinic3_hwdev *hwdev,
return 0;
}
+static int hinic3_get_rss_type(struct hinic3_hwdev *hwdev,
+ struct hinic3_rss_type *rss_type)
+{
+ struct l2nic_cmd_rss_ctx_tbl ctx_tbl = {};
+ struct mgmt_msg_params msg_params = {};
+ int err;
+
+ ctx_tbl.func_id = hinic3_global_func_id(hwdev);
+
+ mgmt_msg_params_init_default(&msg_params, &ctx_tbl, sizeof(ctx_tbl));
+
+ err = hinic3_send_mbox_to_mgmt(hwdev, MGMT_MOD_L2NIC,
+ L2NIC_CMD_GET_RSS_CTX_TBL,
+ &msg_params);
+ if (err || ctx_tbl.msg_head.status) {
+ dev_err(hwdev->dev, "Failed to get hash type, err: %d, status: 0x%x\n",
+ err, ctx_tbl.msg_head.status);
+ return -EINVAL;
+ }
+
+ rss_type->ipv4 = L2NIC_RSS_TYPE_GET(ctx_tbl.context, IPV4);
+ rss_type->ipv6 = L2NIC_RSS_TYPE_GET(ctx_tbl.context, IPV6);
+ rss_type->ipv6_ext = L2NIC_RSS_TYPE_GET(ctx_tbl.context, IPV6_EXT);
+ rss_type->tcp_ipv4 = L2NIC_RSS_TYPE_GET(ctx_tbl.context, TCP_IPV4);
+ rss_type->tcp_ipv6 = L2NIC_RSS_TYPE_GET(ctx_tbl.context, TCP_IPV6);
+ rss_type->tcp_ipv6_ext = L2NIC_RSS_TYPE_GET(ctx_tbl.context,
+ TCP_IPV6_EXT);
+ rss_type->udp_ipv4 = L2NIC_RSS_TYPE_GET(ctx_tbl.context, UDP_IPV4);
+ rss_type->udp_ipv6 = L2NIC_RSS_TYPE_GET(ctx_tbl.context, UDP_IPV6);
+
+ return 0;
+}
+
static int hinic3_rss_cfg_hash_type(struct hinic3_hwdev *hwdev, u8 opcode,
enum hinic3_rss_hash_type *type)
{
@@ -264,7 +297,8 @@ static int hinic3_set_hw_rss_parameters(struct net_device *netdev, u8 rss_en)
if (err)
return err;
- hinic3_fillout_indir_tbl(netdev, nic_dev->rss_indir);
+ if (!netif_is_rxfh_configured(netdev))
+ hinic3_fillout_indir_tbl(netdev, nic_dev->rss_indir);
err = hinic3_config_rss_hw_resource(netdev, nic_dev->rss_indir);
if (err)
@@ -334,3 +368,452 @@ void hinic3_try_to_enable_rss(struct net_device *netdev)
clear_bit(HINIC3_RSS_ENABLE, &nic_dev->flags);
nic_dev->q_params.num_qps = nic_dev->max_qps;
}
+
+static int hinic3_set_l4_rss_hash_ops(const struct ethtool_rxnfc *cmd,
+ struct hinic3_rss_type *rss_type)
+{
+ u8 rss_l4_en;
+
+ switch (cmd->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
+ case 0:
+ rss_l4_en = 0;
+ break;
+ case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
+ rss_l4_en = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (cmd->flow_type) {
+ case TCP_V4_FLOW:
+ rss_type->tcp_ipv4 = rss_l4_en;
+ break;
+ case TCP_V6_FLOW:
+ rss_type->tcp_ipv6 = rss_l4_en;
+ break;
+ case UDP_V4_FLOW:
+ rss_type->udp_ipv4 = rss_l4_en;
+ break;
+ case UDP_V6_FLOW:
+ rss_type->udp_ipv6 = rss_l4_en;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int hinic3_update_rss_hash_opts(struct net_device *netdev,
+ struct ethtool_rxnfc *cmd,
+ struct hinic3_rss_type *rss_type)
+{
+ int err;
+
+ switch (cmd->flow_type) {
+ case TCP_V4_FLOW:
+ case TCP_V6_FLOW:
+ case UDP_V4_FLOW:
+ case UDP_V6_FLOW:
+ err = hinic3_set_l4_rss_hash_ops(cmd, rss_type);
+ if (err)
+ return err;
+
+ break;
+ case IPV4_FLOW:
+ rss_type->ipv4 = 1;
+ break;
+ case IPV6_FLOW:
+ rss_type->ipv6 = 1;
+ break;
+ default:
+ netdev_err(netdev, "Unsupported flow type\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int hinic3_set_rss_hash_opts(struct net_device *netdev,
+ struct ethtool_rxnfc *cmd)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ struct hinic3_rss_type rss_type;
+ int err;
+
+ if (!test_bit(HINIC3_RSS_ENABLE, &nic_dev->flags)) {
+ cmd->data = 0;
+ netdev_err(netdev, "RSS is disable, not support to set flow-hash\n");
+ return -EOPNOTSUPP;
+ }
+
+ /* RSS only supports hashing of IP addresses and L4 ports */
+ if (cmd->data & ~(RXH_IP_SRC | RXH_IP_DST |
+ RXH_L4_B_0_1 | RXH_L4_B_2_3))
+ return -EINVAL;
+
+ /* Both IP addresses must be part of the hash tuple */
+ if (!(cmd->data & RXH_IP_SRC) || !(cmd->data & RXH_IP_DST))
+ return -EINVAL;
+
+ err = hinic3_get_rss_type(nic_dev->hwdev, &rss_type);
+ if (err) {
+ netdev_err(netdev, "Failed to get rss type\n");
+ return err;
+ }
+
+ err = hinic3_update_rss_hash_opts(netdev, cmd, &rss_type);
+ if (err)
+ return err;
+
+ err = hinic3_set_rss_type(nic_dev->hwdev, rss_type);
+ if (err) {
+ netdev_err(netdev, "Failed to set rss type\n");
+ return err;
+ }
+
+ nic_dev->rss_type = rss_type;
+
+ return 0;
+}
+
+static void convert_rss_type(u8 rss_opt, struct ethtool_rxnfc *cmd)
+{
+ if (rss_opt)
+ cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
+}
+
+static int hinic3_convert_rss_type(struct net_device *netdev,
+ struct hinic3_rss_type *rss_type,
+ struct ethtool_rxnfc *cmd)
+{
+ cmd->data = RXH_IP_SRC | RXH_IP_DST;
+ switch (cmd->flow_type) {
+ case TCP_V4_FLOW:
+ convert_rss_type(rss_type->tcp_ipv4, cmd);
+ break;
+ case TCP_V6_FLOW:
+ convert_rss_type(rss_type->tcp_ipv6, cmd);
+ break;
+ case UDP_V4_FLOW:
+ convert_rss_type(rss_type->udp_ipv4, cmd);
+ break;
+ case UDP_V6_FLOW:
+ convert_rss_type(rss_type->udp_ipv6, cmd);
+ break;
+ case IPV4_FLOW:
+ case IPV6_FLOW:
+ break;
+ default:
+ netdev_err(netdev, "Unsupported flow type\n");
+ cmd->data = 0;
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int hinic3_get_rss_hash_opts(struct net_device *netdev,
+ struct ethtool_rxnfc *cmd)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ struct hinic3_rss_type rss_type;
+ int err;
+
+ cmd->data = 0;
+
+ if (!test_bit(HINIC3_RSS_ENABLE, &nic_dev->flags))
+ return 0;
+
+ err = hinic3_get_rss_type(nic_dev->hwdev, &rss_type);
+ if (err) {
+ netdev_err(netdev, "Failed to get rss type\n");
+ return err;
+ }
+
+ return hinic3_convert_rss_type(netdev, &rss_type, cmd);
+}
+
+int hinic3_get_rxnfc(struct net_device *netdev,
+ struct ethtool_rxnfc *cmd, u32 *rule_locs)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ int err = 0;
+
+ switch (cmd->cmd) {
+ case ETHTOOL_GRXRINGS:
+ cmd->data = nic_dev->q_params.num_qps;
+ break;
+ case ETHTOOL_GRXFH:
+ err = hinic3_get_rss_hash_opts(netdev, cmd);
+ break;
+ default:
+ err = -EOPNOTSUPP;
+ break;
+ }
+
+ return err;
+}
+
+int hinic3_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
+{
+ int err;
+
+ switch (cmd->cmd) {
+ case ETHTOOL_SRXFH:
+ err = hinic3_set_rss_hash_opts(netdev, cmd);
+ break;
+ default:
+ err = -EOPNOTSUPP;
+ break;
+ }
+
+ return err;
+}
+
+static u16 hinic3_max_channels(struct net_device *netdev)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ u8 tcs = netdev_get_num_tc(netdev);
+
+ return tcs ? nic_dev->max_qps / tcs : nic_dev->max_qps;
+}
+
+static u16 hinic3_curr_channels(struct net_device *netdev)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+
+ if (netif_running(netdev))
+ return nic_dev->q_params.num_qps ?
+ nic_dev->q_params.num_qps : 1;
+ else
+ return min_t(u16, hinic3_max_channels(netdev),
+ nic_dev->q_params.num_qps);
+}
+
+void hinic3_get_channels(struct net_device *netdev,
+ struct ethtool_channels *channels)
+{
+ channels->max_rx = 0;
+ channels->max_tx = 0;
+ channels->max_other = 0;
+ /* report maximum channels */
+ channels->max_combined = hinic3_max_channels(netdev);
+ channels->rx_count = 0;
+ channels->tx_count = 0;
+ channels->other_count = 0;
+ /* report flow director queues as maximum channels */
+ channels->combined_count = hinic3_curr_channels(netdev);
+}
+
+static int
+hinic3_validate_channel_parameter(struct net_device *netdev,
+ const struct ethtool_channels *channels)
+{
+ u16 max_channel = hinic3_max_channels(netdev);
+ unsigned int count = channels->combined_count;
+
+ if (!count) {
+ netdev_err(netdev, "Unsupported combined_count=0\n");
+ return -EINVAL;
+ }
+
+ if (channels->tx_count || channels->rx_count || channels->other_count) {
+ netdev_err(netdev, "Setting rx/tx/other count not supported\n");
+ return -EINVAL;
+ }
+
+ if (count > max_channel) {
+ netdev_err(netdev, "Combined count %u exceed limit %u\n", count,
+ max_channel);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int hinic3_set_channels(struct net_device *netdev,
+ struct ethtool_channels *channels)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ unsigned int count = channels->combined_count;
+ struct hinic3_dyna_txrxq_params q_params;
+ int err;
+
+ if (hinic3_validate_channel_parameter(netdev, channels))
+ return -EINVAL;
+
+ if (!test_bit(HINIC3_RSS_ENABLE, &nic_dev->flags)) {
+ netdev_err(netdev, "This function doesn't support RSS, only support 1 queue pair\n");
+ return -EOPNOTSUPP;
+ }
+
+ netdev_dbg(netdev, "Set max combined queue number from %u to %u\n",
+ nic_dev->q_params.num_qps, count);
+
+ if (netif_running(netdev)) {
+ q_params = nic_dev->q_params;
+ q_params.num_qps = (u16)count;
+ q_params.txqs_res = NULL;
+ q_params.rxqs_res = NULL;
+ q_params.irq_cfg = NULL;
+
+ err = hinic3_change_channel_settings(netdev, &q_params);
+ if (err) {
+ netdev_err(netdev, "Failed to change channel settings\n");
+ return err;
+ }
+ } else {
+ nic_dev->q_params.num_qps = (u16)count;
+ }
+
+ return 0;
+}
+
+u32 hinic3_get_rxfh_indir_size(struct net_device *netdev)
+{
+ return L2NIC_RSS_INDIR_SIZE;
+}
+
+static int hinic3_set_rss_rxfh(struct net_device *netdev,
+ const u32 *indir, u8 *key)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ int err;
+ u32 i;
+
+ if (indir) {
+ for (i = 0; i < L2NIC_RSS_INDIR_SIZE; i++)
+ nic_dev->rss_indir[i] = (u16)indir[i];
+
+ err = hinic3_rss_set_indir_tbl(nic_dev->hwdev,
+ nic_dev->rss_indir);
+ if (err) {
+ netdev_err(netdev, "Failed to set rss indir table\n");
+ return err;
+ }
+ }
+
+ if (key) {
+ err = hinic3_rss_set_hash_key(nic_dev->hwdev, key);
+ if (err) {
+ netdev_err(netdev, "Failed to set rss key\n");
+ return err;
+ }
+
+ memcpy(nic_dev->rss_hkey, key, L2NIC_RSS_KEY_SIZE);
+ }
+
+ return 0;
+}
+
+u32 hinic3_get_rxfh_key_size(struct net_device *netdev)
+{
+ return L2NIC_RSS_KEY_SIZE;
+}
+
+static int hinic3_rss_get_indir_tbl(struct hinic3_hwdev *hwdev,
+ u32 *indir_table)
+{
+ struct hinic3_cmd_buf_pair pair;
+ __le16 *indir_tbl = NULL;
+ int err, i;
+
+ err = hinic3_cmd_buf_pair_init(hwdev, &pair);
+ if (err) {
+ dev_err(hwdev->dev, "Failed to allocate cmd_buf.\n");
+ return err;
+ }
+
+ err = hinic3_cmdq_detail_resp(hwdev, MGMT_MOD_L2NIC,
+ L2NIC_UCODE_CMD_GET_RSS_INDIR_TBL,
+ pair.in, pair.out, NULL);
+ if (err) {
+ dev_err(hwdev->dev, "Failed to get rss indir table\n");
+ goto err_get_indir_tbl;
+ }
+
+ indir_tbl = (__le16 *)pair.out->buf;
+ for (i = 0; i < L2NIC_RSS_INDIR_SIZE; i++)
+ indir_table[i] = le16_to_cpu(*(indir_tbl + i));
+
+err_get_indir_tbl:
+ hinic3_cmd_buf_pair_uninit(hwdev, &pair);
+
+ return err;
+}
+
+int hinic3_get_rxfh(struct net_device *netdev,
+ struct ethtool_rxfh_param *rxfh)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ int err = 0;
+
+ if (!test_bit(HINIC3_RSS_ENABLE, &nic_dev->flags)) {
+ netdev_err(netdev, "Rss is disabled\n");
+ return -EOPNOTSUPP;
+ }
+
+ rxfh->hfunc =
+ nic_dev->rss_hash_type == HINIC3_RSS_HASH_ENGINE_TYPE_XOR ?
+ ETH_RSS_HASH_XOR : ETH_RSS_HASH_TOP;
+
+ if (rxfh->indir) {
+ err = hinic3_rss_get_indir_tbl(nic_dev->hwdev, rxfh->indir);
+ if (err)
+ return err;
+ }
+
+ if (rxfh->key)
+ memcpy(rxfh->key, nic_dev->rss_hkey, L2NIC_RSS_KEY_SIZE);
+
+ return err;
+}
+
+static int hinic3_update_hash_func_type(struct net_device *netdev, u8 hfunc)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ enum hinic3_rss_hash_type new_rss_hash_type;
+
+ switch (hfunc) {
+ case ETH_RSS_HASH_NO_CHANGE:
+ return 0;
+ case ETH_RSS_HASH_XOR:
+ new_rss_hash_type = HINIC3_RSS_HASH_ENGINE_TYPE_XOR;
+ break;
+ case ETH_RSS_HASH_TOP:
+ new_rss_hash_type = HINIC3_RSS_HASH_ENGINE_TYPE_TOEP;
+ break;
+ default:
+ netdev_err(netdev, "Unsupported hash func %u\n", hfunc);
+ return -EOPNOTSUPP;
+ }
+
+ if (new_rss_hash_type == nic_dev->rss_hash_type)
+ return 0;
+
+ nic_dev->rss_hash_type = new_rss_hash_type;
+ return hinic3_rss_set_hash_type(nic_dev->hwdev, nic_dev->rss_hash_type);
+}
+
+int hinic3_set_rxfh(struct net_device *netdev,
+ struct ethtool_rxfh_param *rxfh,
+ struct netlink_ext_ack *extack)
+{
+ struct hinic3_nic_dev *nic_dev = netdev_priv(netdev);
+ int err;
+
+ if (!test_bit(HINIC3_RSS_ENABLE, &nic_dev->flags)) {
+ netdev_err(netdev, "Not support to set rss parameters when rss is disable\n");
+ return -EOPNOTSUPP;
+ }
+
+ err = hinic3_update_hash_func_type(netdev, rxfh->hfunc);
+ if (err)
+ return err;
+
+ err = hinic3_set_rss_rxfh(netdev, rxfh->indir, rxfh->key);
+
+ return err;
+}
--git a/drivers/net/ethernet/huawei/hinic3/hinic3_rss.h b/drivers/net/ethernet/huawei/hinic3/hinic3_rss.h
index 78d82c2aca06..9f1b77780cd4 100644
--- a/drivers/net/ethernet/huawei/hinic3/hinic3_rss.h
+++ b/drivers/net/ethernet/huawei/hinic3/hinic3_rss.h
@@ -5,10 +5,29 @@
#define _HINIC3_RSS_H_
#include <linux/netdevice.h>
+#include <linux/ethtool.h>
int hinic3_rss_init(struct net_device *netdev);
void hinic3_rss_uninit(struct net_device *netdev);
void hinic3_try_to_enable_rss(struct net_device *netdev);
void hinic3_clear_rss_config(struct net_device *netdev);
+int hinic3_get_rxnfc(struct net_device *netdev,
+ struct ethtool_rxnfc *cmd, u32 *rule_locs);
+int hinic3_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd);
+
+void hinic3_get_channels(struct net_device *netdev,
+ struct ethtool_channels *channels);
+int hinic3_set_channels(struct net_device *netdev,
+ struct ethtool_channels *channels);
+
+u32 hinic3_get_rxfh_indir_size(struct net_device *netdev);
+u32 hinic3_get_rxfh_key_size(struct net_device *netdev);
+
+int hinic3_get_rxfh(struct net_device *netdev,
+ struct ethtool_rxfh_param *rxfh);
+int hinic3_set_rxfh(struct net_device *netdev,
+ struct ethtool_rxfh_param *rxfh,
+ struct netlink_ext_ack *extack);
+
#endif
--
2.43.0
^ permalink raw reply related
* [PATCH net-next v04 6/6] hinic3: Remove unneeded coalesce parameters
From: Fan Gong @ 2026-04-08 4:03 UTC (permalink / raw)
To: Fan Gong, Zhu Yikai, netdev, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Andrew Lunn,
Ioana Ciornei, Mohsin Bashir
Cc: linux-kernel, linux-doc, luosifu, Xin Guo, Zhou Shuai, Wu Like,
Shi Jing, Zheng Jiezhen, Maxime Chevallier
In-Reply-To: <cover.1775618797.git.zhuyikai1@h-partners.com>
Remove unneeded coalesce parameters in irq handling.
Co-developed-by: Zhu Yikai <zhuyikai1@h-partners.com>
Signed-off-by: Zhu Yikai <zhuyikai1@h-partners.com>
Signed-off-by: Fan Gong <gongfan1@huawei.com>
---
drivers/net/ethernet/huawei/hinic3/hinic3_irq.c | 6 +-----
drivers/net/ethernet/huawei/hinic3/hinic3_rx.h | 3 ---
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_irq.c b/drivers/net/ethernet/huawei/hinic3/hinic3_irq.c
index d3b3927b5408..42464c007174 100644
--- a/drivers/net/ethernet/huawei/hinic3/hinic3_irq.c
+++ b/drivers/net/ethernet/huawei/hinic3/hinic3_irq.c
@@ -156,13 +156,9 @@ static int hinic3_set_interrupt_moder(struct net_device *netdev, u16 q_id,
spin_unlock_irqrestore(&nic_dev->channel_res_lock, flags);
err = hinic3_set_interrupt_cfg(nic_dev->hwdev, info);
- if (err) {
+ if (err)
netdev_err(netdev,
"Failed to modify moderation for Queue: %u\n", q_id);
- } else {
- nic_dev->rxqs[q_id].last_coalesc_timer_cfg = coalesc_timer_cfg;
- nic_dev->rxqs[q_id].last_pending_limit = pending_limit;
- }
return err;
}
diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_rx.h b/drivers/net/ethernet/huawei/hinic3/hinic3_rx.h
index c11d080408a7..2ab691ed11a9 100644
--- a/drivers/net/ethernet/huawei/hinic3/hinic3_rx.h
+++ b/drivers/net/ethernet/huawei/hinic3/hinic3_rx.h
@@ -111,9 +111,6 @@ struct hinic3_rxq {
dma_addr_t cqe_start_paddr;
struct dim dim;
-
- u8 last_coalesc_timer_cfg;
- u8 last_pending_limit;
} ____cacheline_aligned;
struct hinic3_dyna_rxq_res {
--
2.43.0
^ permalink raw reply related
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