* [v11 PATCH 1/2] EDAC: Add EDAC driver for ARM Cortex A72 cores
2025-05-29 3:00 [v11 PATCH 0/2] Add L1 and L2 error detection for A72 Vijay Balakrishna
@ 2025-05-29 3:00 ` Vijay Balakrishna
2025-06-30 16:33 ` Borislav Petkov
2025-05-29 3:00 ` [v11 PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
2025-05-29 9:55 ` [v11 PATCH 0/2] Add L1 and L2 error detection for A72 Borislav Petkov
2 siblings, 1 reply; 6+ messages in thread
From: Vijay Balakrishna @ 2025-05-29 3:00 UTC (permalink / raw)
To: Borislav Petkov, Tony Luck, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: James Morse, Mauro Carvalho Chehab, Robert Richter, linux-edac,
linux-kernel, Tyler Hicks, Marc Zyngier, Sascha Hauer,
Lorenzo Pieralisi, devicetree, Vijay Balakrishna
From: Sascha Hauer <s.hauer@pengutronix.de>
The driver is designed to support error detection and reporting for
Cortex A72 cores, specifically within their L1 and L2 cache systems.
The errors are detected by reading CPU/L2 memory error syndrome
registers.
Unfortunately there is no robust way to inject errors into the caches,
so this driver doesn't contain any code to actually test it. It has
been tested though with code taken from an older version [1] of this
driver. For reasons stated in thread [1], the error injection code is
not suitable for mainline, so it is removed from the driver.
[1] https://lore.kernel.org/all/1521073067-24348-1-git-send-email-york.sun@nxp.com/#t
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Co-developed-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
MAINTAINERS | 7 ++
drivers/edac/Kconfig | 8 ++
drivers/edac/Makefile | 1 +
drivers/edac/edac_a72.c | 230 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 246 insertions(+)
create mode 100644 drivers/edac/edac_a72.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3cbf9ac0d83f..dac4692c10c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8429,6 +8429,13 @@ F: Documentation/driver-api/edac.rst
F: drivers/edac/
F: include/linux/edac.h
+EDAC-A72
+M: Vijay Balakrishna <vijayb@linux.microsoft.com>
+M: Tyler Hicks <code@tyhicks.com>
+L: linux-edac@vger.kernel.org
+S: Supported
+F: drivers/edac/edac_a72.c
+
EDAC-DMC520
M: Lei Wang <lewan@microsoft.com>
L: linux-edac@vger.kernel.org
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 19ad3c3b675d..b824472208c4 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -576,4 +576,12 @@ config EDAC_LOONGSON
errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000
are compatible.
+config EDAC_CORTEX_A72
+ tristate "ARM Cortex A72"
+ depends on ARM64
+ help
+ Support for L1/L2 cache error detection for ARM Cortex A72 processor.
+ The detected and reported errors are from reading CPU/L2 memory error
+ syndrome registers.
+
endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index a8f2d8f6c894..136416f43b44 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -88,3 +88,4 @@ obj-$(CONFIG_EDAC_NPCM) += npcm_edac.o
obj-$(CONFIG_EDAC_ZYNQMP) += zynqmp_edac.o
obj-$(CONFIG_EDAC_VERSAL) += versal_edac.o
obj-$(CONFIG_EDAC_LOONGSON) += loongson_edac.o
+obj-$(CONFIG_EDAC_CORTEX_A72) += edac_a72.o
diff --git a/drivers/edac/edac_a72.c b/drivers/edac/edac_a72.c
new file mode 100644
index 000000000000..4f40616d40a0
--- /dev/null
+++ b/drivers/edac/edac_a72.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cortex A72 EDAC L1 and L2 cache error detection
+ *
+ * Copyright (c) 2020 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (c) 2025 Microsoft Corporation, <vijayb@linux.microsoft.com>
+ *
+ * Based on Code from:
+ * Copyright (c) 2018, NXP Semiconductor
+ * Author: York Sun <york.sun@nxp.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/bitfield.h>
+#include <asm/smp_plat.h>
+
+#include "edac_module.h"
+
+#define DRVNAME "edac-a72"
+
+#define SYS_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2)
+#define SYS_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3)
+
+#define CPUMERRSR_EL1_RAMID GENMASK(30, 24)
+#define L2MERRSR_EL1_CPUID_WAY GENMASK(21, 18)
+
+#define CPUMERRSR_EL1_VALID BIT(31)
+#define CPUMERRSR_EL1_FATAL BIT(63)
+#define L2MERRSR_EL1_VALID BIT(31)
+#define L2MERRSR_EL1_FATAL BIT(63)
+
+#define L1_I_TAG_RAM 0x00
+#define L1_I_DATA_RAM 0x01
+#define L1_D_TAG_RAM 0x08
+#define L1_D_DATA_RAM 0x09
+#define TLB_RAM 0x18
+
+#define MESSAGE_SIZE 64
+
+struct mem_err_synd_reg {
+ u64 cpu_mesr;
+ u64 l2_mesr;
+};
+
+static struct cpumask compat_mask;
+
+static void report_errors(struct edac_device_ctl_info *edac_ctl, int cpu,
+ struct mem_err_synd_reg *mesr)
+{
+ u64 cpu_mesr = mesr->cpu_mesr;
+ u64 l2_mesr = mesr->l2_mesr;
+ char msg[MESSAGE_SIZE];
+
+ if (cpu_mesr & CPUMERRSR_EL1_VALID) {
+ const char *str;
+ bool fatal = cpu_mesr & CPUMERRSR_EL1_FATAL;
+
+ switch (FIELD_GET(CPUMERRSR_EL1_RAMID, cpu_mesr)) {
+ case L1_I_TAG_RAM:
+ str = "L1-I Tag RAM";
+ break;
+ case L1_I_DATA_RAM:
+ str = "L1-I Data RAM";
+ break;
+ case L1_D_TAG_RAM:
+ str = "L1-D Tag RAM";
+ break;
+ case L1_D_DATA_RAM:
+ str = "L1-D Data RAM";
+ break;
+ case TLB_RAM:
+ str = "TLB RAM";
+ break;
+ default:
+ str = "Unspecified";
+ break;
+ }
+
+ snprintf(msg, MESSAGE_SIZE, "%s %s error(s) on CPU %d",
+ str, fatal ? "fatal" : "correctable", cpu);
+
+ if (fatal)
+ edac_device_handle_ue(edac_ctl, cpu, 0, msg);
+ else
+ edac_device_handle_ce(edac_ctl, cpu, 0, msg);
+ }
+
+ if (l2_mesr & L2MERRSR_EL1_VALID) {
+ bool fatal = l2_mesr & L2MERRSR_EL1_FATAL;
+
+ snprintf(msg, MESSAGE_SIZE, "L2 %s error(s) on CPU %d CPUID/WAY 0x%lx",
+ fatal ? "fatal" : "correctable", cpu,
+ FIELD_GET(L2MERRSR_EL1_CPUID_WAY, l2_mesr));
+ if (fatal)
+ edac_device_handle_ue(edac_ctl, cpu, 1, msg);
+ else
+ edac_device_handle_ce(edac_ctl, cpu, 1, msg);
+ }
+}
+
+static void read_errors(void *data)
+{
+ struct mem_err_synd_reg *mesr = data;
+
+ mesr->cpu_mesr = read_sysreg_s(SYS_CPUMERRSR_EL1);
+ if (mesr->cpu_mesr & CPUMERRSR_EL1_VALID) {
+ write_sysreg_s(0, SYS_CPUMERRSR_EL1);
+ isb();
+ }
+ mesr->l2_mesr = read_sysreg_s(SYS_L2MERRSR_EL1);
+ if (mesr->l2_mesr & L2MERRSR_EL1_VALID) {
+ write_sysreg_s(0, SYS_L2MERRSR_EL1);
+ isb();
+ }
+}
+
+static void a72_edac_check(struct edac_device_ctl_info *edac_ctl)
+{
+ struct mem_err_synd_reg mesr;
+ int cpu;
+
+ cpus_read_lock();
+ for_each_cpu_and(cpu, cpu_online_mask, &compat_mask) {
+ smp_call_function_single(cpu, read_errors, &mesr, true);
+ report_errors(edac_ctl, cpu, &mesr);
+ }
+ cpus_read_unlock();
+}
+
+static int a72_edac_probe(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_ctl;
+ struct device *dev = &pdev->dev;
+ int rc;
+
+ edac_ctl = edac_device_alloc_ctl_info(0, "cpu",
+ num_possible_cpus(), "L", 2, 1,
+ edac_device_alloc_index());
+ if (!edac_ctl)
+ return -ENOMEM;
+
+ edac_ctl->edac_check = a72_edac_check;
+ edac_ctl->dev = dev;
+ edac_ctl->mod_name = dev_name(dev);
+ edac_ctl->dev_name = dev_name(dev);
+ edac_ctl->ctl_name = DRVNAME;
+ dev_set_drvdata(dev, edac_ctl);
+
+ rc = edac_device_add_device(edac_ctl);
+ if (rc)
+ goto out_dev;
+
+ return 0;
+
+out_dev:
+ edac_device_free_ctl_info(edac_ctl);
+
+ return rc;
+}
+
+static void a72_edac_remove(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_ctl = dev_get_drvdata(&pdev->dev);
+
+ edac_device_del_device(edac_ctl->dev);
+ edac_device_free_ctl_info(edac_ctl);
+}
+
+static const struct of_device_id cortex_arm64_edac_of_match[] = {
+ { .compatible = "arm,cortex-a72" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, cortex_arm64_edac_of_match);
+
+static struct platform_driver a72_edac_driver = {
+ .probe = a72_edac_probe,
+ .remove = a72_edac_remove,
+ .driver = {
+ .name = DRVNAME,
+ },
+};
+
+static int __init a72_edac_driver_init(void)
+{
+ struct platform_device *pdev;
+ int cpu, err;
+
+ for_each_possible_cpu(cpu) {
+ struct device_node *np __free(device_node) =
+ of_cpu_device_node_get(cpu);
+
+ if (np) {
+ if (of_match_node(cortex_arm64_edac_of_match, np) &&
+ of_property_read_bool(np, "edac-enabled")) {
+ cpumask_set_cpu(cpu, &compat_mask);
+ }
+ } else {
+ pr_warn("failed to find device node for CPU %d\n", cpu);
+ }
+ }
+
+ if (cpumask_empty(&compat_mask))
+ return 0;
+
+ err = platform_driver_register(&a72_edac_driver);
+ if (err)
+ return err;
+
+ pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0);
+ if (IS_ERR(pdev)) {
+ pr_err("failed to register a72 edac device\n");
+ platform_driver_unregister(&a72_edac_driver);
+ return PTR_ERR(pdev);
+ }
+
+ return 0;
+}
+
+static void __exit a72_edac_driver_exit(void)
+{
+ platform_driver_unregister(&a72_edac_driver);
+}
+
+module_init(a72_edac_driver_init);
+module_exit(a72_edac_driver_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+MODULE_DESCRIPTION("Cortex A72 L1 and L2 cache EDAC driver");
--
2.49.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [v11 PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property
2025-05-29 3:00 [v11 PATCH 0/2] Add L1 and L2 error detection for A72 Vijay Balakrishna
2025-05-29 3:00 ` [v11 PATCH 1/2] EDAC: Add EDAC driver for ARM Cortex A72 cores Vijay Balakrishna
@ 2025-05-29 3:00 ` Vijay Balakrishna
2025-05-29 9:55 ` [v11 PATCH 0/2] Add L1 and L2 error detection for A72 Borislav Petkov
2 siblings, 0 replies; 6+ messages in thread
From: Vijay Balakrishna @ 2025-05-29 3:00 UTC (permalink / raw)
To: Borislav Petkov, Tony Luck, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: James Morse, Mauro Carvalho Chehab, Robert Richter, linux-edac,
linux-kernel, Tyler Hicks, Marc Zyngier, Sascha Hauer,
Lorenzo Pieralisi, devicetree, Vijay Balakrishna
From: Sascha Hauer <s.hauer@pengutronix.de>
Some ARM Cortex CPUs including A72 have Error Detection And
Correction (EDAC) support on their L1 and L2 caches. This is implemented
in implementation defined registers, so usage of this functionality is
not safe in virtualized environments or when EL3 already uses these
registers. This patch adds a edac-enabled flag which can be explicitly
set when EDAC can be used.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[vijayb: Added A72 to the commit message]
Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/arm/cpus.yaml | 50 +++++++++++++------
1 file changed, 34 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 2e666b2a4dcd..af884d51362d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -331,6 +331,12 @@ properties:
corresponding to the index of an SCMI performance domain provider, must be
"perf".
+ edac-enabled:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ A72 CPUs support Error Detection And Correction (EDAC) on their L1 and
+ L2 caches. This flag marks this function as usable.
+
qcom,saw:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
@@ -378,22 +384,34 @@ properties:
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
-if:
- # If the enable-method property contains one of those values
- properties:
- enable-method:
- contains:
- enum:
- - brcm,bcm11351-cpu-method
- - brcm,bcm23550
- - brcm,bcm-nsp-smp
- # and if enable-method is present
- required:
- - enable-method
-
-then:
- required:
- - secondary-boot-reg
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: arm,cortex-a72
+ then:
+ # Allow edac-enabled only for Cortex A72
+ properties:
+ edac-enabled: false
+
+ - if:
+ # If the enable-method property contains one of those values
+ properties:
+ enable-method:
+ contains:
+ enum:
+ - brcm,bcm11351-cpu-method
+ - brcm,bcm23550
+ - brcm,bcm-nsp-smp
+ # and if enable-method is present
+ required:
+ - enable-method
+
+ then:
+ required:
+ - secondary-boot-reg
required:
- device_type
--
2.49.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [v11 PATCH 0/2] Add L1 and L2 error detection for A72
2025-05-29 3:00 [v11 PATCH 0/2] Add L1 and L2 error detection for A72 Vijay Balakrishna
2025-05-29 3:00 ` [v11 PATCH 1/2] EDAC: Add EDAC driver for ARM Cortex A72 cores Vijay Balakrishna
2025-05-29 3:00 ` [v11 PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
@ 2025-05-29 9:55 ` Borislav Petkov
2025-06-27 16:49 ` Vijay Balakrishna
2 siblings, 1 reply; 6+ messages in thread
From: Borislav Petkov @ 2025-05-29 9:55 UTC (permalink / raw)
To: Vijay Balakrishna
Cc: Tony Luck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
James Morse, Mauro Carvalho Chehab, Robert Richter, linux-edac,
linux-kernel, Tyler Hicks, Marc Zyngier, Sascha Hauer,
Lorenzo Pieralisi, devicetree
On Wed, May 28, 2025 at 08:00:26PM -0700, Vijay Balakrishna wrote:
> Changes since v10:
> - edac_a72.c: copyright line add (Jonathan)
> - cpus.yaml: drop stale comment line (Krzysztof)
> - added "Reviewed-by" tags
It seems you're new to kernel development:
From: Documentation/process/submitting-patches.rst
"Don't get discouraged - or impatient
------------------------------------
After you have submitted your change, be patient and wait. Reviewers are
busy people and may not get to your patch right away.
Once upon a time, patches used to disappear into the void without comment,
but the development process works more smoothly than that now. You should
receive comments within a week or so; if that does not happen, make sure
that you have sent your patches to the right place. Wait for a minimum of
one week before resubmitting or pinging reviewers - possibly longer during
busy times like merge windows."
And we have a merge window right now.
Instead of sending patches every day, you should spend some time perusing the
documentation about how this all works:
https://kernel.org/doc/html/latest/process/development-process.html
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply [flat|nested] 6+ messages in thread