From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andi Kleen Subject: Re: Hardware Error Kernel Mini-Summit Date: Mon, 24 May 2010 20:31:20 +0200 Message-ID: <20100524183120.GC3429@gargoyle.fritz.box> References: <1274204560.17703.82.camel@Joe-Laptop.home> <20100518185305.GA23921@elte.hu> <987664A83D2D224EAE907B061CE93D53C61D1C57@orsmsx505.amr.corp.intel.com> <20100518191802.GG25224@aftab> <20100518222832.GJ22675@basil.fritz.box> <20100524155506.GA7145@sgi.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Tony Luck Cc: Russ Anderson , "Eric W. Biederman" , Borislav Petkov , Hidetoshi Seto , Mauro Carvalho Chehab , "Young, Brent" , Linux Kernel Mailing List , Ingo Molnar , Thomas Gleixner , Matt Domsch , Doug Thompson , Joe Perches , Ingo Molnar , "bluesmoke-devel@lists.sourceforge.net" , Linux Edac Mailing List List-Id: edac.vger.kernel.org On Mon, May 24, 2010 at 10:35:21AM -0700, Tony Luck wrote: > On Mon, May 24, 2010 at 8:55 AM, Russ Anderson wrote: > > ia64 had the Intel defined MCA Spec which defined the interaction > > between SAL and the kernel. =A0x86 does not have a similar well > > defined way of how errors should be handled. =A0It would be > > good to agree on how the errors should be handled. >=20 > X86 has machine check registers defined by the SDM. It also > has some f/w <-> OS interactions defined by the APEI sections > in the latest ACPI spec (chapter 17 of the 4.0a spec released > last month - see http://acpi.info). Some parts look cleaner than I should add the Intel Software Developer's manual has quite precise guidelines on what to do (and the Linux MCE code implements near all that faithfully)=20 The ACPI spec isn't quite as precise unfortunately. -Andi