[v6,3/7] EDAC, sb_edac: Assign EDAC memory controller per h/w controller

[Borislav Petkov <bp@alien8.de>]

On Tue, May 23, 2017 at 08:07:31AM +0800, Qiuxu Zhuo wrote:
> Tony pointed out that "currently the driver pretends there is
> one big 8-channel memory controller per socket instead of 2
> 4-channel controllers. This is fine with all memory controller
> populated with symmetrical DIMM configurations, but runs into
> difficulties on asymmetrical setups".
> 
> Restructure the driver to assign an EDAC memory controller to
> each real h/w memory controller to resolve the issue.
> 
> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> ---

Ontop:
---
From: Borislav Petkov <bp@suse.de>
Date: Thu, 25 May 2017 13:00:05 +0200
Subject: [PATCH] EDAC, sb_edac: Fix mod_name

It is called "sb_edac.c" now.

Signed-off-by: Borislav Petkov <bp@suse.de>
---
 drivers/edac/sb_edac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 2fe965aef1ae..f25a048549ac 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -3205,7 +3205,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
 		MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
 	mci->edac_ctl_cap = EDAC_FLAG_NONE;
 	mci->edac_cap = EDAC_FLAG_NONE;
-	mci->mod_name = "sbridge_edac.c";
+	mci->mod_name = "sb_edac.c";
 	mci->mod_ver = SBRIDGE_REVISION;
 	mci->dev_name = pci_name(pdev);
 	mci->ctl_page_to_phys = NULL;