[1/1] EDAC, sb_edac: Classify memory mirroring modes.

[Borislav Petkov <bp@alien8.de>]

On Thu, Jul 27, 2017 at 11:42:16PM +0800, Qiuxu Zhuo wrote:
> Basically there are full memory mirroring and address range partial
> memory mirroring(supported by Haswell EX and Broadwell EX) modes.
> 
> a) In full memory mirroring, the memory behind each memory controller
>    is mirrored, the memory is split into two identical mirrors (primary
>    and secondary), half of the memory is reserved for redundancy.
> 
> b) In address range partial memory mirroring, the memory size(range)
>    of primary and secondary behind each memory controller can be user
>    defined by the TAD0 register. The rest memory ranges defined by
>    TAD1/TAD2/... in that memory controller are non-mirrored.
> 
> For more detail mirroring, see the following link written by Tony Luck:
> https://01.org/lkp/blogs/tonyluck/2016/address-range-partial-memory-mirroring-linux
> 
> Currently the sb_edac driver only supports address decoding in full
> memory mirroring and non-mirroring modes. In address range partial memory
> mirroring mode, it may fail to decode address that falls in non-mirroring
> area (the following was one of this kind failed logs).
>   ---
>   mce: Uncorrected hardware memory error in user-access at 566d53a400
>   Memory failure: 0x566d53a: Killing einj_mem_uc:4647 due to hardware memory corruption
>   Memory failure: 0x566d53a: recovery action for dirty LRU page: Recovered
>   mce: [Hardware Error]: Machine check events logged
>   EDAC sbridge MC1: HANDLING MCE MEMORY ERROR
>   EDAC sbridge MC1: CPU 48: Machine Check Event: 0 Bank 7: ec00000000010090
>   EDAC sbridge MC1: TSC 4b914aa5a99dab
>   EDAC sbridge MC1: ADDR 566d53a400
>   EDAC sbridge MC1: MISC 1443a0c86
>   EDAC sbridge MC1: PROCESSOR 0:406f1 TIME 1499712764 SOCKET 2 APIC 80
>   EDAC MC1: 0 UE Can't discover the memory rank for ch addr 0x7fb54e900 on any memory ( page:0x0 offset:0x0 grain:32)
>   mce: [Hardware Error]: Machine check events logged
>   ---
> 
> This patch classifies memory mirroring modes, and makes the address decoding
> in address range partial memory mode correct.
> 
> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> ---
>  drivers/edac/sb_edac.c | 45 ++++++++++++++++++++++++++++++++-------------
>  1 file changed, 32 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
> index 80d860c..cae3a5b 100644
> --- a/drivers/edac/sb_edac.c
> +++ b/drivers/edac/sb_edac.c
> @@ -300,6 +300,12 @@ enum domain {
>  	SOCK,
>  };
>  
> +enum mirroring_mode {
> +	NON_MIRRORING,
> +	ADDR_RANGE_MIRRORING,
> +	FULL_MIRRORING,
> +};
> +
>  struct sbridge_pvt;
>  struct sbridge_info {
>  	enum type	type;
> @@ -377,8 +383,9 @@ struct sbridge_pvt {
>  	struct sbridge_channel	channel[NUM_CHANNELS];
>  
>  	/* Memory type detection */
> -	bool			is_mirrored, is_lockstep, is_close_pg;
> +	bool			is_cur_addr_mirrored, is_lockstep, is_close_pg;
>  	bool			is_chan_hash;
> +	enum mirroring_mode	mirroring_md;

Call that variable simply "mirror_mode"

>  	/* Memory description */
>  	u64			tolm, tohm;
> @@ -1648,10 +1655,6 @@ static int get_dimm_config(struct mem_ctl_info *mci)
>  	enum edac_type mode;
>  	u32 reg;
>  
> -	if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
> -		pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg);
> -		pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
> -	}
>  	pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
>  	edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
>  		 pvt->sbridge_dev->mc,
> @@ -1663,21 +1666,32 @@ static int get_dimm_config(struct mem_ctl_info *mci)
>  	 */
>  	if (pvt->info.type == KNIGHTS_LANDING) {
>  		mode = EDAC_S4ECD4ED;
> -		pvt->is_mirrored = false;
> +		pvt->mirroring_md = NON_MIRRORING;
> +		pvt->is_cur_addr_mirrored = false;
>  
>  		if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
>  			return -1;
>  		pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr);
>  	} else {
> +		if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
> +			pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg);

Error handling.

> +			pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
> +			if (GET_BITFIELD(reg, 28, 28)) {
> +				pvt->mirroring_md = ADDR_RANGE_MIRRORING;
> +				edac_dbg(0, "Address range partial memory mirroring is enabled\n");
> +				goto next;
> +			}
> +		}