From: Borislav Petkov <bp@alien8.de>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
Aristeu Rozanski <aris@redhat.com>,
Mauro Carvalho Chehab <mchehab@s-opensource.com>,
linux-edac@vger.kernel.org
Subject: [V2,2/2] x86/mce: Add macros for corrected error count bit field
Date: Wed, 26 Sep 2018 13:05:17 +0200 [thread overview]
Message-ID: <20180926110517.GC5584@zn.tnic> (raw)
On Mon, Sep 24, 2018 at 05:03:43PM -0700, Luck, Tony wrote:
> From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
>
> The bit field 52:38 of MCi_STATUS is for corrected error count.
> Add {*_SHIFT|*_MASK|*_CEC(c)} macros for the bit field.
>
> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
>
> V2: Just the CEC change. Vertical alignment of other fields fixed in part 1
>
> arch/x86/include/asm/mce.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> index 37b29e841757..a81a22e3592c 100644
> --- a/arch/x86/include/asm/mce.h
> +++ b/arch/x86/include/asm/mce.h
> @@ -39,6 +39,9 @@
> #define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
> #define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
> #define MCI_STATUS_AR BIT_ULL(55) /* Action required */
> +#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
> +#define MCI_STATUS_CEC_MASK 0x1fffc000000000ULL
GENMASK_ULL(52,38) right?
next reply other threads:[~2018-09-26 11:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-26 11:05 Borislav Petkov [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-09-26 18:25 [V2,2/2] x86/mce: Add macros for corrected error count bit field Luck, Tony
2018-09-25 0:03 Luck, Tony
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