From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E212BC0650F for ; Thu, 8 Aug 2019 07:50:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BD888218FC for ; Thu, 8 Aug 2019 07:50:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731031AbfHHHud (ORCPT ); Thu, 8 Aug 2019 03:50:33 -0400 Received: from verein.lst.de ([213.95.11.211]:44193 "EHLO verein.lst.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725796AbfHHHud (ORCPT ); Thu, 8 Aug 2019 03:50:33 -0400 Received: by verein.lst.de (Postfix, from userid 2407) id 32BFA68B02; Thu, 8 Aug 2019 09:50:30 +0200 (CEST) Date: Thu, 8 Aug 2019 09:50:29 +0200 From: Christoph Hellwig To: Paul Walmsley Cc: Christoph Hellwig , Greg KH , arnd@arndb.de, palmer@sifive.com, linux-kernel@vger.kernel.org, james.morse@arm.com, linux-riscv@lists.infradead.org, mchehab@kernel.org, linux-edac@vger.kernel.org Subject: Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc Message-ID: <20190808075029.GB30308@lst.de> References: <20190807151009.31971-1-hch@lst.de> <20190807152215.GA26690@kroah.com> <20190807152438.GA16495@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote: > On Wed, 7 Aug 2019, Christoph Hellwig wrote: > > > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > > > Signed-off-by: Christoph Hellwig > > > > --- > > > > arch/riscv/mm/Makefile | 1 - > > > > drivers/misc/Makefile | 1 + > > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > > > 3 files changed, 1 insertion(+), 1 deletion(-) > > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > > > > > Why isn't this in drivers/edac/ ? > > > why is this a misc driver? Seems like it should sit next to the edac > > > stuff. > > > > No idea. EDAC maintainers, would you object to taking what is > > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? > > If this driver is moved out of arch/riscv/mm, it should ideally go into > some sort of common L2 cache controller driver directory, along > with other L2 cache controller drivers like arch/arm/mm/*l2c*. > > Like many L2 cache controllers, this controller also supports cache > flushing operations and SoC-specific way operations. We just don't use > those on RISC-V - yet. Well, another reason to not have it under arch/riscv/ as it is a SOC specific driver, which we all have somewhere else, just like arm64 and new arm ports do. And especially not unconditionally built.