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Peter Anvin" , x86@kernel.org, linux-edac@vger.kernel.org Subject: [PATCH] x86/mce: Enable HSD131, HSM142, HSW131, BDM48, and HSM142 Date: Wed, 5 Feb 2020 07:58:31 -0500 Message-Id: <20200205125831.20430-1-prarit@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Content-Transfer-Encoding: quoted-printable Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Intel Errata HSD131, HSM142, HSW131, and BDM48 report that "spurious corrected errors may be logged in the IA32_MC0_STATUS register with the valid field (bit 63) set, the uncorrected error field (bit 61) not set, a Model Specific Error Code (bits [31:16]) of 0x000F, and an MCA Error Code (bits [15:0]) of 0x0005." Block these spurious errors from the console and logs. Links to Intel Specification updates: HSD131: https://www.intel.com/content/www/us/en/products/docs/processors/= core/4th-gen-core-family-desktop-specification-update.html HSM142: https://www.intel.com/content/www/us/en/products/docs/processors/= core/4th-gen-core-family-mobile-specification-update.html HSW131: https://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1= 200v3-spec-update.html BDM48: https://www.intel.com/content/www/us/en/products/docs/processors/c= ore/5th-gen-core-family-spec-update.html Signed-off-by: Alexander Krupp Signed-off-by: Prarit Bhargava Cc: Tony Luck Cc: Borislav Petkov Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: linux-edac@vger.kernel.org --- arch/x86/kernel/cpu/mce/core.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/cor= e.c index 2c4f949611e4..d893cc764a06 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -121,6 +121,8 @@ static struct irq_work mce_irq_work; =20 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs = *regs); =20 +static int (*quirk_noprint)(struct mce *m); + /* * CPU/chipset specific EDAC code can register a notifier call here to p= rint * MCE errors in a human-readable form. @@ -232,6 +234,9 @@ struct mca_msr_regs msr_ops =3D { =20 static void __print_mce(struct mce *m) { + if (quirk_noprint && quirk_noprint(m)) + return; + pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", m->extcpu, (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), @@ -1622,6 +1627,15 @@ static void quirk_sandybridge_ifu(int bank, struct= mce *m, struct pt_regs *regs) m->cs =3D regs->cs; } =20 +static int quirk_spurious_ce_noprint(struct mce *m) +{ + if (m->bank =3D=3D 0 && + (m->status & 0xa0000000ffffffff) =3D=3D 0x80000000000f0005) + return 1; + + return 0; +} + /* Add per CPU specific workarounds here */ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { @@ -1696,6 +1710,13 @@ static int __mcheck_cpu_apply_quirks(struct cpuinf= o_x86 *c) =20 if (c->x86 =3D=3D 6 && c->x86_model =3D=3D 45) quirk_no_way_out =3D quirk_sandybridge_ifu; + + if ((c->x86 =3D=3D 6) && + ((c->x86_model =3D=3D 0x3c) || (c->x86_model =3D=3D 0x3d) || + (c->x86_model =3D=3D 0x45) || (c->x86_model =3D=3D 46))) { + pr_info("MCE errata HSD131, HSM142, HSW131, BDM48, or HSM142 enabled.= \n"); + quirk_noprint =3D quirk_spurious_ce_noprint; + } } =20 if (c->x86_vendor =3D=3D X86_VENDOR_ZHAOXIN) { --=20 2.21.1