[PATCH v3 0/2] Add EDAC support for Cadence ddr controller

[Dhananjay Kangude <dkangude@cadence.com>]

These patches add new edac driver for Cadence ddr memory controller.
Cadence controller detects single(CE) and double(UE) bit errors during
memory operations(RMW). DDR controller raised the interrupt on detection
of the ecc error event and fill the data into registers. Driver handle
the interrupt event and notify edac subsystem about ecc errors.

Changes since v3:
=================
- Corrected YAML file location

Changes since v2:
=================
- Added minor fixes to YAML file
- Split ISR into two differnt functions
- Removed unused paramters
- Fixed indentation issues
- Improved code readabilty
- Checked return value for edac_get_dimm
- Modified quirks as a ip_features

Changes since v1:
=================
- Made predefined arrays as static
 Fixes: 201447a5db9b ("EDAC/Cadence:Add EDAC driver for cadence memory controller")
- Replace macro 'EDAC_DIMM_PTR' with newly introduce function
- Removed unused variable root

Dhananjay Kangude (2):
  dt-bindings: edac: Add cadence ddr mc support
  EDAC/Cadence:Add EDAC driver for cadence memory controller

 .../devicetree/bindings/edac/cdns,ddr-edac.yaml    |   47 ++
 drivers/edac/Kconfig                               |    8 +
 drivers/edac/cadence_edac.c                        |  641 ++++++++++++++++++++
 3 files changed, 696 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
 create mode 100644 drivers/edac/cadence_edac.c