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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT047.mail.protection.outlook.com (10.13.177.220) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5017.22 via Frontend Transport; Mon, 28 Feb 2022 16:14:28 +0000 Received: from milan-ETHANOL-X.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Mon, 28 Feb 2022 10:14:26 -0600 From: Naveen Krishna Chatradhi To: CC: , , , , Muralidhara M K , "Naveen Krishna Chatradhi" Subject: [PATCH 04/14] EDAC/amd64: Add determine_memory_type() into pvt->ops Date: Mon, 28 Feb 2022 21:43:44 +0530 Message-ID: <20220228161354.54923-5-nchatrad@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220228161354.54923-1-nchatrad@amd.com> References: <20220228161354.54923-1-nchatrad@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4b1aad82-b7ad-4e70-bd9e-08d9fad56596 X-MS-TrafficTypeDiagnostic: MN0PR12MB5980:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:28.8366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b1aad82-b7ad-4e70-bd9e-08d9fad56596 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5980 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for determine_memory_type() in pvt->ops and assign family specific determine_memory_type() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 33 ++++++++++++++++++++------------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 708c4bbc0d1c..07428a6c7683 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1632,20 +1632,10 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) } } -static void determine_memory_type(struct amd64_pvt *pvt) +static void f1x_determine_memory_type(struct amd64_pvt *pvt) { u32 dram_ctrl, dcsm; - if (pvt->umc) { - if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) - pvt->dram_type = MEM_LRDDR4; - else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) - pvt->dram_type = MEM_RDDR4; - else - pvt->dram_type = MEM_DDR4; - return; - } - switch (pvt->fam) { case 0xf: if (pvt->ext_model >= K8_REV_F) @@ -1701,6 +1691,16 @@ static void determine_memory_type(struct amd64_pvt *pvt) pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; } +static void f17_determine_memory_type(struct amd64_pvt *pvt) +{ + if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) + pvt->dram_type = MEM_LRDDR4; + else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) + pvt->dram_type = MEM_RDDR4; + else + pvt->dram_type = MEM_DDR4; +} + /* Get the number of DCT channels the memory controller is using. */ static int k8_early_channel_count(struct amd64_pvt *pvt) { @@ -3309,7 +3309,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) pvt->ops->get_base_mask(pvt); - determine_memory_type(pvt); + pvt->ops->determine_memory_type(pvt); edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); determine_ecc_sym_sz(pvt); @@ -3785,6 +3785,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = k8_prep_chip_selects; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x10: @@ -3796,6 +3797,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x15: @@ -3823,6 +3825,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->early_channel_count = f1x_early_channel_count; pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->get_base_mask = read_dct_base_mask; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x16: @@ -3840,6 +3843,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f16_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x17: @@ -3871,6 +3875,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; + pvt->ops->determine_memory_type = f17_determine_memory_type; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3908,6 +3913,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; + pvt->ops->determine_memory_type = f17_determine_memory_type; break; default: @@ -3917,7 +3923,8 @@ static int per_family_init(struct amd64_pvt *pvt) /* ops required for all the families */ if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || - !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects) { + !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || + !pvt->ops->determine_memory_type) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index cca59a1b3021..4d8830b8afa2 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -466,6 +466,7 @@ struct low_ops { unsigned int cs_mode, int cs_mask_nr); void (*get_base_mask)(struct amd64_pvt *pvt); void (*prep_chip_selects)(struct amd64_pvt *pvt); + void (*determine_memory_type)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, -- 2.25.1