public inbox for linux-edac@vger.kernel.org
 help / color / mirror / Atom feed
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Andrew Halaney <ahalaney@redhat.com>,
	andersson@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, bp@alien8.de,
	tony.luck@intel.com, quic_saipraka@quicinc.com,
	konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, james.morse@arm.com,
	mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org,
	quic_ppareek@quicinc.com, luca.weiss@fairphone.com
Subject: Re: [PATCH v2 00/13] Qcom: LLCC/EDAC: Fix base address used for LLCC banks
Date: Tue, 13 Dec 2022 23:27:38 +0530	[thread overview]
Message-ID: <20221213175738.GI4862@thinkpad> (raw)
In-Reply-To: <ec64e3a0-085d-7830-fd4e-6969c1c9bbdf@linaro.org>

On Tue, Dec 13, 2022 at 05:54:56PM +0100, Krzysztof Kozlowski wrote:
> On 13/12/2022 06:28, Manivannan Sadhasivam wrote:
> > On Mon, Dec 12, 2022 at 01:23:40PM -0600, Andrew Halaney wrote:
> >> On Mon, Dec 12, 2022 at 06:02:58PM +0530, Manivannan Sadhasivam wrote:
> >>> The Qualcomm LLCC/EDAC drivers were using a fixed register stride for
> >>> accessing the (Control and Status Regsiters) CSRs of each LLCC bank.
> >>> This offset only works for some SoCs like SDM845 for which driver support
> >>> was initially added.
> >>>
> >>> But the later SoCs use different register stride that vary between the
> >>> banks with holes in-between. So it is not possible to use a single register
> >>> stride for accessing the CSRs of each bank. By doing so could result in a
> >>> crash with the current drivers. So far this crash is not reported since
> >>> EDAC_QCOM driver is not enabled in ARM64 defconfig and no one tested the
> >>> driver extensively by triggering the EDAC IRQ (that's where each bank
> >>> CSRs are accessed).
> >>>
> >>> For fixing this issue, let's obtain the base address of each LLCC bank from
> >>> devicetree and get rid of the fixed stride.
> >>>
> >>> This series affects multiple platforms but I have only tested this on
> >>> SM8250 and SM8450. Testing on other platforms is welcomed.
> >>>
> >>
> >> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8540p-ride
> >>
> > 
> > Thanks!
> > 
> >> I took this for a quick spin on the qdrive3 I've got access to without
> >> any issue:
> >>
> >>     [root@localhost ~]# modprobe qcom_edac
> >>     [root@localhost ~]# dmesg | grep -i edac
> >>     [    0.620723] EDAC MC: Ver: 3.0.0
> >>     [    1.165417] ghes_edac: GHES probing device list is empty
> >>     [  594.688103] EDAC DEVICE0: Giving out device to module qcom_llcc_edac controller llcc: DEV qcom_llcc_edac (INTERRUPT)
> >>     [root@localhost ~]# cat /proc/interrupts | grep ecc
> >>     174:          0          0          0          0          0          0          0          0     GICv3 614 Level     llcc_ecc
> >>     [root@localhost ~]#
> >>
> >> Potentially stupid question, but are users expected to manually load the
> >> driver as I did? I don't see how it would be loaded automatically in the
> >> current state, but thought it was funny that I needed to modprobe
> >> myself.
> >>
> >> Please let me know if you want me to do any more further testing!
> >>
> > 
> > Well, I always ended up using the driver as a built-in. I do make it module for
> > build test but never really used it as a module, so didn't catch this issue.
> > 
> > This is due to the module alias not exported by the qcom_edac driver. Below
> > diff allows kernel to autoload it:
> > 
> > diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> > index f7afb5375293..13919d01c22d 100644
> > --- a/drivers/edac/qcom_edac.c
> > +++ b/drivers/edac/qcom_edac.c
> > @@ -419,3 +419,4 @@ module_platform_driver(qcom_llcc_edac_driver);
> >  
> >  MODULE_DESCRIPTION("QCOM EDAC driver");
> >  MODULE_LICENSE("GPL v2");
> > +MODULE_ALIAS("platform:qcom_llcc_edac");
> 
> While this is a way to fix it, but instead of creating aliases for wrong
> names, either a correct name should be used or driver should receive ID
> table.
> 

I'm not sure how you'd fix it with a _correct_ name here. Also, the id table is
an overkill since there is only one driver that is making use of it. And
moreover, there is no definite ID to use.

Thanks,
Mani

> Best regards,
> Krzysztof
> 

-- 
மணிவண்ணன் சதாசிவம்

  reply	other threads:[~2022-12-13 17:57 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-12 12:32 [PATCH v2 00/13] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Manivannan Sadhasivam
2022-12-12 12:32 ` [PATCH v2 01/13] dt-bindings: arm: msm: Update the maintainers for LLCC Manivannan Sadhasivam
2022-12-13 16:20   ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 02/13] dt-bindings: arm: msm: Fix register regions used for LLCC banks Manivannan Sadhasivam
2022-12-13 16:24   ` Krzysztof Kozlowski
2022-12-13 17:30     ` Manivannan Sadhasivam
2022-12-13 18:34       ` Krzysztof Kozlowski
2022-12-13 16:28   ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 03/13] arm64: dts: qcom: sdm845: Fix the base addresses of " Manivannan Sadhasivam
2022-12-13  5:04   ` Sai Prakash Ranjan
2022-12-13 16:27   ` Krzysztof Kozlowski
2022-12-13 17:13     ` Manivannan Sadhasivam
2022-12-13 18:37       ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 04/13] arm64: dts: qcom: sc7180: Remove reg-names property from LLCC node Manivannan Sadhasivam
2022-12-13  5:05   ` Sai Prakash Ranjan
2022-12-13 16:30   ` Krzysztof Kozlowski
2022-12-13 17:16     ` Manivannan Sadhasivam
2022-12-12 12:33 ` [PATCH v2 05/13] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Manivannan Sadhasivam
2022-12-13  5:06   ` Sai Prakash Ranjan
2022-12-13 16:30   ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 06/13] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2022-12-13  5:06   ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 07/13] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2022-12-13  5:07   ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 08/13] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2022-12-13  5:07   ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 09/13] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2022-12-13  5:08   ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 10/13] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2022-12-13  5:08   ` Sai Prakash Ranjan
2022-12-12 12:33 ` [PATCH v2 11/13] arm64: dts: qcom: sm6350: Remove reg-names property from LLCC node Manivannan Sadhasivam
2022-12-13  5:09   ` Sai Prakash Ranjan
2022-12-13 16:31   ` Krzysztof Kozlowski
2022-12-13 17:17     ` Manivannan Sadhasivam
2022-12-12 12:33 ` [PATCH v2 12/13] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Manivannan Sadhasivam
2022-12-13 16:37   ` Krzysztof Kozlowski
2022-12-13 17:44     ` Manivannan Sadhasivam
2022-12-13 18:44       ` Krzysztof Kozlowski
2022-12-12 12:33 ` [PATCH v2 13/13] qcom: llcc/edac: Support polling mode for ECC handling Manivannan Sadhasivam
2022-12-12 15:53   ` Luca Weiss
2022-12-12 16:16     ` Manivannan Sadhasivam
2022-12-12 19:23 ` [PATCH v2 00/13] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Andrew Halaney
2022-12-13  5:28   ` Manivannan Sadhasivam
2022-12-13 16:17     ` Andrew Halaney
2022-12-13 16:54     ` Krzysztof Kozlowski
2022-12-13 17:57       ` Manivannan Sadhasivam [this message]
2022-12-13 18:47         ` Krzysztof Kozlowski
2022-12-19 13:50           ` Manivannan Sadhasivam
2022-12-19 14:11             ` Krzysztof Kozlowski
2022-12-19 14:16               ` Manivannan Sadhasivam
2022-12-19 14:21                 ` Krzysztof Kozlowski
2022-12-19 16:49                 ` Dmitry Baryshkov
2022-12-19 17:31                   ` Manivannan Sadhasivam
2022-12-19 18:31   ` Manivannan Sadhasivam

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221213175738.GI4862@thinkpad \
    --to=manivannan.sadhasivam@linaro.org \
    --cc=ahalaney@redhat.com \
    --cc=andersson@kernel.org \
    --cc=bp@alien8.de \
    --cc=james.morse@arm.com \
    --cc=konrad.dybcio@linaro.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-edac@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=luca.weiss@fairphone.com \
    --cc=mchehab@kernel.org \
    --cc=quic_ppareek@quicinc.com \
    --cc=quic_saipraka@quicinc.com \
    --cc=robh+dt@kernel.org \
    --cc=rric@kernel.org \
    --cc=tony.luck@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox