[PATCH v4 02/13] dt-bindings: memory: Add BT1 DDRC DT-schema

Serge Semin
2023-09-20T19:57:42Z

Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
are individual IRQs for each ECC and DFI events. The dedicated scrubber
clock source is absent since it's fully synchronous to the core clock.

Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v2:
- Keep the alphabetically ordered compatible strings list. (@Krzysztof)
- Fix grammar nitpicks in the patch log. (@Krzysztof)
- Drop the PHY CSR region. (@Rob)
- Move the device bindings to the separate DT-schema.
---
.../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml
new file mode 100644
index 000000000000..80353a0a676f
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-ddrc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 DDR Controller
+
+maintainers:
+ - Serge Semin <fancer.lancer@gmail.com>
+
+description:
+ Baikal-T1 DDRC is based on the DW uMCTL2 DDRC IP-core v2.51a with DDR2
+ and DDR3 protocol capability, 32-bit data bus + 8-bit ECC + up to 2
+ SDRAM ranks. There are individual IRQs for each ECC and DFI events.
+ The dedicated scrubber clock source is absent since it's fully
+ synchronous to the core clock.
+
+allOf:
+ - $ref: /schemas/memory-controllers/snps,dw-umctl2-common.yaml#
+
+properties:
+ compatible:
+ const: baikal,bt1-ddrc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 4
+
+ interrupt-names:
+ items:
+ - const: dfi_e
+ - const: ecc_ce
+ - const: ecc_ue
+ - const: ecc_sbr
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: aclk
+ - const: core
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: arst
+ - const: core
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ #include <dt-bindings/clock/bt1-ccu.h>
+ #include <dt-bindings/reset/bt1-ccu.h>
+
+ memory-controller@1f042000 {
+ compatible = "baikal,bt1-ddrc";
+ reg = <0x1f042000 0x1000>;
+
+ interrupts = <GIC_SHARED 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dfi_e", "ecc_ce", "ecc_ue", "ecc_sbr";
+
+ clocks = <&ccu_sys CCU_SYS_APB_CLK>,
+ <&ccu_axi CCU_AXI_DDR_CLK>,
+ <&ccu_pll CCU_DDR_PLL>;
+ clock-names = "pclk", "aclk", "core";
+
+ resets = <&ccu_axi CCU_AXI_DDR_RST>,
+ <&ccu_sys CCU_SYS_DDR_INIT_RST>;
+ reset-names = "arst", "core";
+ };
+...
--
2.41.0