Re: [PATCH 07/13] rasdaemon: cxl: Update CXL DRAM event to CXL spec rev 3.1

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Wed, 20 Nov 2024 09:59:17 +0000
<shiju.jose@huawei.com> wrote:

> From: Shiju Jose <shiju.jose@huawei.com>
> 
> CXL spec 3.1 section 8.2.9.2.1.2 Table 8-46, DRAM Event Record has updated
> with following new fields and new types for Memory Event Type, Transaction
> Type and Validity Flags fields.
> 1. Component Identifier
> 2. Sub-channel
> 3. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 4. Corrected Memory Error Count at Event
> 5. Memory Event Sub-Type
> 
> Update the parsing, logging and recording of DRAM event for the above
> spec rev 3.1 changes.
> 
> Example rasdaemon log for CXL DRAM event,
> 
> cxl_dram 2024-11-20 00:18:53 +0000 memdev:mem0 host:0000:0f:00.0 serial:0x3 \
> log type:Informational hdr_uuid:601dcbb3-9c06-4eab-b8af-4e9bfb5c9624 \
> hdr_handle:0x1 hdr_related_handle:0x0 hdr_timestamp:1970-01-01 00:00:58 +0000 \
> hdr_length:128 hdr_maint_op_class:1 hdr_maint_op_sub_class:3 dpa:0x18680 \
> dpa_flags:descriptor:'UNCORRECTABLE EVENT' 'THRESHOLD EVENT' \
> memory_event_type:Data Path Error memory_event_sub_type:Media Link CRC Error \
> transaction_type:Internal Media Scrub hpa:0xffffffffffffffff region: \
> region_uuid:00000000-0000-0000-0000-000000000000 channel:3 rank:17 \
> nibble_mask:3866802 bank_group:7 bank:11 row:2 column:77
> correction_mask:21 00 00 00 00 00 00 00 2c 00 00 00 00 00 00 00 37 00 00 \
> 00 00 00 00 00 42 00 00 00 00 00 00 00 comp_id:01 74 c5 08 9a 1a 0b fc d2 \
> 7e 2f 31 9b 3c 81 4d comp_id_pldm_valid_flags:'PLDM Entity ID' \
> PLDM Entity ID:74 c5 08 9a 1a 0b \
> Advanced Programmable CME threshold Event Flags:'Corrected Memory Errors \
> in Multiple Media Components' 'Exceeded Programmable Threshold' \
> CVME Count:0x94
> 
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Also LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>