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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?T8OJJGAoK3JhnLyQIWtmEEGk+BRKZNByrMJWIdq7GQPWtxJ9GjZQYB5Kg7Sy?= =?us-ascii?Q?KCRbLPN6HrMNXgpRPwU+9OsqO1fU+W2TtBGepvWlU2GPmhATu172wKPGHfbC?= =?us-ascii?Q?p39JZe2E+w9aJ3n/JrTcZEX+WlxBQyl7HikstNdWn6MmYSnLMCdG7HMY8Sqs?= =?us-ascii?Q?t1XCdkZ/qjuuqUJ32PBl7cYx8tgfbiyE0wmEuEJytCf5juzeNMSB1/FSEyNo?= =?us-ascii?Q?cySnorgAh9DWAfDgV34yX/l/4BUuh7IFwHAg6Nr9YlJPsjk2XTC7D/dgvDn3?= =?us-ascii?Q?mz23GeaCaKq0hK50XfGXV9LBoyFTbWkznAUznpS4EQVA54VxH5INWSVTBfsf?= =?us-ascii?Q?4ugNz9kUNHXVfpZ8GVBWwRXTleFdjvimrWzg/8SwvtICc1M9Bxpw5FiitGqO?= =?us-ascii?Q?0UjGtpWZD5MKCV2gaB4YPCcGJyN7EAWpiRLfJ1W5H6ohz3MQJCpO/2sXTwGF?= =?us-ascii?Q?QNfC0QV9CaZzPA35ZixJB05R8M5a3W8WLbOgu9n9eblhysfKqv4TT6W4NO4i?= =?us-ascii?Q?GklLgnF7W4lEjx1Li2PXvbXVbF9AcLkywgIZJ1IJU+Ju9u+RsKz+eeVhHZdg?= =?us-ascii?Q?CXm2yLY9ke9hyFQPoKn1Ej2y+VTKG3XDIw6DnmgAgrp/EG+ELvb9VFeKxb2R?= =?us-ascii?Q?7IKX3MNK8eoEYaCrJ0DPi1uRpOGM2VUQdWTW+4N+7S7Ek1bxe5UI7b9vjEDG?= =?us-ascii?Q?0uuSVbqiP4JIUkiMmtKXAX66NL8v6UUoXVmgLNf7UQS7Eckh/o/tRryviFAd?= =?us-ascii?Q?ev0K3JbhZZVhgYCjrUmn8wlyV+iWnyldFKl94EjrXvtnA2xCbRfyx4NOzIPy?= =?us-ascii?Q?Hu1xxnARbYCPPuU/Lzsi5c1HOski/PqSEUKYNXbXQLpcVg08ShHYY1RbChlt?= =?us-ascii?Q?6bV7JRZ6Yjoy98gUZ9AqSr2I2TLyQndLK5wuk8jHPEt//FXMy7PODpoRS+PG?= =?us-ascii?Q?Lkk8D7A3qLDCIa/SCcpOA4AE2Q9UAap4pShMZMkIXDzfSHbRG3vI76cDI7t2?= =?us-ascii?Q?PK96PiIOyX+bzjc8+RtPIRT3op+NDA9GfEGyXnCnqbwDsXlqeuhizOy/hSTn?= =?us-ascii?Q?wxw5/vxFADOfzUfHGsLpATXlFTG7/mOk8zrFZXcwdHUeGD5yo5jf2aeFBjVi?= =?us-ascii?Q?/MjJg6SJ+1HTfpV83moT2z4cdZZGLKdAZwmhPZipKETIcD26KPvood8Z0/WQ?= =?us-ascii?Q?OgipZHIGld6xhH2XIcfIcPZB1fVgInKYRnJONpYwNopPqxJeWZ+jxCJWZ0VL?= =?us-ascii?Q?euO8vXdX2mLDzJWVdbDUQwKz7KvhXTDZGr7ehcufI26VwmHzxQZQ0CDFehOF?= =?us-ascii?Q?gHWPJoNWtMj6zkznRcJxcK1Ib/bc+DcW+cYQVk/ctz/nYkbHJ2GmlUDX/9V8?= =?us-ascii?Q?gv78EqrUVlJrJqOghzyXjcjeV0xxUHbO7YntUbH63ER2WDNkGVx1qIK6f6FT?= =?us-ascii?Q?CvAwfcFuL9P8kLGR43YJyolby7IODm0tMzP5+70X5/D5GMdNrKOYcyCUZsMD?= =?us-ascii?Q?PVUaQr12HFj/3wPz0Bo50m8FBaKaM4w6s8JEOt7KEowCHxeBLkZIyzD2Qqbm?= =?us-ascii?Q?BN+1PvbBjOVwigxlLhqDYLdCMuxWF6VqZ/ISrHO7?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 167f9af3-1c5c-49ad-0451-08dd5100d173 X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2025 16:16:51.4277 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZVZ1/MPoOhAc5bBjvcSrUh3J2gvYmiGjA2gLNO3Am4XuhpdX2QhjmLqhqvQKeze9D0g0EeuTNnRnpk6zRrSLjg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6650 On Tue, Feb 18, 2025 at 08:23:22AM +0000, Zhuo, Qiuxu wrote: > > From: Yazen Ghannam > > [...] > > behavior. The deferred error interrupt is technically advertised by the SUCCOR > > feature. However, this was first made available on SMCA systems. > > Therefore, only set up the deferred error interrupt on SMCA systems and > > simplify the code. > > Does this description imply that: > > if mce_flags.succor = true, then mce_flags.smca must also be true. > No, they are independent features. However, in practice (on production systems) SMCA systems also support SUCCOR. > > > > Signed-off-by: Yazen Ghannam > > [...] > > -static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) -{ > > - u32 low = 0, high = 0; > > - int def_offset = -1, def_new; > > - > > - if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) > > - return; > > - > > - def_new = (low & MASK_DEF_LVTOFF) >> 4; > > - if (!(low & MASK_DEF_LVTOFF)) { > > - pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for > > deferred error IRQs correctly.\n"); > > - def_new = DEF_LVT_OFF; > > - low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); > > - } > > This code is missing from this patch. > Expected? > Yes, this old code is replaced by smca_enable_interrupt_vectors(). > > - > > - def_offset = setup_APIC_deferred_error(def_offset, def_new); > > - if ((def_offset == def_new) && > > - (deferred_error_int_vector != amd_deferred_error_interrupt)) > > - deferred_error_int_vector = amd_deferred_error_interrupt; > > - > > - if (!mce_flags.smca) > > - low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; > > - > > - wrmsr(MSR_CU_DEF_ERR, low, high); > > -} > > - > > This code is missing from this patch. > Expected? > Yes, same as above. > > static u32 smca_get_block_address(unsigned int bank, unsigned int block, > > unsigned int cpu) > > { > > @@ -551,7 +516,6 @@ prepare_threshold_block(unsigned int bank, unsigned > > int block, u32 addr, > > int offset, u32 misc_high) > > { > > unsigned int cpu = smp_processor_id(); > > - u32 smca_low, smca_high; > > struct threshold_block b; > > int new; > > > > @@ -571,18 +535,10 @@ prepare_threshold_block(unsigned int bank, > > unsigned int block, u32 addr, > > __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks); > > b.interrupt_enable = 1; > > > > - if (!mce_flags.smca) { > > - new = (misc_high & MASK_LVTOFF_HI) >> 20; > > - goto set_offset; > > - } > > - > > - /* Gather LVT offset for thresholding: */ > > - if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) > > - goto out; > > - > > - new = (smca_low & SMCA_THR_LVT_OFF) >> 12; > > + if (mce_flags.smca) > > + goto done; > > > > -set_offset: > > + new = (misc_high & MASK_LVTOFF_HI) >> 20; > > offset = setup_APIC_mce_threshold(offset, new); > > if (offset == new) > > thresholding_irq_en = true; > > @@ -590,7 +546,6 @@ prepare_threshold_block(unsigned int bank, unsigned > > int block, u32 addr, > > done: > > mce_threshold_block_init(&b, offset); > > > > -out: > > return offset; > > } > > > > @@ -659,6 +614,32 @@ static void disable_err_thresholding(struct > > cpuinfo_x86 *c, unsigned int bank) > > wrmsrl(MSR_K7_HWCR, hwcr); > > } > > > > +/* > > + * Enable the APIC LVT interrupt vectors once per-CPU. This should be > > +done before hardware is > > + * ready to send interrupts. > > + * > > + * Individual error sources are enabled later during per-bank init. > > + */ > > +static void smca_enable_interrupt_vectors(void) > > +{ > > + struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data); > > + u64 mca_intr_cfg, offset; > > + > > + if (!mce_flags.smca || !mce_flags.succor) > > + return; > > + > > In the old code, the deferred IRQ setup just depends on mce_flags.succor, > But now it depends on: mce_flags.smca && mce_flags.succor. > Is this expected? > Yes, this is described in the quoted part of the commit message above. > > + if (rdmsrl_safe(MSR_CU_DEF_ERR, &mca_intr_cfg)) > > + return; > > + > > + offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; > > + if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, > > APIC_EILVT_MSG_FIX, 0)) > > + data->thr_intr_en = true; > > + > > + offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; > > + if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, > > APIC_EILVT_MSG_FIX, 0)) > > + data->dfr_intr_en = true; > > +} > > + > > static void amd_apply_quirks(struct cpuinfo_x86 *c) { > > struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); @@ > > -690,11 +671,16 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) > > > > amd_apply_quirks(c); > > mce_flags.amd_threshold = 1; > > + smca_enable_interrupt_vectors(); > > > > for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { > > - if (mce_flags.smca) > > + if (mce_flags.smca) { > > smca_configure(bank, cpu); > > > > + if (!this_cpu_ptr(&mce_amd_data)->thr_intr_en) > > + continue; > > + } > > + > > disable_err_thresholding(c, bank); > > > > for (block = 0; block < NR_BLOCKS; ++block) { @@ -715,9 > > +701,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) > > offset = prepare_threshold_block(bank, block, > > address, offset, high); > > } > > } > > - > > - if (mce_flags.succor) > > - deferred_error_interrupt_enable(c); > > The old code to set up deferred error IRQ just depends on mce_flags.succor, > > [...] Correct, this is the same reasoning as above. Thanks, Yazen