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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?vwb1bJWF48wG6Fz9oh3OKkd8S/PsRH00bXQzOkoqmhWn1hQY02XEYPDbZV/F?= =?us-ascii?Q?AQei9pe7sxheCzj9pZHwVv79jJeLqYzxokeuDHUqKmGRbm/vJqNZTOuAdqWZ?= =?us-ascii?Q?qWBchDX1v6K/AjitdxbpG9awMmv21w4vC9FDuQNrOoIqd7OvFtvT/LAlqx5i?= =?us-ascii?Q?Y7Hb2mXby+ljg1732x8LGlSOHs8zEYhF9CUTh11U2GkswaYyJM2v0vt0SKxI?= =?us-ascii?Q?mUXGe/wJyrHhi2tY71rxC6PJMoeI2YsfsMWPml06mHTCZki2ouh8qKc6nWd5?= =?us-ascii?Q?g0UyZBExxCVemzmEl5qH9OnfrdHMYrTBYDSFii1dourAjZ4g2OzdWLxFqTWH?= =?us-ascii?Q?wE6xEDacZ/shnMROjOoz0zAG/hivvQfLDsMZWF+Rfnjjf5aHuPuf4mO0/bOv?= =?us-ascii?Q?7oKDARiTdk1TT+iuwbroa3ZnRNhY4T8iPCxagFBpq3b2DU1G68C+gfjTI4jb?= =?us-ascii?Q?JL8tX53Ea63S/ZRg+8Sy4AqDEYxaYz+2/olPPFSid/f5K0/Dcyv8GICVfh4e?= =?us-ascii?Q?K6R/no8NsuGJS7EwFFi/jj2S3wqkFQMU+4bMkpu34+uO4APukXpXJMx/Bk0H?= =?us-ascii?Q?DzoFeJePTnPr8MRJyFbW87sSMQ28QARJpLSwtmUU0QGzGOpXgs7YsQZvQJWa?= =?us-ascii?Q?cZ50DI2T0PPpzBgLTn6gADSr17J99CeRn8XTG/E+UDSvYpDzRpnTkMAd/fs5?= =?us-ascii?Q?ZnGViiqFtVCqN1Tr78bdHPZy3Z96LHQs92/SAcyrcPZk2NeBSQfe0y6rCfWh?= =?us-ascii?Q?/pTdmiF8WNZWTXk0m8UcLsbOPvaUd6gu2hzoMH4JKgupTECIFDDz4EomJchC?= =?us-ascii?Q?zDDBKUC9753x2rRs8j3Rf7PO6y0N6TIepm+HSnblkSE0JYCwri6hXEsnsa25?= =?us-ascii?Q?mi3bmJ/cKbYKbd1crWs9Sa4+11Ck6YNBPpsA5xmfYKfC6pA+yS+vZCOuPnDy?= =?us-ascii?Q?b7W/HCjjVUHcXTK6bQPUM/oorYSSa6dE/XKl1aVNZnxRqdvqEKrPyiErKBW+?= =?us-ascii?Q?QdhtTvAoeUmF9m/IpMGgZErUOfE/UnIrT9VNN6iNOWCTnaby2006XiL5u/iD?= =?us-ascii?Q?NuOt86A2WkliTNQxzZvtESib+vtpZOdFHcVV4139ZddSeIHfVM83lHq13sNj?= =?us-ascii?Q?GeM0RQVuuDU43InTNLqrQIKjhoXIUEu5OwrQWp2QiVqSt+LZ1wuiz7ABxsGR?= =?us-ascii?Q?zBE3F1kqAGKaO1mbUa9cVE2sP+SJ/uh5bM4XXndOeBP0y7LgfARHIRwmi76F?= =?us-ascii?Q?JRHeCnLawKQSdDxLHne8vql1RfkfG22F1zZX+zdglQu6SyyediwbCNakNFmJ?= =?us-ascii?Q?WNXqMLa0VJJbVfLowv6jEpwi6ljPt+wEia5jKgwx+QubFQif0T9ZNIyr/uSe?= =?us-ascii?Q?o/Orw1LMI6cGckld7JEXcvzOhHzYlH9H5RJM4XqDtgkBfGSfr4PTJACn/3rq?= =?us-ascii?Q?8NKgnx3OB0cLy3RwJ8ymr9pfzKCZtwC48vw8pX6J5EZGQBMXo0w4dW0+2S2l?= =?us-ascii?Q?kbZgmC3PIxYQuUnPenmsOI2hyJ1xQZUYy3fvGd4wb89p49fqjcDSV0hrxcbM?= =?us-ascii?Q?2gsMKHrvhI2LwJjpXKJVaArcTyzaRSVnekrWjDJ5?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d99dce0b-e503-48f9-fb66-08dd916a6def X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2025 15:34:05.7004 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bGowpYf3uigRhmM+LdAGoqBgP843uPG6DNPzLKckgrjOhNoN7J4rc2t9H1ewKypFTW7zHGethX+2aNhlMRS3eQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5833 On Fri, May 09, 2025 at 04:08:21PM +0200, Borislav Petkov wrote: > On Thu, May 08, 2025 at 11:53:00AM -0400, Yazen Ghannam wrote: > > Let me flip it around. Why is this check needed at all? > > As I said above, some BIOS f*ckup. > > > Was there ever a real issue to resolve? > > Not that I remember... > > > It seems to me the deferred error updates are just following what other code > > did. > > Let's search the web for it: > > * https://bbs.archlinux.org/viewtopic.php?id=299379 > > - silly guests, who cares > > * https://gitlab.com/qemu-project/qemu/-/issues/2571 > > - another misguided qemu... > > Aha: > > https://lore.kernel.org/lkml/20241219124426.325747-1-pbonzini@redhat.com > > the usual virt silly stuff. > > > I figure the reason to have the platform give the offset to the OS is so > > the OS doesn't hard code it (in case it needs to change). These offsets > > were hard coded in the past (conflict between IBS/THR), and it caused > > problems when the offsets switched in the hardware. The registers that > > give the offsets were introduced soon after, I think. > > Right. > > > So the checks we do are defeating the purpose. The OS is still hard > > coding the offsets. The goal of this change is to follow the intent of > > the design. Sometimes we need to let go and trust [the BIOS]. ;) > > Look at you being silly :-P > > > Now we could update the checks to verify that an offset is not used for > > multiple interrupt sources. > > ... or, we won't do anything until someone in BIOS f*cks up again. > > > Let's follow up with the design folks to be sure. > > Yah, sounds like we will have to verify them after all. You can see how > universally widespread the trust in BIOS is... > > :-P > > In any case, whatever you do, when you axe off stuff, write in the commit > message why you do so. Silently removing it is making me want to know why it > is ok now. > Right, it sounds like we should take the values from the platform and just make sure they aren't used for multiple sources. In other words, we don't hard code the offsets, and we verify that each source has a unique offset. I agree we can leave this for now. So I'll drop this part from the patch. I think this topic can be a separate set, and it should cover all APIC LVT sources including IBS. I'll add it to the to-do list. :) Thanks, Yazen