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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?g7ZppcEd+fUxOTsEFOP+4aJXbIr694s4zk6QPsPcnj2hiV8+cVvSCnQgmsfe?= =?us-ascii?Q?Esjp5ylZVzhPrLYTqpCYTSUbIM73kHX5Fif0NlpmkcM3gAO6u4edyuh5DiGD?= =?us-ascii?Q?UgB4u05kZJCREVgx/YKDYTw1+z046/fnJjY5+Iqud5X/kAzvYnUtxrCvzW5j?= =?us-ascii?Q?B2YMzpydhoSSW9PYy6dvtqWlR/RNeAp+BiEaLOwJPXDELBA8g1F3tE+bld0w?= =?us-ascii?Q?X7fq113OSPWWLKZUHNfPkBp1m2WMNkPU1i+PwIeIpiPHLLIOtcQcE8qfS0xg?= =?us-ascii?Q?EvHlGippaTqRWku1DHRyKxe3waNzWfrENPgt6p8B5JbbBbt4yHOFAn8dJVZ2?= =?us-ascii?Q?+wZGtfkiNSgnln0m4mT17fXwIKYzEVdYw9/zIhse/Hp/kYKvrTsojyZ5ZDlP?= =?us-ascii?Q?ZzuRsyqQWtD66WSYskLzSfBNMQ+hygRKHNOgv5fTcwucFI1nc0WdVXNIVqWz?= =?us-ascii?Q?sWRh4hVIZKH36ClfNszKA5lXZH0UrbwHWc8W3xJD4jfKdvlOoGbj+w38KrYh?= =?us-ascii?Q?Lm7KFfyV0+t4dKdQ5YSLZ4e/okBizu6XokigJ17j5cLjZcBC5sRjZdXn6tTc?= =?us-ascii?Q?qIgNiFESqJsOdMgv+Q6tPJNqnmPJCPr3JnRJDKWTxal+2JT3hZNNvLcg4F3P?= =?us-ascii?Q?+FIH5EO8tocillXAFcgvIJ6OBU0RC2QvzblnWexc9fAfUKFymBHeSFf5SR8f?= =?us-ascii?Q?8J4c4YZNl7UT9yYqaEZEMr+k28sBQxFbh04Adt/T3DF51Cig63gG91RR+R6+?= =?us-ascii?Q?0p1rIolJvCA21n4QuezmCFuUuCGCwk3fsGnoBqntOF71U3yKw80HdYAUX9Qy?= =?us-ascii?Q?OiEVWMvZND7U/wMxrKyw4khhpW+5IrTBffvnBZ+yDsgV/t9kW0SfNcVwJ3By?= =?us-ascii?Q?Njb5agmxDUsGwotpevf4uNM/1AUefiWH0mZo2PW/bgkFy00QgnjLbjFjctXR?= =?us-ascii?Q?wOzUJezsWZpJO5eER+WJtqsryo8Ls9Yh3g3iY+hrQpCqGDxBpxuhjZ9zk2DW?= =?us-ascii?Q?K8cmrQVcCp/9GltzOmHpRaX3bwcril6xuQ52J8WW+Q2w6aDMh+sngxdsIvnc?= =?us-ascii?Q?Ofz9b0W4j5LwLKzi0lbCSvN94JJYbGaVq58zCrH+FheGUfHWzsYSlj9iZ5AJ?= =?us-ascii?Q?A0yGuqx+vaJKBy3tVzag5qeAD2PAZMqqSJuKneAvUoFSgtQ9BgHvnEJRekEs?= =?us-ascii?Q?fyO1k4M/30M+RHBWDBfgxRn+XJPm/tLKyJ+U0/MjlDkrac5FC0eXLl4E3jHH?= =?us-ascii?Q?k8m/h+ZYgRfcNE43x1mpWzrWhVfujY0iUViQJBNfBvD6ydrDCTkCTunx8HL5?= =?us-ascii?Q?GxMcPp12u7g0PsSdSuCZMfeA0ODSb0bcumXCnZaB+bzKLV3erfIVCshWgByW?= =?us-ascii?Q?vg0L0RC8jeEc5ytSAnFzdQVhgJ7lqa8RLz6K22/tG6MXAkWG/XrVMDdUxUx8?= =?us-ascii?Q?TMVkkcVN4DBeuKL5hO+tR3xTsARheHeICUKIUP6mrGB2recZ+sXEDLMH+9AL?= =?us-ascii?Q?SgQfJmdBljnkpQhDejdChE3FCLjwx2WvRPpY7Kz2BNNCMN0a1Y7CiPT9/JED?= =?us-ascii?Q?cBbfy5ONdhmNRVtAWXc/DJGnuuS54+cj7hKhmGGD?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 372b3fb2-ec2c-4456-7a43-08ddd4e819ae X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2025 12:52:28.8378 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mJfZXk5J8YLj+kBlTwB6e8Fx+vXwCstlya+4X0bCHzZcTeK0anQkfCiniPz3Ih3lQplb/tsEDf54REw2qpO8JQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF0D2C72F0D On Tue, Jul 29, 2025 at 08:46:57PM +0000, Avadhut Naik wrote: > Starting with Zen6, AMD's Scalable MCA systems will incorporate two new > bits in MCA_STATUS and MCA_CONFIG MSRs. These bits will indicate if a > valid System Physical Address (SPA) is present in MCA_ADDR. > > PhysAddrValidSupported bit (MCA_CONFIG[11]) serves as the architectural > indicator and states if PhysAddrV bit (MCA_STATUS[54]) is Reserved or > if it indicates validity of SPA in MCA_ADDR. > > PhysAddrV bit (MCA_STATUS[54]) advertises if MCA_ADDR contains valid > SPA or if it is implementation specific. The commit message is missing an imperative statement. You can describe how and why these bits are helpful. For example: "Use and prefer MCA_STATUS[PhysAddrV] when checking for a usable address." or something like this. > > Signed-off-by: Avadhut Naik > --- > arch/x86/include/asm/mce.h | 2 ++ > arch/x86/kernel/cpu/mce/amd.c | 16 +++++++++++++--- > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h > index 6c77c03139f7..387cf250525f 100644 > --- a/arch/x86/include/asm/mce.h > +++ b/arch/x86/include/asm/mce.h > @@ -48,6 +48,7 @@ > > /* AMD-specific bits */ > #define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */ > +#define MCI_STATUS_PADDRVAL BIT_ULL(54) /* Valid System Physical Address */ > #define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */ > #define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */ > #define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */ > @@ -62,6 +63,7 @@ > */ > #define MCI_CONFIG_MCAX 0x1 > #define MCI_CONFIG_FRUTEXT BIT_ULL(9) > +#define MCI_CONFIG_PAVALID BIT_ULL(11) > #define MCI_IPID_MCATYPE 0xFFFF0000 > #define MCI_IPID_HWID 0xFFF > > diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c > index 5c4eb28c3ac9..6ac222aec28d 100644 > --- a/arch/x86/kernel/cpu/mce/amd.c > +++ b/arch/x86/kernel/cpu/mce/amd.c > @@ -748,9 +748,9 @@ bool amd_mce_is_memory_error(struct mce *m) > } > > /* > - * AMD systems do not have an explicit indicator that the value in MCA_ADDR is > - * a system physical address. Therefore, individual cases need to be detected. > - * Future cases and checks will be added as needed. > + * Some AMD systems have an explicit indicator that the value in MCA_ADDR is a > + * system physical address. Individual cases though, need to be detected for > + * other systems. Future cases will be added as needed. > * > * 1) General case > * a) Assume address is not usable. > @@ -764,11 +764,21 @@ bool amd_mce_is_memory_error(struct mce *m) > * a) Reported in legacy bank 4 with extended error code (XEC) 8. > * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore, > * this bit should not be checked. > + * 4) MCI_STATUS_PADDRVAL is set > + * a)Will provide a valid system physical address. Space after "a)". > * > * NOTE: SMCA UMC memory errors fall into case #1. > */ > bool amd_mce_usable_address(struct mce *m) > { > + u64 smca_config; > + > + rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), smca_config); Newline here. > + if (smca_config & MCI_CONFIG_PAVALID) { > + if(m->status & MCI_STATUS_PADDRVAL) > + return true; > + return false; > + } Newline here. Also, the entire hunk above should go after the !SMCA case below and before the other SMCA cases. Furthermore, the hunk can be simplified to this: if (smca_config & MCI_CONFIG_PAVALID) return m->status & MCI_STATUS_PADDRVAL; Also also, the bit names are uncannily similar. I think they should be the same (except for the prefix) or clearly different. MCI_CONFIG_PADDRV/MCI_STATUS_PADDRV MCI_CONFIG_PHYS_ADDRV_SUPP/MCI_STATUS_PADDRVAL > /* Check special northbridge case 3) first. */ > if (!mce_flags.smca) { > if (legacy_mce_is_memory_error(m)) > > base-commit: d69139008b6dcd9c18483e956f61d187b0c214a2 > -- We should revisit saving MCA_CONFIG during logging. We end up reading it multiple times during error processing. I realize this came up before in a previous patch set. IIRC, the point of contention was exposing MCA_CONFIG to userspace. We don't necessarily have to do that. We can just use it in the kernel data structures. Thanks, Yazen