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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <x86@kernel.org>, Tony Luck <tony.luck@intel.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>,
	<Smita.KoralahalliChannabasappa@amd.com>,
	Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
	Nikolay Borisov <nik.borisov@suse.com>,
	<linux-acpi@vger.kernel.org>,
	"Yazen Ghannam" <yazen.ghannam@amd.com>
Subject: [PATCH v6 13/15] x86/mce/amd: Define threshold restart function for banks
Date: Mon, 8 Sep 2025 15:40:42 +0000	[thread overview]
Message-ID: <20250908-wip-mca-updates-v6-13-eef5d6c74b9c@amd.com> (raw)
In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com>

Prepare for CMCI storm support by moving the common bank/block
iterator code to a helper function.

Include a parameter to switch the interrupt enable. This will be used by
the CMCI storm handling function.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---

Notes:
    Link:
    https://lore.kernel.org/r/20250825-wip-mca-updates-v5-18-865768a2eef8@amd.com
    
    v5->v6:
    * No change.
    
    v4->v5:
    * No change.
    
    v3->v4:
    * New in v4.

 arch/x86/kernel/cpu/mce/amd.c | 37 +++++++++++++++++++------------------
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 9ca4079ff342..fbdb0cec5737 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -471,6 +471,24 @@ static void threshold_restart_block(void *_tr)
 	wrmsr(tr->b->address, lo, hi);
 }
 
+static void threshold_restart_bank(unsigned int bank, bool intr_en)
+{
+	struct threshold_bank **thr_banks = this_cpu_read(threshold_banks);
+	struct threshold_block *block, *tmp;
+	struct thresh_restart tr;
+
+	if (!thr_banks || !thr_banks[bank])
+		return;
+
+	memset(&tr, 0, sizeof(tr));
+
+	list_for_each_entry_safe(block, tmp, &thr_banks[bank]->miscj, miscj) {
+		tr.b = block;
+		tr.b->interrupt_enable = intr_en;
+		threshold_restart_block(&tr);
+	}
+}
+
 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 {
 	struct thresh_restart tr = {
@@ -814,24 +832,7 @@ static void amd_deferred_error_interrupt(void)
 
 static void amd_reset_thr_limit(unsigned int bank)
 {
-	struct threshold_bank **bp = this_cpu_read(threshold_banks);
-	struct threshold_block *block, *tmp;
-	struct thresh_restart tr;
-
-	/*
-	 * Validate that the threshold bank has been initialized already. The
-	 * handler is installed at boot time, but on a hotplug event the
-	 * interrupt might fire before the data has been initialized.
-	 */
-	if (!bp || !bp[bank])
-		return;
-
-	memset(&tr, 0, sizeof(tr));
-
-	list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj) {
-		tr.b = block;
-		threshold_restart_block(&tr);
-	}
+	threshold_restart_bank(bank, true);
 }
 
 /*

-- 
2.51.0


  parent reply	other threads:[~2025-09-08 15:41 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-08 15:40 [PATCH v6 00/15] AMD MCA interrupts rework Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 01/15] x86/mce: Set CR4.MCE last during init Yazen Ghannam
2025-09-10 11:43   ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 02/15] x86/mce: Define BSP-only init Yazen Ghannam
2025-09-10 11:47   ` Nikolay Borisov
2025-09-10 13:53     ` Yazen Ghannam
2025-09-10 14:28       ` Nikolay Borisov
2025-09-10 17:23     ` Luck, Tony
2025-09-08 15:40 ` [PATCH v6 03/15] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-09-10 11:48   ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 04/15] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-09-10 13:27   ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 05/15] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-09-10 13:29   ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 06/15] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-09-10 15:09   ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 07/15] x86/mce: Add clear_bank() helper Yazen Ghannam
2025-09-10 15:22   ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 08/15] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 09/15] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 10/15] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-09-11 10:22   ` Nikolay Borisov
2025-09-11 15:53     ` Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 11/15] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 12/15] x86/mce/amd: Remove redundant reset_block() Yazen Ghannam
2025-09-11 14:42   ` Nikolay Borisov
2025-09-11 16:11     ` Yazen Ghannam
2025-09-08 15:40 ` Yazen Ghannam [this message]
2025-09-11 14:49   ` [PATCH v6 13/15] x86/mce/amd: Define threshold restart function for banks Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 14/15] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 15/15] x86/mce: Save and use APEI corrected threshold limit Yazen Ghannam
2025-09-11 17:01   ` Nikolay Borisov
2025-09-15 17:33     ` Yazen Ghannam
2025-09-19 10:42       ` Nikolay Borisov
2025-09-22 13:58         ` Yazen Ghannam
2025-09-08 16:10 ` [PATCH v6 00/15] AMD MCA interrupts rework Luck, Tony
2025-09-09 13:36   ` Yazen Ghannam

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