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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ORtxnrtXa/I/3I3oy5z8of3AK32fBqEK4kCow43M5ntMRsWKnSKF5c4R+EA+?= =?us-ascii?Q?zBQceCfVL+51DX9iC0nWNPdz5HK5UO1v6NhqxLrEIa3lea9ACvSGCyLgYMkN?= =?us-ascii?Q?LY+KJC9pX30NaU7xJ7vUoryb9CALmsvGP6UgoN89yze/8nuEiqoPBx2xkFyr?= =?us-ascii?Q?+qMcyqqS++nUrCgfdJw1qkrhqNwc0NCEvA0Za6osAKs5GxiEnZ6ICvidVKBJ?= =?us-ascii?Q?PcDAp/BYgebxCdoJQPnPswrIT3kiHP46If/FbZ3mqEACNkHlDyxyi4eWquvO?= =?us-ascii?Q?ublES2/62TiyYaITyGGb4mJg0mRVROQxxnDI1wCaVg7OUzOjGCq+JDKONGUG?= =?us-ascii?Q?eK54Qkq0qsP0c52YjNLOrnKta8UntJKed3aA3sn2fAxPQDpyr0qiFSGJ7+kn?= =?us-ascii?Q?6/DI5eq0AXIf8ORCBVy4sZbVDCwUkN28DAFDYQ+wq1M/6OBMJpsgTkw1dL7N?= =?us-ascii?Q?yj1VsVKqHMFgrxTW7EPU3L9wQ8OCMiiHyFAgNkog5GcGWkqXh4is2u3zHT27?= =?us-ascii?Q?/eWjqBBV63OD48hSBHpeFBDuA6KLARONvw8qOhAXGQPfznt/tkHI/XkrhOou?= =?us-ascii?Q?wbYA2FQrJljemy5Zk4avMg4GaBCn+eNgdsFMu9lZfGYogVh97U8sUNs1u0K1?= =?us-ascii?Q?wkG5Xbr7od+bSpHamUjNeU+3BGR2RCX3cJ33GjuTHqRdA0+fQLmcsQETLcp8?= =?us-ascii?Q?4cmT0kFLOM8PSgmvubC2i4EtjR6Tkv6yxanlSn8jetwcQcLaeo6MMepF9vIp?= =?us-ascii?Q?B+phOQe+fqBuS7VkCKFpBaoFgqa531HknC4ZO1BzXysYbUbfho6++vPOiM6Y?= =?us-ascii?Q?qp9XcBBjb2cHB8ZItkQtwkIdt5BcZRayDrg/EzrHBnSOmE1H8/3439H6GUst?= =?us-ascii?Q?JMv3FM/KNUuQE5YgCFZiTwBFcM1quVehW9/cA/MPC6EnTlhnatREq52Erp03?= =?us-ascii?Q?KOl0jZUV/ctImJd2IVZTJiyYmwb0r0thjstKG4gjHzljvVX8w5E5uvi1AOgv?= =?us-ascii?Q?FlcnkVYcF5WnWVOwwMjJUOnH574HkgRVyNdNbtAcyz2Pj+MYs6k2zfQuhCCf?= =?us-ascii?Q?XEyJbZUGPlxsO/PBtjfQr8Rg+u5rJyZx5vJvqUjGuQlLrWUgDp7PAjdoYdwS?= =?us-ascii?Q?MH1kSxDe0PFgOYSeU5lcHXhRbQiMUqFaMAxz8UNbbLn+a9dEAK3cK/K8qGqw?= =?us-ascii?Q?wEAAR5SWN/FzLWhXANCoSWy9gbKJDUwCAsG4hFha1rbIdqXMEiGm0TBW/4Ak?= =?us-ascii?Q?OLlCpMcnSVlBiFpFQhpxYCd8zKTcIx9LPvaN8X22QNGwPr5Mh/wHooUt9EZW?= =?us-ascii?Q?nTtPnJWvr2OwIwrPrW/xUUrbBGo3czM6mnmbcgl10K/97YwMD3BxfRdItJ3U?= =?us-ascii?Q?q9tHSi/PYZjgYSUrYbaXyu1DiAnIiuDjLFNFFKdmUNwmAIdt9tTCVZn+YqB+?= =?us-ascii?Q?LfxMNBC20rDix6HJpwlHd2OkKmWmSZxCbWqHrcPGkpotc2wiZK7vGxZaDNQz?= =?us-ascii?Q?x1asWFBauLmjp+AR3vM5OhMvQaIV+AOwL0uHF1ZBhUsQV76QrcuZ+SmvelW/?= =?us-ascii?Q?XpoTFmZE2uq3sJxixz7GAhJfChaciADj9JNVh1qg?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: c50f7ee0-8c70-4789-3bec-08ddf07b7e58 X-MS-Exchange-CrossTenant-AuthSource: CY5PR12MB6369.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2025 15:05:34.9743 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nrmgBUbVxHoS/j/8K52Ztyhkon2uGycGMNVULV78hN0C3xgY9aGmtMuX1/OVTp0ki11AHxDvBXD1WjcXkEzC/A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7113 On Tue, Sep 09, 2025 at 06:53:11PM +0000, Avadhut Naik wrote: > Currently, the NUM_CONTROLLERS macro is only used to statically allocate > the csels array of struct chip_select in struct amd64_pvt. > > The size of this array, however, will never exceed the number of UMCs on > the SOC. Since, max_mcs variable in struct amd64_pvt already stores the > number of UMCs on the SOC, the macro can be removed and the static array > can be dynamically allocated instead. You should note that max_mcs and the csels array are also used in legacy systems with 'DCTs'. Those had a max of 2 controllers which we already set in per_family_init() as the global default. So the legacy systems are covered by this change too. Without noting this, it seems like that case may be overlooked. > > Signed-off-by: Avadhut Naik > --- > Changes in v3: > Patch introduced. > --- > drivers/edac/amd64_edac.c | 19 +++++++++++++------ > drivers/edac/amd64_edac.h | 5 ++--- > 2 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c > index 3989794e4f29..0fade110c3fb 100644 > --- a/drivers/edac/amd64_edac.c > +++ b/drivers/edac/amd64_edac.c > @@ -4000,30 +4000,34 @@ static int probe_one_instance(unsigned int nid) > if (ret < 0) > goto err_enable; > > + pvt->csels = kcalloc(pvt->max_mcs, sizeof(*pvt->csels), GFP_KERNEL); > + if (!pvt->csels) > + goto err_enable; > + You can move this allocation to the end of per_family_init(). That's where we determine 'max_mcs'. If you do so, then the 'goto' changes below are not needed. Another option is to put it in hw_info_get() like we do for UMCs. But that means adding the allocation to three different helper functions rather than just the one with per_family_init(). > ret = pvt->ops->hw_info_get(pvt); > if (ret < 0) > - goto err_enable; > + goto err_csels; > > ret = 0; > if (!instance_has_memory(pvt)) { > amd64_info("Node %d: No DIMMs detected.\n", nid); > - goto err_enable; > + goto err_csels; > } > > if (!pvt->ops->ecc_enabled(pvt)) { > ret = -ENODEV; > > if (!ecc_enable_override) > - goto err_enable; > + goto err_csels; > > if (boot_cpu_data.x86 >= 0x17) { > amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS."); > - goto err_enable; > + goto err_csels; > } else > amd64_warn("Forcing ECC on!\n"); > > if (!enable_ecc_error_reporting(s, nid, F3)) > - goto err_enable; > + goto err_csels; > } > > ret = init_one_instance(pvt); > @@ -4033,7 +4037,7 @@ static int probe_one_instance(unsigned int nid) > if (boot_cpu_data.x86 < 0x17) > restore_ecc_error_reporting(s, nid, F3); > > - goto err_enable; > + goto err_csels; > } > > amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); > @@ -4043,6 +4047,8 @@ static int probe_one_instance(unsigned int nid) > > return ret; > > +err_csels: > + kfree(pvt->csels); This can go in hw_info_put(). We have kfree(pvt->umc) there already. > err_enable: > hw_info_put(pvt); > kfree(pvt); > @@ -4077,6 +4083,7 @@ static void remove_one_instance(unsigned int nid) > /* Free the EDAC CORE resources */ > mci->pvt_info = NULL; > > + kfree(pvt->csels); > hw_info_put(pvt); > kfree(pvt); > edac_mc_free(mci); > diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h > index 56999ed3ae56..39d30255c767 100644 > --- a/drivers/edac/amd64_edac.h > +++ b/drivers/edac/amd64_edac.h > @@ -96,7 +96,6 @@ > /* Hardware limit on ChipSelect rows per MC and processors per system */ > #define NUM_CHIPSELECTS 8 > #define DRAM_RANGES 8 > -#define NUM_CONTROLLERS 12 > > #define ON true > #define OFF false > @@ -347,8 +346,8 @@ struct amd64_pvt { > u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ > u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ > > - /* one for each DCT/UMC */ > - struct chip_select csels[NUM_CONTROLLERS]; > + /* Allocate one for each DCT/UMC */ > + struct chip_select *csels; > > /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ > struct dram_range ranges[DRAM_RANGES]; > -- Thanks, Yazen