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From: Krzysztof Kozlowski <krzk@kernel.org>
To: niravkumarlaxmidas.rabara@altera.com
Cc: dinguyen@kernel.org, matthew.gerlach@altera.com, robh@kernel.org,
	 krzk+dt@kernel.org, conor+dt@kernel.org, bp@alien8.de,
	tony.luck@intel.com,  linux-edac@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/6] arm64: dts: agilex5: Add ECC manager and submodule nodes
Date: Wed, 29 Oct 2025 07:51:28 +0100	[thread overview]
Message-ID: <20251029-devout-wise-toad-8b36ed@kuoka> (raw)
In-Reply-To: <20251028092232.773991-3-niravkumarlaxmidas.rabara@altera.com>

On Tue, Oct 28, 2025 at 05:22:28PM +0800, niravkumarlaxmidas.rabara@altera.com wrote:
> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
> 
> Add the ECC manager (eccmgr) node and its associated ECC submodules to the
> Agilex5 SoCFPGA device tree. The eccmgr node serves as a logical parent to
> group various ECC hardware instances, including those for USB, Ethernet,
> OCRAM, IO96B memory controllers, Secure Device Manager (SDM) QSPI, and
> Configuration RAM (CRAM) Single Event Upset (SEU) subsystems.
> 
> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
> ---
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 98 +++++++++++++++++++
>  1 file changed, 98 insertions(+)

DTS cannot be the second patch. Organize your patchset correctly, see
submitting patches.


> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 04e99cd7e74b..5ea7a506d3d2 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -428,6 +428,104 @@ usb0: usb@10b00000 {
>  			status = "disabled";
>  		};
>  
> +		eccmgr {
> +			compatible = "altr,socfpga-a10-ecc-manager";
> +			altr,sysmgr-syscon = <&sysmgr>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "global_sbe", "global_dbe", "io96b0" , "io96b1",
> +					  "sdm_qspi_sbe", "sdm_qspi_dbe", "sdm_seu";
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			ranges;
> +
> +			ocram-ecc@108cc000 {
> +				compatible = "altr,socfpga-a10-ocram-ecc";
> +				reg = <0x108cc000 0x100>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, <33 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			usb0-ecc@108c4000 {
> +				compatible = "altr,socfpga-usb-ecc";
> +				reg = <0x108c4000 0x100>;
> +				altr,ecc-parent = <&usb0>;
> +				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, <34 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac0-rx-ecc@108c0000 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0000 0x100>;
> +				altr,ecc-parent = <&gmac0>;
> +				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac0-tx-ecc@108c0400 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0400 0x100>;
> +				altr,ecc-parent = <&gmac0>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, <37 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac1-rx-ecc@108c0800 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0800 0x100>;
> +				altr,ecc-parent = <&gmac1>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac1-tx-ecc@108c0c00 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c0c00 0x100>;
> +				altr,ecc-parent = <&gmac1>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <39 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac2-rx-ecc@108c1000 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c1000 0x100>;
> +				altr,ecc-parent = <&gmac2>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, <40 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			emac2-tx-ecc@108c1400 {
> +				compatible = "altr,socfpga-eth-mac-ecc";
> +				reg = <0x108c1400 0x100>;
> +				altr,ecc-parent = <&gmac2>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>, <41 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			io96b0-ecc@18400000 {
> +				compatible = "altr,socfpga-io96b0-ecc";
> +				reg = <0x18400000 0x1000>;

Could not express more: NAK. Completely pointless node with pointless
name.

Best regards,
Krzysztof


  reply	other threads:[~2025-10-29  6:51 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-28  9:22 [PATCH 0/6] Add EDAC support for Agilex5 SoCFPGA niravkumarlaxmidas.rabara
2025-10-28  9:22 ` [PATCH 1/6] dt-bindings: edac: altera: Document additional ECC instances niravkumarlaxmidas.rabara
2025-10-29  6:50   ` Krzysztof Kozlowski
2025-10-31  8:01     ` Niravkumar L Rabara
2025-10-28  9:22 ` [PATCH 2/6] arm64: dts: agilex5: Add ECC manager and submodule nodes niravkumarlaxmidas.rabara
2025-10-29  6:51   ` Krzysztof Kozlowski [this message]
2025-10-28  9:22 ` [PATCH 3/6] EDAC/altera: Add DBE interrupt handling for Agilex5 niravkumarlaxmidas.rabara
2025-10-28  9:22 ` [PATCH 4/6] EDAC/altera: Add IO96B ECC support for Agilex5 SoCFPGA niravkumarlaxmidas.rabara
2025-10-30 14:30   ` Borislav Petkov
2025-10-31 11:52     ` Niravkumar L Rabara
2025-11-02 19:25       ` Borislav Petkov
2025-11-04  3:46   ` kernel test robot
2025-10-28  9:22 ` [PATCH 5/6] EDAC/altera: Add support for CRAM SEU error handling on SoCFPGA niravkumarlaxmidas.rabara
2025-10-29  6:52   ` Krzysztof Kozlowski
2025-10-28  9:22 ` [PATCH 6/6] EDAC: altera: Add ECC support for SDM QSPI on Agilex5 niravkumarlaxmidas.rabara
2025-10-29  6:52   ` Krzysztof Kozlowski

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