[PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Yazen Ghannam]

Recognize new SMCA bank types and include their short names for sysfs
and long names for decoding.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/include/asm/mce.h    | 11 +++++++++++
 arch/x86/kernel/cpu/mce/amd.c | 21 +++++++++++++++++++++
 drivers/edac/mce_amd.c        | 10 ++++++++++
 3 files changed, 42 insertions(+)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2d98886de09a..6e1f10ca053f 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -370,13 +370,24 @@ enum smca_bank_types {
 	SMCA_NBIO,	/* Northbridge IO Unit */
 	SMCA_PCIE,	/* PCI Express Unit */
 	SMCA_PCIE_V2,
+	SMCA_MPRAS,	/* MP for RAS */
 	SMCA_XGMI_PCS,	/* xGMI PCS Unit */
+	SMCA_SSBDCI,	/* Die to Die Interconnect */
 	SMCA_NBIF,	/* NBIF Unit */
 	SMCA_SHUB,	/* System HUB Unit */
 	SMCA_SATA,	/* SATA Unit */
 	SMCA_USB,	/* USB Unit */
+	SMCA_MPDACC,	/* MP for Data Acceleration */
+	SMCA_MPM,	/* Microprocessor Manageability Core */
+	SMCA_MPASP,	/* AMD Secure Processor */
+	SMCA_MPASP_V2,
+	SMCA_MPART,	/* AMD Root of Trust Microprocessor */
+	SMCA_DACC_FE,	/* Data Acceleration Front-end */
+	SMCA_DACC_BE,	/* Data Acceleration Back-end */
 	SMCA_USR_DP,	/* Ultra Short Reach Data Plane Controller */
 	SMCA_USR_CP,	/* Ultra Short Reach Control Plane Controller */
+	SMCA_EDDR5CMN,	/* eDDR5 CMN */
+	SMCA_PCIE_PL,	/* PCIe Link */
 	SMCA_GMI_PCS,	/* GMI PCS Unit */
 	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
 	SMCA_WAFL_PHY,	/* WAFL PHY Unit */
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 3f1dda355307..662d86a6bda4 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -117,13 +117,23 @@ static const char * const smca_names[] = {
 	[SMCA_MPDMA]			= "mpdma",
 	[SMCA_NBIO]			= "nbio",
 	[SMCA_PCIE ... SMCA_PCIE_V2]	= "pcie",
+	[SMCA_MPRAS]			= "mpras",
 	[SMCA_XGMI_PCS]			= "xgmi_pcs",
+	[SMCA_SSBDCI]			= "ssbdci",
 	[SMCA_NBIF]			= "nbif",
 	[SMCA_SHUB]			= "shub",
 	[SMCA_SATA]			= "sata",
 	[SMCA_USB]			= "usb",
+	[SMCA_MPDACC]			= "mpdacc",
+	[SMCA_MPM]			= "mpm",
+	[SMCA_MPASP ... SMCA_MPASP_V2]	= "mpasp",
+	[SMCA_MPART]			= "mpart",
+	[SMCA_DACC_FE]			= "dacc_fe",
+	[SMCA_DACC_BE]			= "dacc_be",
 	[SMCA_USR_DP]			= "usr_dp",
 	[SMCA_USR_CP]			= "usr_cp",
+	[SMCA_EDDR5CMN]			= "eddr5_cmn",
+	[SMCA_PCIE_PL]			= "pcie_pl",
 	[SMCA_GMI_PCS]			= "gmi_pcs",
 	[SMCA_XGMI_PHY]			= "xgmi_phy",
 	[SMCA_WAFL_PHY]			= "wafl_phy",
@@ -204,13 +214,24 @@ static const struct smca_hwid smca_hwid_mcatypes[] = {
 	{ SMCA_PCIE,	 HWID_MCATYPE(0x46, 0x0)	},
 	{ SMCA_PCIE_V2,	 HWID_MCATYPE(0x46, 0x1)	},
 
+	{ SMCA_MPRAS,	 HWID_MCATYPE(0x12, 0x0)	},
 	{ SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0)	},
+	{ SMCA_SSBDCI,	 HWID_MCATYPE(0x5C, 0x0)	},
 	{ SMCA_NBIF,	 HWID_MCATYPE(0x6C, 0x0)	},
 	{ SMCA_SHUB,	 HWID_MCATYPE(0x80, 0x0)	},
 	{ SMCA_SATA,	 HWID_MCATYPE(0xA8, 0x0)	},
 	{ SMCA_USB,	 HWID_MCATYPE(0xAA, 0x0)	},
+	{ SMCA_MPDACC,	 HWID_MCATYPE(0xBE, 0x0)	},
+	{ SMCA_MPM,	 HWID_MCATYPE(0xF9, 0x0)	},
+	{ SMCA_MPASP,	 HWID_MCATYPE(0xFD, 0x0)	},
+	{ SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1)	},
+	{ SMCA_MPART,	 HWID_MCATYPE(0xFF, 0x2)	},
+	{ SMCA_DACC_FE,	 HWID_MCATYPE(0x157, 0x0)	},
+	{ SMCA_DACC_BE,	 HWID_MCATYPE(0x164, 0x0)	},
 	{ SMCA_USR_DP,	 HWID_MCATYPE(0x170, 0x0)	},
 	{ SMCA_USR_CP,	 HWID_MCATYPE(0x180, 0x0)	},
+	{ SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0)	},
+	{ SMCA_PCIE_PL,	 HWID_MCATYPE(0x1E1, 0x0)	},
 	{ SMCA_GMI_PCS,  HWID_MCATYPE(0x241, 0x0)	},
 	{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0)	},
 	{ SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0)	},
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index af3c12284a1e..43051aab72ba 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -710,11 +710,21 @@ static const char * const smca_long_names[] = {
 	[SMCA_MPDMA]			= "MPDMA Unit",
 	[SMCA_NBIO]			= "Northbridge IO Unit",
 	[SMCA_PCIE ... SMCA_PCIE_V2]	= "PCI Express Unit",
+	[SMCA_MPRAS]			= "MPRAS Unit",
 	[SMCA_XGMI_PCS]			= "Ext Global Memory Interconnect PCS Unit",
+	[SMCA_SSBDCI]			= "Die to Die Interconnect Unit",
 	[SMCA_NBIF]			= "NBIF Unit",
 	[SMCA_SHUB]			= "System Hub Unit",
 	[SMCA_SATA]			= "SATA Unit",
 	[SMCA_USB]			= "USB Unit",
+	[SMCA_MPDACC]			= "MPDACC Unit",
+	[SMCA_MPM]			= "MPM Unit",
+	[SMCA_MPASP ... SMCA_MPASP_V2]	= "MPASP Unit",
+	[SMCA_MPART]			= "MPART Unit",
+	[SMCA_DACC_FE]			= "DACC Front-end Unit",
+	[SMCA_DACC_BE]			= "DACC Back-end Unit",
+	[SMCA_EDDR5CMN]			= "eDDR5 CMN Unit",
+	[SMCA_PCIE_PL]			= "PCIe Link Unit",
 	[SMCA_GMI_PCS]			= "Global Memory Interconnect PCS Unit",
 	[SMCA_XGMI_PHY]			= "Ext Global Memory Interconnect PHY Unit",
 	[SMCA_WAFL_PHY]			= "WAFL PHY Unit",
-- 
2.52.0

Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Borislav Petkov]

On Mon, Feb 02, 2026 at 05:21:58PM +0000, Yazen Ghannam wrote:
> Recognize new SMCA bank types and include their short names for sysfs
> and long names for decoding.
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---
>  arch/x86/include/asm/mce.h    | 11 +++++++++++
>  arch/x86/kernel/cpu/mce/amd.c | 21 +++++++++++++++++++++
>  drivers/edac/mce_amd.c        | 10 ++++++++++
>  3 files changed, 42 insertions(+)
> 
> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> index 2d98886de09a..6e1f10ca053f 100644
> --- a/arch/x86/include/asm/mce.h
> +++ b/arch/x86/include/asm/mce.h
> @@ -370,13 +370,24 @@ enum smca_bank_types {
>  	SMCA_NBIO,	/* Northbridge IO Unit */
>  	SMCA_PCIE,	/* PCI Express Unit */
>  	SMCA_PCIE_V2,
> +	SMCA_MPRAS,	/* MP for RAS */
>  	SMCA_XGMI_PCS,	/* xGMI PCS Unit */
> +	SMCA_SSBDCI,	/* Die to Die Interconnect */
>  	SMCA_NBIF,	/* NBIF Unit */
>  	SMCA_SHUB,	/* System HUB Unit */
>  	SMCA_SATA,	/* SATA Unit */
>  	SMCA_USB,	/* USB Unit */
> +	SMCA_MPDACC,	/* MP for Data Acceleration */
> +	SMCA_MPM,	/* Microprocessor Manageability Core */
> +	SMCA_MPASP,	/* AMD Secure Processor */
> +	SMCA_MPASP_V2,
> +	SMCA_MPART,	/* AMD Root of Trust Microprocessor */
> +	SMCA_DACC_FE,	/* Data Acceleration Front-end */
> +	SMCA_DACC_BE,	/* Data Acceleration Back-end */
>  	SMCA_USR_DP,	/* Ultra Short Reach Data Plane Controller */
>  	SMCA_USR_CP,	/* Ultra Short Reach Control Plane Controller */
> +	SMCA_EDDR5CMN,	/* eDDR5 CMN */
> +	SMCA_PCIE_PL,	/* PCIe Link */
>  	SMCA_GMI_PCS,	/* GMI PCS Unit */
>  	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
>  	SMCA_WAFL_PHY,	/* WAFL PHY Unit */

That ordering looks rather random. Does it matter which enum number a bank
type is? If not, let's sort them alphabetically for easier reading...

In the remaining places too.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Yazen Ghannam]

On Sat, Feb 28, 2026 at 04:04:47PM +0100, Borislav Petkov wrote:
> On Mon, Feb 02, 2026 at 05:21:58PM +0000, Yazen Ghannam wrote:
> > Recognize new SMCA bank types and include their short names for sysfs
> > and long names for decoding.
> > 
> > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> > ---
> >  arch/x86/include/asm/mce.h    | 11 +++++++++++
> >  arch/x86/kernel/cpu/mce/amd.c | 21 +++++++++++++++++++++
> >  drivers/edac/mce_amd.c        | 10 ++++++++++
> >  3 files changed, 42 insertions(+)
> > 
> > diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> > index 2d98886de09a..6e1f10ca053f 100644
> > --- a/arch/x86/include/asm/mce.h
> > +++ b/arch/x86/include/asm/mce.h
> > @@ -370,13 +370,24 @@ enum smca_bank_types {
> >  	SMCA_NBIO,	/* Northbridge IO Unit */
> >  	SMCA_PCIE,	/* PCI Express Unit */
> >  	SMCA_PCIE_V2,
> > +	SMCA_MPRAS,	/* MP for RAS */
> >  	SMCA_XGMI_PCS,	/* xGMI PCS Unit */
> > +	SMCA_SSBDCI,	/* Die to Die Interconnect */
> >  	SMCA_NBIF,	/* NBIF Unit */
> >  	SMCA_SHUB,	/* System HUB Unit */
> >  	SMCA_SATA,	/* SATA Unit */
> >  	SMCA_USB,	/* USB Unit */
> > +	SMCA_MPDACC,	/* MP for Data Acceleration */
> > +	SMCA_MPM,	/* Microprocessor Manageability Core */
> > +	SMCA_MPASP,	/* AMD Secure Processor */
> > +	SMCA_MPASP_V2,
> > +	SMCA_MPART,	/* AMD Root of Trust Microprocessor */
> > +	SMCA_DACC_FE,	/* Data Acceleration Front-end */
> > +	SMCA_DACC_BE,	/* Data Acceleration Back-end */
> >  	SMCA_USR_DP,	/* Ultra Short Reach Data Plane Controller */
> >  	SMCA_USR_CP,	/* Ultra Short Reach Control Plane Controller */
> > +	SMCA_EDDR5CMN,	/* eDDR5 CMN */
> > +	SMCA_PCIE_PL,	/* PCIe Link */
> >  	SMCA_GMI_PCS,	/* GMI PCS Unit */
> >  	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
> >  	SMCA_WAFL_PHY,	/* WAFL PHY Unit */
> 
> That ordering looks rather random. Does it matter which enum number a bank
> type is? If not, let's sort them alphabetically for easier reading...
> 
> In the remaining places too.
> 

The ordering is based on the HWID_MCATYPE() tuple. The intent is to keep
those in numerical order for easy reference with documentation.

See: smca_hwid_mcatypes[]

Thanks,
Yazen

Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Borislav Petkov]

On Mon, Mar 02, 2026 at 09:22:55AM -0500, Yazen Ghannam wrote:
> The ordering is based on the HWID_MCATYPE() tuple. The intent is to keep
> those in numerical order for easy reference with documentation.
> 
> See: smca_hwid_mcatypes[]

Ok, what is determining *this* particular order?

First LS, then LS_V2, then IF, then L2_CACHE, then EX... all those start with
0xb0.

Then CS, PIE, etc start with 0x2e...

I guess I don't see yet what the sorting criterion here is...

Thx.

static const struct smca_hwid smca_hwid_mcatypes[] = {



 { SMCA_RESERVED, (((0x00) << 16) | (0x0)) },


 { SMCA_LS, (((0xB0) << 16) | (0x0)) },
 { SMCA_LS_V2, (((0xB0) << 16) | (0x10)) },
 { SMCA_IF, (((0xB0) << 16) | (0x1)) },
 { SMCA_L2_CACHE, (((0xB0) << 16) | (0x2)) },
 { SMCA_DE, (((0xB0) << 16) | (0x3)) },

 { SMCA_EX, (((0xB0) << 16) | (0x5)) },
 { SMCA_FP, (((0xB0) << 16) | (0x6)) },
 { SMCA_L3_CACHE, (((0xB0) << 16) | (0x7)) },


 { SMCA_CS, (((0x2E) << 16) | (0x0)) },
 { SMCA_PIE, (((0x2E) << 16) | (0x1)) },
 { SMCA_CS_V2, (((0x2E) << 16) | (0x2)) },
 { SMCA_MA_LLC, (((0x2E) << 16) | (0x4)) },


 { SMCA_UMC, (((0x96) << 16) | (0x0)) },
 { SMCA_UMC_V2, (((0x96) << 16) | (0x1)) },


 { SMCA_PB, (((0x05) << 16) | (0x0)) },


 { SMCA_PSP, (((0xFF) << 16) | (0x0)) },
 { SMCA_PSP_V2, (((0xFF) << 16) | (0x1)) },


 { SMCA_SMU, (((0x01) << 16) | (0x0)) },
 { SMCA_SMU_V2, (((0x01) << 16) | (0x1)) },


 { SMCA_MP5, (((0x01) << 16) | (0x2)) },


 { SMCA_MPDMA, (((0x01) << 16) | (0x3)) },


 { SMCA_NBIO, (((0x18) << 16) | (0x0)) },


 { SMCA_PCIE, (((0x46) << 16) | (0x0)) },
 { SMCA_PCIE_V2, (((0x46) << 16) | (0x1)) },

 { SMCA_XGMI_PCS, (((0x50) << 16) | (0x0)) },
 { SMCA_NBIF, (((0x6C) << 16) | (0x0)) },
 { SMCA_SHUB, (((0x80) << 16) | (0x0)) },
 { SMCA_SATA, (((0xA8) << 16) | (0x0)) },
 { SMCA_USB, (((0xAA) << 16) | (0x0)) },
 { SMCA_USR_DP, (((0x170) << 16) | (0x0)) },
 { SMCA_USR_CP, (((0x180) << 16) | (0x0)) },
 { SMCA_GMI_PCS, (((0x241) << 16) | (0x0)) },
 { SMCA_XGMI_PHY, (((0x259) << 16) | (0x0)) },
 { SMCA_WAFL_PHY, (((0x267) << 16) | (0x0)) },
 { SMCA_GMI_PHY, (((0x269) << 16) | (0x0)) },
};

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Yazen Ghannam]

On Tue, Mar 03, 2026 at 04:38:14PM +0100, Borislav Petkov wrote:
> On Mon, Mar 02, 2026 at 09:22:55AM -0500, Yazen Ghannam wrote:
> > The ordering is based on the HWID_MCATYPE() tuple. The intent is to keep
> > those in numerical order for easy reference with documentation.
> > 
> > See: smca_hwid_mcatypes[]
> 
> Ok, what is determining *this* particular order?
> 
> First LS, then LS_V2, then IF, then L2_CACHE, then EX... all those start with
> 0xb0.
> 
> Then CS, PIE, etc start with 0x2e...
> 
> I guess I don't see yet what the sorting criterion here is...
> 
> Thx.

Yes, you're right. IIRC, the original order was based on the first
documentation from Zen1.

Later on, we tried to keep new bank types ordered numerically, if they
didn't fit with an existing type. That's mostly the group at the end.

> 
> static const struct smca_hwid smca_hwid_mcatypes[] = {
> 
> 
> 
>  { SMCA_RESERVED, (((0x00) << 16) | (0x0)) },
> 
> 
>  { SMCA_LS, (((0xB0) << 16) | (0x0)) },
>  { SMCA_LS_V2, (((0xB0) << 16) | (0x10)) },
>  { SMCA_IF, (((0xB0) << 16) | (0x1)) },
>  { SMCA_L2_CACHE, (((0xB0) << 16) | (0x2)) },
>  { SMCA_DE, (((0xB0) << 16) | (0x3)) },
> 
>  { SMCA_EX, (((0xB0) << 16) | (0x5)) },
>  { SMCA_FP, (((0xB0) << 16) | (0x6)) },
>  { SMCA_L3_CACHE, (((0xB0) << 16) | (0x7)) },
> 
> 
>  { SMCA_CS, (((0x2E) << 16) | (0x0)) },
>  { SMCA_PIE, (((0x2E) << 16) | (0x1)) },
>  { SMCA_CS_V2, (((0x2E) << 16) | (0x2)) },
>  { SMCA_MA_LLC, (((0x2E) << 16) | (0x4)) },
> 
> 
>  { SMCA_UMC, (((0x96) << 16) | (0x0)) },
>  { SMCA_UMC_V2, (((0x96) << 16) | (0x1)) },
> 
> 
>  { SMCA_PB, (((0x05) << 16) | (0x0)) },
> 
> 
>  { SMCA_PSP, (((0xFF) << 16) | (0x0)) },
>  { SMCA_PSP_V2, (((0xFF) << 16) | (0x1)) },
> 
> 
>  { SMCA_SMU, (((0x01) << 16) | (0x0)) },
>  { SMCA_SMU_V2, (((0x01) << 16) | (0x1)) },
> 
> 
>  { SMCA_MP5, (((0x01) << 16) | (0x2)) },
> 
> 
>  { SMCA_MPDMA, (((0x01) << 16) | (0x3)) },
> 
> 
>  { SMCA_NBIO, (((0x18) << 16) | (0x0)) },
> 
> 
>  { SMCA_PCIE, (((0x46) << 16) | (0x0)) },
>  { SMCA_PCIE_V2, (((0x46) << 16) | (0x1)) },
> 
>  { SMCA_XGMI_PCS, (((0x50) << 16) | (0x0)) },
>  { SMCA_NBIF, (((0x6C) << 16) | (0x0)) },
>  { SMCA_SHUB, (((0x80) << 16) | (0x0)) },
>  { SMCA_SATA, (((0xA8) << 16) | (0x0)) },
>  { SMCA_USB, (((0xAA) << 16) | (0x0)) },
>  { SMCA_USR_DP, (((0x170) << 16) | (0x0)) },
>  { SMCA_USR_CP, (((0x180) << 16) | (0x0)) },
>  { SMCA_GMI_PCS, (((0x241) << 16) | (0x0)) },
>  { SMCA_XGMI_PHY, (((0x259) << 16) | (0x0)) },
>  { SMCA_WAFL_PHY, (((0x267) << 16) | (0x0)) },
>  { SMCA_GMI_PHY, (((0x269) << 16) | (0x0)) },
> };
> 

We can re-sort them. Still want to have them alphabetically?

I can re-sort in a pre-patch before adding the new ones.

Thanks,
Yazen

Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Borislav Petkov]

On Wed, Mar 04, 2026 at 10:04:02AM -0500, Yazen Ghannam wrote:
> We can re-sort them. Still want to have them alphabetically?

I'm not sure how yet - all I'm trying to say is that random order is kinda
suboptimal when having to look at the code.

Alphabetically probably sounds ok because you have 0xb0 ones, for example,
which belong to different banks which makes me think that the hwid in
HWID_MCATYPE(hwid, mcatype) is perhaps arbitrary and not very important. 

And perhaps we can work better with alphabetically sorted IP names...

Rite?

> I can re-sort in a pre-patch before adding the new ones.

Yeah, makes sense.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Yazen Ghannam]

On Wed, Mar 04, 2026 at 05:39:53PM +0100, Borislav Petkov wrote:
> On Wed, Mar 04, 2026 at 10:04:02AM -0500, Yazen Ghannam wrote:
> > We can re-sort them. Still want to have them alphabetically?
> 
> I'm not sure how yet - all I'm trying to say is that random order is kinda
> suboptimal when having to look at the code.
> 
> Alphabetically probably sounds ok because you have 0xb0 ones, for example,
> which belong to different banks which makes me think that the hwid in
> HWID_MCATYPE(hwid, mcatype) is perhaps arbitrary and not very important. 

The HWID and McaType are defined in the hardware. The name/enum is
arbitrary, and we use those for convenience.

Some of the HWID represent a group of IP, e.g. 0xb0 is (so far) used for
Core banks, 0x2e for Fabric, etc.

So far we haven't needed to use HWID on its own. Though I had a patch to
check for a "memory controller" type by HWID=0x96.

https://lore.kernel.org/all/20231118193248.1296798-6-yazen.ghannam@amd.com/

Though maybe you mean "sorting based on HWID/McaType" is not important?
I agree.

> 
> And perhaps we can work better with alphabetically sorted IP names...
> 
> Rite?
> 
> > I can re-sort in a pre-patch before adding the new ones.
> 
> Yeah, makes sense.
> 

Okay, I'll work on it.

Thanks,
Yazen

Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

[Borislav Petkov]

On Wed, Mar 04, 2026 at 01:02:20PM -0500, Yazen Ghannam wrote:
> Though maybe you mean "sorting based on HWID/McaType" is not important?
> I agree.

Yeah, we can sort by IP name and not care of the numeric groups.

> Okay, I'll work on it.

Thanks!

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

[PATCH] x86/MCE/AMD, EDAC/mce_amd: Add new SMCA bank types.

[Muralidhara M K]

Add the (HWID, MCATYPE) tuples and names for new
SMCA bank types.

Also, add their respective error descriptions to the MCE
decoding module edac_mce_amd.

Signed-off-by: Muralidhara M K <muralimk@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/include/asm/mce.h    |  5 +++
 arch/x86/kernel/cpu/mce/amd.c | 16 ++++++++
 drivers/edac/mce_amd.c        | 70 +++++++++++++++++++++++++++++++++++
 3 files changed, 91 insertions(+)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index ddfb3cad8dff..cf7f35fdf2c8 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -317,6 +317,7 @@ enum smca_bank_types {
 	SMCA_CS_V2,	/* Coherent Slave */
 	SMCA_PIE,	/* Power, Interrupts, etc. */
 	SMCA_UMC,	/* Unified Memory Controller */
+	SMCA_UMC_V2,	/* Unified Memory Controller */
 	SMCA_PB,	/* Parameter Block */
 	SMCA_PSP,	/* Platform Security Processor */
 	SMCA_PSP_V2,	/* Platform Security Processor */
@@ -325,6 +326,10 @@ enum smca_bank_types {
 	SMCA_MP5,	/* Microprocessor 5 Unit */
 	SMCA_NBIO,	/* Northbridge IO Unit */
 	SMCA_PCIE,	/* PCI Express Unit */
+	SMCA_PCIE_V2,	/* PCI Express Unit */
+	SMCA_XGMI_PCS,	/* xGMI PCS Unit */
+	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
+	SMCA_WAFL_PHY,	/* WAFL PHY Unit */
 	N_SMCA_BANK_TYPES
 };
 
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index e486f96b3cb3..055f3a0acf5e 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -90,6 +90,7 @@ static struct smca_bank_name smca_names[] = {
 	[SMCA_CS_V2]	= { "coherent_slave",	"Coherent Slave" },
 	[SMCA_PIE]	= { "pie",		"Power, Interrupts, etc." },
 	[SMCA_UMC]	= { "umc",		"Unified Memory Controller" },
+	[SMCA_UMC_V2]	= { "umc_v2",		"Unified Memory Controller" },
 	[SMCA_PB]	= { "param_block",	"Parameter Block" },
 	[SMCA_PSP]	= { "psp",		"Platform Security Processor" },
 	[SMCA_PSP_V2]	= { "psp",		"Platform Security Processor" },
@@ -98,6 +99,10 @@ static struct smca_bank_name smca_names[] = {
 	[SMCA_MP5]	= { "mp5",		"Microprocessor 5 Unit" },
 	[SMCA_NBIO]	= { "nbio",		"Northbridge IO Unit" },
 	[SMCA_PCIE]	= { "pcie",		"PCI Express Unit" },
+	[SMCA_PCIE_V2]	= { "pcie",		"PCI Express Unit" },
+	[SMCA_XGMI_PCS]	= { "xgmi_pcs",		"Ext Global Memory Interconnect PCS Unit" },
+	[SMCA_XGMI_PHY]	= { "xgmi_phy",		"Ext Global Memory Interconnect PHY Unit" },
+	[SMCA_WAFL_PHY]	= { "wafl_phy",		"WAFL PHY Unit" },
 };
 
 static const char *smca_get_name(enum smca_bank_types t)
@@ -155,6 +160,7 @@ static struct smca_hwid smca_hwid_mcatypes[] = {
 
 	/* Unified Memory Controller MCA type */
 	{ SMCA_UMC,	 HWID_MCATYPE(0x96, 0x0)	},
+	{ SMCA_UMC_V2,	 HWID_MCATYPE(0x96, 0x1)	},
 
 	/* Parameter Block MCA type */
 	{ SMCA_PB,	 HWID_MCATYPE(0x05, 0x0)	},
@@ -175,6 +181,16 @@ static struct smca_hwid smca_hwid_mcatypes[] = {
 
 	/* PCI Express Unit MCA type */
 	{ SMCA_PCIE,	 HWID_MCATYPE(0x46, 0x0)	},
+	{ SMCA_PCIE_V2,	 HWID_MCATYPE(0x46, 0x1)	},
+
+	/* xGMI PCS MCA type */
+	{ SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0)	},
+
+	/* xGMI PHY MCA type */
+	{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0)	},
+
+	/* WAFL PHY MCA type */
+	{ SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0)	},
 };
 
 struct smca_bank smca_banks[MAX_NR_BANKS];
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 5dd905a3f30c..5515fd9336b1 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -323,6 +323,21 @@ static const char * const smca_umc_mce_desc[] = {
 	"AES SRAM ECC error",
 };
 
+static const char * const smca_umc2_mce_desc[] = {
+	"DRAM ECC error",
+	"Data poison error",
+	"SDP parity error",
+	"Reserved",
+	"Address/Command parity error",
+	"Write data parity error",
+	"DCQ SRAM ECC error",
+	"Reserved",
+	"Read data parity error",
+	"Rdb SRAM ECC error",
+	"RdRsp SRAM ECC error",
+	"LM32 MP errors",
+};
+
 static const char * const smca_pb_mce_desc[] = {
 	"An ECC error in the Parameter Block RAM array",
 };
@@ -400,6 +415,56 @@ static const char * const smca_pcie_mce_desc[] = {
 	"CCIX Non-okay write response with data error",
 };
 
+static const char * const smca_pcie2_mce_desc[] = {
+	"SDP Parity Error logging",
+};
+
+static const char * const smca_xgmipcs_mce_desc[] = {
+	"DataLossErr",
+	"TrainingErr",
+	"FlowCtrlAckErr",
+	"RxFifoUnderflowErr",
+	"RxFifoOverflowErr",
+	"CRCErr",
+	"BERExceededErr",
+	"TxVcidDataErr",
+	"ReplayBufParityErr",
+	"DataParityErr",
+	"ReplayFifoOverflowErr",
+	"ReplayFIfoUnderflowErr",
+	"ElasticFifoOverflowErr",
+	"DeskewErr",
+	"FlowCtrlCRCErr",
+	"DataStartupLimitErr",
+	"FCInitTimeoutErr",
+	"RecoveryTimeoutErr",
+	"ReadySerialTimeoutErr",
+	"ReadySerialAttemptErr",
+	"RecoveryAttemptErr",
+	"RecoveryRelockAttemptErr",
+	"ReplayAttemptErr",
+	"SyncHdrErr",
+	"TxReplayTimeoutErr",
+	"RxReplayTimeoutErr",
+	"LinkSubTxTimeoutErr",
+	"LinkSubRxTimeoutErr",
+	"RxCMDPktErr",
+};
+
+static const char * const smca_xgmiphy_mce_desc[] = {
+	"RAM ECC Error",
+	"ARC instruction buffer parity error",
+	"ARC data buffer parity error",
+	"PHY APB error",
+};
+
+static const char * const smca_waflphy_mce_desc[] = {
+	"RAM ECC Error",
+	"ARC instruction buffer parity error",
+	"ARC data buffer parity error",
+	"PHY APB error",
+};
+
 struct smca_mce_desc {
 	const char * const *descs;
 	unsigned int num_descs;
@@ -418,6 +483,7 @@ static struct smca_mce_desc smca_mce_descs[] = {
 	[SMCA_CS_V2]	= { smca_cs2_mce_desc,	ARRAY_SIZE(smca_cs2_mce_desc)	},
 	[SMCA_PIE]	= { smca_pie_mce_desc,	ARRAY_SIZE(smca_pie_mce_desc)	},
 	[SMCA_UMC]	= { smca_umc_mce_desc,	ARRAY_SIZE(smca_umc_mce_desc)	},
+	[SMCA_UMC_V2]	= { smca_umc2_mce_desc,	ARRAY_SIZE(smca_umc2_mce_desc)	},
 	[SMCA_PB]	= { smca_pb_mce_desc,	ARRAY_SIZE(smca_pb_mce_desc)	},
 	[SMCA_PSP]	= { smca_psp_mce_desc,	ARRAY_SIZE(smca_psp_mce_desc)	},
 	[SMCA_PSP_V2]	= { smca_psp2_mce_desc,	ARRAY_SIZE(smca_psp2_mce_desc)	},
@@ -426,6 +492,10 @@ static struct smca_mce_desc smca_mce_descs[] = {
 	[SMCA_MP5]	= { smca_mp5_mce_desc,	ARRAY_SIZE(smca_mp5_mce_desc)	},
 	[SMCA_NBIO]	= { smca_nbio_mce_desc,	ARRAY_SIZE(smca_nbio_mce_desc)	},
 	[SMCA_PCIE]	= { smca_pcie_mce_desc,	ARRAY_SIZE(smca_pcie_mce_desc)	},
+	[SMCA_PCIE_V2]	= { smca_pcie2_mce_desc,   ARRAY_SIZE(smca_pcie2_mce_desc)	},
+	[SMCA_XGMI_PCS]	= { smca_xgmipcs_mce_desc, ARRAY_SIZE(smca_xgmipcs_mce_desc)	},
+	[SMCA_XGMI_PHY]	= { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc)	},
+	[SMCA_WAFL_PHY]	= { smca_waflphy_mce_desc, ARRAY_SIZE(smca_waflphy_mce_desc)	},
 };
 
 static bool f12h_mc0_mce(u16 ec, u8 xec)
-- 
2.26.2