Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types

Yazen Ghannam
2026-03-04T15:04:15Z

On Tue, Mar 03, 2026 at 04:38:14PM +0100, Borislav Petkov wrote:
> On Mon, Mar 02, 2026 at 09:22:55AM -0500, Yazen Ghannam wrote:
> > The ordering is based on the HWID_MCATYPE() tuple. The intent is to keep
> > those in numerical order for easy reference with documentation.
> >
> > See: smca_hwid_mcatypes[]
>
> Ok, what is determining *this* particular order?
>
> First LS, then LS_V2, then IF, then L2_CACHE, then EX... all those start with
> 0xb0.
>
> Then CS, PIE, etc start with 0x2e...
>
> I guess I don't see yet what the sorting criterion here is...
>
> Thx.

Yes, you're right. IIRC, the original order was based on the first
documentation from Zen1.

Later on, we tried to keep new bank types ordered numerically, if they
didn't fit with an existing type. That's mostly the group at the end.

>
> static const struct smca_hwid smca_hwid_mcatypes[] = {
>
>
>
> { SMCA_RESERVED, (((0x00) << 16) | (0x0)) },
>
>
> { SMCA_LS, (((0xB0) << 16) | (0x0)) },
> { SMCA_LS_V2, (((0xB0) << 16) | (0x10)) },
> { SMCA_IF, (((0xB0) << 16) | (0x1)) },
> { SMCA_L2_CACHE, (((0xB0) << 16) | (0x2)) },
> { SMCA_DE, (((0xB0) << 16) | (0x3)) },
>
> { SMCA_EX, (((0xB0) << 16) | (0x5)) },
> { SMCA_FP, (((0xB0) << 16) | (0x6)) },
> { SMCA_L3_CACHE, (((0xB0) << 16) | (0x7)) },
>
>
> { SMCA_CS, (((0x2E) << 16) | (0x0)) },
> { SMCA_PIE, (((0x2E) << 16) | (0x1)) },
> { SMCA_CS_V2, (((0x2E) << 16) | (0x2)) },
> { SMCA_MA_LLC, (((0x2E) << 16) | (0x4)) },
>
>
> { SMCA_UMC, (((0x96) << 16) | (0x0)) },
> { SMCA_UMC_V2, (((0x96) << 16) | (0x1)) },
>
>
> { SMCA_PB, (((0x05) << 16) | (0x0)) },
>
>
> { SMCA_PSP, (((0xFF) << 16) | (0x0)) },
> { SMCA_PSP_V2, (((0xFF) << 16) | (0x1)) },
>
>
> { SMCA_SMU, (((0x01) << 16) | (0x0)) },
> { SMCA_SMU_V2, (((0x01) << 16) | (0x1)) },
>
>
> { SMCA_MP5, (((0x01) << 16) | (0x2)) },
>
>
> { SMCA_MPDMA, (((0x01) << 16) | (0x3)) },
>
>
> { SMCA_NBIO, (((0x18) << 16) | (0x0)) },
>
>
> { SMCA_PCIE, (((0x46) << 16) | (0x0)) },
> { SMCA_PCIE_V2, (((0x46) << 16) | (0x1)) },
>
> { SMCA_XGMI_PCS, (((0x50) << 16) | (0x0)) },
> { SMCA_NBIF, (((0x6C) << 16) | (0x0)) },
> { SMCA_SHUB, (((0x80) << 16) | (0x0)) },
> { SMCA_SATA, (((0xA8) << 16) | (0x0)) },
> { SMCA_USB, (((0xAA) << 16) | (0x0)) },
> { SMCA_USR_DP, (((0x170) << 16) | (0x0)) },
> { SMCA_USR_CP, (((0x180) << 16) | (0x0)) },
> { SMCA_GMI_PCS, (((0x241) << 16) | (0x0)) },
> { SMCA_XGMI_PHY, (((0x259) << 16) | (0x0)) },
> { SMCA_WAFL_PHY, (((0x267) << 16) | (0x0)) },
> { SMCA_GMI_PHY, (((0x269) << 16) | (0x0)) },
> };
>

We can re-sort them. Still want to have them alphabetically?

I can re-sort in a pre-patch before adding the new ones.

Thanks,
Yazen