From: Aaron Tomlin <atomlin@atomlin.com>
To: tony.luck@intel.com, bp@alien8.de, tglx@kernel.org,
mingo@redhat.com, dave.hansen@linux.intel.com
Cc: x86@kernel.org, hpa@zytor.com, frederic@kernel.org,
marco.crivellari@suse.com, sean@ashe.io,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [RFC PATCH] x86/mce: Avoid arming periodic polling timer on isolated CPUs
Date: Tue, 1 Sep 2026 11:11:38 -0400 [thread overview]
Message-ID: <20260901151138.132950-1-atomlin@atomlin.com> (raw)
Latency-sensitive workloads rely on CPU isolation (i.e., configured via
nohz_full= or isolcpus=nohz) to guarantee deterministic execution
without interruption from background kernel activity.
On x86 platforms, the Machine Check Architecture (MCA) subsystem arms a
per-CPU, pinned standard timer (mce_timer) to periodically poll hardware
banks for "silent" corrected machine check errors. Because mce_timer is
pinned to the local CPU via TIMER_PINNED, the timer core cannot migrate
its expiration to a housekeeping CPU. Consequently, every check_interval
(defaulting to five minutes, or as frequently as every 10 ms during
error decay), a timer tick interrupts the isolated CPU to execute
mce_timer_fn() and machine_check_poll(), introducing unavoidable latency
jitter.
Presently, the only mechanisms available to suppress this timer (i.e.,
the mce=ignore_ce boot parameter or setting check_interval=0 via sysfs)
are system-wide globals. Setting these attributes disables polling
across the entire platform, needlessly blinding non-isolated
housekeeping CPUs from monitoring shared memory controllers and uncore
error telemetry.
Amend should_enable_timer() to query housekeeping_cpu() for
HK_TYPE_TIMER (HK_TYPE_KERNEL_NOISE). When a CPU is designated as
isolated, the timer is neither armed at CPU online nor re-armed upon
timer expiration. Housekeeping CPUs continue to run their polling timers
unaltered, preserving routine monitoring of shared package and memory
controller banks.
On isolated CPUs, critical synchronous exceptions (#MC) remain fully
functional for fatal and recoverable uncorrected errors, and CMCI
interrupts continue to deliver asynchronous notifications where
supported. When CPU isolation is not configured, static branch
optimisations ensure zero runtime overhead.
Signed-off-by: Aaron Tomlin <atomlin@atomlin.com>
---
arch/x86/kernel/cpu/mce/core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index ab469605fc89..fd047968ad17 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -25,6 +25,7 @@
#include <linux/delay.h>
#include <linux/ctype.h>
#include <linux/sched.h>
+#include <linux/sched/isolation.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#include <linux/slab.h>
@@ -1759,6 +1760,9 @@ void (*mc_poll_banks)(void) = mc_poll_banks_default;
static bool should_enable_timer(unsigned long iv)
{
+ if (!housekeeping_cpu(smp_processor_id(), HK_TYPE_TIMER))
+ return false;
+
return !mca_cfg.ignore_ce && iv;
}
--
2.55.0
next reply other threads:[~2026-09-01 15:11 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 15:11 Aaron Tomlin [this message]
2026-09-01 17:58 ` [RFC PATCH] x86/mce: Avoid arming periodic polling timer on isolated CPUs Luck, Tony
2026-09-02 0:34 ` Aaron Tomlin
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