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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-198a0d98660sm1757914c88.9.2026.10.23.17.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 17:04:09 -0700 (PDT) Date: Fri, 23 Oct 2026 17:04:05 -0700 From: Jonathan Cameron To: Mauro Carvalho Chehab Cc: Pierre Gondois , Tony Luck , Borislav Petkov , linux-kernel@vger.kernel.org, James Morse , Mark Brown , "Rafael J. Wysocki" , Len Brown , Mauro Carvalho Chehab , Shuai Xue , Maciej Wieczor-Retman , Pawel Chmielewski , Dave Jiang , "Fabio M. De Francesco" , Breno Leitao , Dan Williams , Terry Bowman , Ard Biesheuvel , Morduan Zang , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, acpica-devel@lists.linux.dev, Ashok Raj Subject: Re: [PATCH v2 0/6] CPER: Add Memory Error Section 2 support Message-ID: <20261023170405.000060b8@oss.qualcomm.com> In-Reply-To: <20261024003917.283b890d@foz.lan> References: <20261019203915.2019037-1-pierre.gondois@arm.com> <20261020101048.00000186@oss.qualcomm.com> <0817615d-5e96-4a3a-b39e-3e5d1b88e716@arm.com> <20261023142621.00007051@oss.qualcomm.com> <20261024003917.283b890d@foz.lan> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIzMDA5NCBTYWx0ZWRfXz6HRI5+qeDs8 hoVkngyjs+bLsbxCdzV6EW6MZz3LG+HvTgf9lVbBo1AEJUPJWPphbYDMjMfP1oX3gpDUz0TXaTk /escYk9jCypZ3W5vskA027KqfOjf9RKaAWbEB1umxas0CFNFPaAUcmpJ+FNcZ1G0I6UI2jSU3Tt vO7QZwgOQICtJFfoKiaUcnU/G1e1JncP3q9tSGKTQjUuNx3fGk4q2EklZIB2KBKSkpOTwg/+5Wg zKwZq1KO8UuFEIenu3XMSRitxvpCTO6rdeOzKkjaVF0JgJHOPzMddKuhKZ777upjZdlCfeJdP2I /cNeUEbfcfz1thSK1IFvVwkW6Vw2kNOE9MfjGe7IDNccytFdGPbljP5UySsr8+KYQ7YnTZMOmGV ebfXW8B1IZ4lENXRUNcwurt1bB2x2BGHuaJ0U9P+l7Krrc3jj/Bre5rawSn6qs8/M4WgpoDJHgt o22d/ROwBpYxwm+xDqw== X-Authority-Analysis: v=2.4 cv=JI+uIMKb c=1 sm=1 tr=0 ts=6adbf5fb cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=7CQSdrXTAAAA:8 a=x053eCT7BGEYFa6Myv8A:9 a=CjuIK1q_8ugA:10 a=vBUdepa8ALXHeOFLBtFW:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIzMDA5NCBTYWx0ZWRfX9wihae1GpUu6 E+mY99NFCip319plApnS2tGVRhrwyteGoycNkUQZz+hw6clNnvE43XJ7Z2iNiIZldbuZoAuMXip iZ1lFJJ2G/3lwoiQk91x36S//qq29H8= X-Proofpoint-ORIG-GUID: WRHCjiU7evGHOHea4wwqlXbvoAeIuOwA X-Proofpoint-GUID: WRHCjiU7evGHOHea4wwqlXbvoAeIuOwA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-23_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 spamscore=0 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610230094 On Sat, 24 Oct 2026 00:40:33 +0200 Mauro Carvalho Chehab wrote: > On Fri, 23 Oct 2026 14:26:21 -0700 > Jonathan Cameron wrote: > > > On Thu, 22 Oct 2026 09:07:25 +0200 > > Pierre Gondois wrote: > > > > > On 10/20/26 19:10, Jonathan Cameron wrote: > > > > On Mon, 19 Oct 2026 22:38:39 +0200 > > > > Pierre Gondois wrote: > > > > > > > >> The support is mostly duplicated from Memory Error Section handling. > > > >> Other than differences coming from the content of Memory Error > > > >> Section 1 and 2, differences in the support are: > > > >> > > > >> - v2 do not rely on a compact "struct cper_mem_err_compact" struct. > > > >> This structure was used to support older versions of the Memory > > > >> Error Section (1). This is not needed for the new structure. > > > >> > > > >> - The compact version is also used by the tracing framework. > > > >> To avoid relying and propagating a non-standard record format, > > > >> through trace event (cf. extlog_mem event) the new trace event > > > >> prints each field individually. > > > >> > > > >> The last patch of the serie was only build-tested due to the > > > >> absence of relevant hardware. apei_mce_report_mem_error() and > > > >> arch_apei_report_mem_error() implementations were also removed since > > > >> last version. > > > >> > > > >> It will also require a proper handling from the rasdaemon. Applying > > > >> this last patch without rasdaemon support will silent the reports of > > > >> Memory Error Section 2 error, cf. ras_userspace_consumers() check. > > > > Hi Pierre, > > > > > > > > I'd slow down a bit. We are mid merge window and convention is normally > > > > one version a week or so anyway. Better to gather up feedback from > > > > a number of folk and spin only one revision to cover it all. > > > > > > > Hello Jonathan, > > > > > > Ok sure, as the v1 was reviewed quickly I thought there was a chance > > > of having the serie accepted quickly aswell. I ll wait a bit more. > > > > > > Thanks for the review, > > > > > > Pierre > > > > > > > A general question that came up in a related thread with one of > > our RAS architects. How does firmware decide what to send? As far as > > I can tell firwmare has no way to know whether the OS understands the CPER > > Memory Section 2. > > > > So options that come to mind. > > 1. Firmware must send a CPER with both Memory Section and Memory Section 2. > > Please don't do this: this would require either Kernespace or userspace to > discard one of the reports, only if the other one is there, which can be > tricky. Could be done more easily at userspace, but only if some database > support is enabled, but, at least on rasdaemon, this is an optional module. Good. That confirms my view that is horrible. > > > 2. For whatever other reason a platform knows it doesn't work with old kernel > > so can assume support in kernel and hopefully userspace got updated too. > > > > 3. We propose some additional discoverability (quickly - code first) to ACPI > > so that it can be a negotiated contract between OS and firmware. > > Until the OS confirms it understands Memory Section 2, firmware has to send > > the older one (or risk the record not being understood). After that > > negotiation it can do what it likes - probably send the Memory Section 2 form. > > > > Option 1 and 2 are ugly at best. > > > > Obvious path to me for option 3 is an _OSC like the one for generic initiators > > that we discovered a need for whilst implementing that years ago. > > > > Anyhow have a better idea? The above doesn't solve the end to end problem as > > maybe userspace still has no idea what this new tracepoint is, but at least gets > > us past hop 1 (so through the kernel). > > > > If we conclude _OSC plan works I'll draft a code first proposal. > > > > Jonathan On another note, Pierre, any plans to actually enable a path to the tracepoints on arm64? Today they only emerge from acpi_extlog which is x86 only. We definitely want the richer data for PFA and obviously for userspace nice to share tracepoints with extlog. Jonathan > > Regards, > Mauro