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From: "Shenhar, Talel" <talel@amazon.com>
To: <krzysztof.kozlowski@linaro.org>, <bp@alien8.de>
Cc: <talel@amazon.com>, <talelshenhar@gmail.com>,
	<shellykz@amazon.com>, <linux-edac@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: RFC on drivers/memory vs drivers/edac memory mapping for DDR Controller
Date: Mon, 2 Jan 2023 14:17:24 +0200	[thread overview]
Message-ID: <2511c7aa-8ce6-a803-a1ea-6121df79c677@amazon.com> (raw)

Hi,

Want to consult on a topic that involve both drivers/memory and 
drivers/edac.

* We want to introduce driver that reads DDR controller RAS register and 
notify for ECC errors by using EDAC MC API found in drivers/edac.
* We also want to have a capability to dynamically change DDR refresh 
rate based on thermal values (best to be done in drivers/memory ?).

The pain point here is that both capabilities are controlled from the 
DDR controller.
This create issue while using 
devm_platform_ioremap_resource*->devm_request_mem_region which prevent 
two mapping of same area.

It seems to be expected problem as we have 2 "framework" (edac and 
memory) split while both aim for same HW unit.
What is the recommended way to face such conflicts?

We had several concept in mind but would love to get your point of view 
first.

Things we had in mind:
1) map more specific region to avoid conflict (we don't need the same 
registers on both entity so if we do very specific multiple mapping this 
shall be resolved)
2) use other kernel API for mapping that doesn't do request_mem_region 
(or use the reserve only for one of them)
3) have single driver (edac mc) handle also the refresh rate
4) export edac_mc.h and have the drivers/memory have all the needed code 
to do both edac and refresh rate under drivers/memory

Your recommendation shall be appreciated!

Thanks,
Talel.


             reply	other threads:[~2023-01-02 12:17 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-02 12:17 Shenhar, Talel [this message]
2023-01-02 12:47 ` RFC on drivers/memory vs drivers/edac memory mapping for DDR Controller Krzysztof Kozlowski
2023-01-02 13:44   ` Shenhar, Talel
2023-01-02 13:59     ` Krzysztof Kozlowski
2023-01-02 16:21       ` Shenhar, Talel
2023-01-02 16:25         ` Krzysztof Kozlowski
2023-01-03 13:12           ` Shenhar, Talel
2023-01-03 13:23             ` Krzysztof Kozlowski
2023-01-03 13:47               ` Shenhar, Talel
2023-01-03 14:02                 ` Krzysztof Kozlowski
2023-01-03 14:24                 ` Krzysztof Kozlowski
2023-01-03 14:34                   ` Shenhar, Talel
2023-01-02 13:43 ` Borislav Petkov
2023-01-02 16:14   ` Shenhar, Talel
2023-01-02 16:23     ` Borislav Petkov

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