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Mon, 23 Sep 2024 11:30:17 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from [10.32.65.165] (10.32.65.165) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 23 Sep 2024 11:23:03 +0800 Message-ID: <271465a0-7719-4cae-899a-dbf58a3d174a@zhaoxin.com> Date: Mon, 23 Sep 2024 11:23:00 +0800 Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin From: Tony W Wang-oc X-ASG-Orig-Subj: Re: [PATCH v3 3/3] x86/mce: Add CMCI storm switching support for Zhaoxin To: "Zhuo, Qiuxu" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "Luck, Tony" , "linux-kernel@vger.kernel.org" , "linux-edac@vger.kernel.org" CC: "CobeChen@zhaoxin.com" , "TimGuo@zhaoxin.com" , "LeoLiu-oc@zhaoxin.com" , "Lyle Li" References: <20240910092652.13354-1-TonyWWang-oc@zhaoxin.com> <20240918055436.15551-1-TonyWWang-oc@zhaoxin.com> <20240918055436.15551-4-TonyWWang-oc@zhaoxin.com> <7a80b9f5-9503-45fa-bbf4-d0dfa97688ff@zhaoxin.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 9/23/2024 11:30:15 AM X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1727062218 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Barracuda-BRTS-Status: 1 X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 2229 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.130834 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Resend this mail because I received the message: Undelivered Mail=20 Returned to Sender On 2024/9/20 20:09, Tony W Wang-oc wrote: >=20 >=20 > On 2024/9/20 19:44, Zhuo, Qiuxu wrote: >> >> >>> From: Tony W Wang-oc >>> [...] >>>>> --- a/arch/x86/kernel/cpu/mce/zhaoxin.c >>>>> +++ b/arch/x86/kernel/cpu/mce/zhaoxin.c >>>>> @@ -63,3 +63,21 @@ void mce_zhaoxin_feature_clear(struct cpuinfo_x86 >>>>> *c) { >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 intel_clear_lmce(); >>>>> =C2=A0=C2=A0 } >>>>> + >>>>> +void mce_zhaoxin_handle_storm(int bank, bool on) { >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 unsigned long flags; >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 u64 val; >>>>> + >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 raw_spin_lock_irqsave(&cmci_discover_lock, = flags); >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 if (on) { >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 val &=3D ~(MCI_CTL2_CMCI_EN | >>>>> MCI_CTL2_CMCI_THRESHOLD_MASK); >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 val |=3D CMCI_STORM_THRESHOLD; >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 } else { >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 val &=3D ~MCI_CTL2_CMCI_THRESHOLD_MASK; >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 val |=3D (MCI_CTL2_CMCI_EN | cmci_threshold[bank]); >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 } >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); >>>>> +=C2=A0=C2=A0=C2=A0=C2=A0 raw_spin_unlock_irqrestore(&cmci_discover_l= ock, flags); } >>>> >>>> Are there any reasons or comments why it needs to disable/enable the >>>> CMCI interrupt here during a CMCI storm on/off? If not, then reuse >>>> mce_intel_handle_storm() to avoid duplicating the code. >>>> >>> >>> As explained in another email. >>> The reason is actually mentioned in the cover letter: "because=20 >>> Zhaoxin's UCR >>> error is not reported through CMCI", and we want to disable CMCI=20 >>> interrupt >>> when CMCI storm happened. >> >> So, this is just you want to disable CMCI when a CMCI storm happens. >> This doesn't explain much to me. >> What's the problem if not disable CMCI when a CMCI storm happens? >> >=20 > In practice, we have encountered a lot of CE errors such as DRAM CE=20 > errors, so it feels safer to disable CMCI interrupt than to set a large=20 > threshold. At the same time, Zhaoxin's UCR is not reported through CMCI,= =20 > so we implemented like this. >=20 > Sincerely > TonyWWang-oc >=20