From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: yazen.ghannam@amd.com, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, tony.luck@intel.com,
x86@kernel.org, Avadhut.Naik@amd.com,
Smita.KoralahalliChannabasappa@amd.com,
amd-gfx@lists.freedesktop.org,
linux-trace-kernel@vger.kernel.org
Subject: Re: [PATCH 03/20] x86/mce: Use mce_setup() helpers for apei_smca_report_x86_error()
Date: Mon, 27 Nov 2023 09:53:17 -0500 [thread overview]
Message-ID: <27e09418-3201-4908-9ea7-13691f28c664@amd.com> (raw)
In-Reply-To: <20231122182805.GIZV5INdVuBOhbtjOm@fat_crate.local>
On 11/22/2023 1:28 PM, Borislav Petkov wrote:
> On Sat, Nov 18, 2023 at 01:32:31PM -0600, Yazen Ghannam wrote:
>> Current AMD systems may report MCA errors using the ACPI Boot Error
>> Record Table (BERT). The BERT entries for MCA errors will be an x86
>> Common Platform Error Record (CPER) with an MSR register context that
>> matches the MCAX/SMCA register space.
>>
>> However, the BERT will not necessarily be processed on the CPU that
>> reported the MCA errors. Therefore, the correct CPU number needs to be
>> determined and the information saved in struct mce.
>>
>> The CPU number is determined by searching all possible CPUs for a Local
>> APIC ID matching the value in the x86 CPER.
>
> Those below are explaining what the patch does. Not needed here.
>
Okay, will remove them.
>> Set up the MCA record after searching for a CPU number. If no possible
>> CPU was found, then return early.
>>
>> Gather the global MCA information first, save the found CPU number, then
>> gather the per-CPU information.
>
Thanks,
Yazen
next prev parent reply other threads:[~2023-11-27 14:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 19:32 [PATCH 00/20] MCA Updates Yazen Ghannam
2023-11-18 19:32 ` [PATCH 01/20] x86/mce/inject: Clear test status value Yazen Ghannam
2023-11-18 19:32 ` [PATCH 02/20] x86/mce: Define mce_setup() helpers for global and per-CPU fields Yazen Ghannam
2023-11-22 18:24 ` Borislav Petkov
2023-11-27 14:52 ` Yazen Ghannam
2023-11-18 19:32 ` [PATCH 03/20] x86/mce: Use mce_setup() helpers for apei_smca_report_x86_error() Yazen Ghannam
2023-11-22 18:28 ` Borislav Petkov
2023-11-27 14:53 ` Yazen Ghannam [this message]
2023-11-18 19:32 ` [PATCH 04/20] x86/mce/amd, EDAC/mce_amd: Move long names to decoder module Yazen Ghannam
2023-11-18 19:32 ` [PATCH 05/20] x86/mce/amd: Use helper for UMC bank type check Yazen Ghannam
2023-11-27 11:43 ` Borislav Petkov
2023-11-27 15:00 ` Yazen Ghannam
2023-11-18 19:32 ` [PATCH 06/20] x86/mce/amd: Use helper for GPU UMC bank type checks Yazen Ghannam
2023-11-27 11:46 ` Borislav Petkov
2023-11-27 15:12 ` Yazen Ghannam
2023-11-18 19:32 ` [PATCH 07/20] x86/mce/amd: Use fixed bank number for quirks Yazen Ghannam
2023-11-18 19:32 ` [PATCH 08/20] x86/mce/amd: Look up bank type by IPID Yazen Ghannam
2023-11-18 19:32 ` [PATCH 09/20] x86/mce/amd: Clean up SMCA configuration Yazen Ghannam
2023-11-18 19:32 ` [PATCH 10/20] x86/mce/amd: Prep DFR handler before enabling banks Yazen Ghannam
2023-11-18 19:32 ` [PATCH 11/20] x86/mce/amd: Simplify DFR handler setup Yazen Ghannam
2023-11-18 19:32 ` [PATCH 12/20] x86/mce/amd: Clean up enable_deferred_error_interrupt() Yazen Ghannam
2023-11-18 19:32 ` [PATCH 13/20] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2023-11-18 19:32 ` [PATCH 14/20] x86/mce/amd: Unify AMD DFR " Yazen Ghannam
2023-11-18 19:32 ` [PATCH 15/20] x86/mce: Skip AMD threshold init if no threshold banks found Yazen Ghannam
2023-11-18 19:32 ` [PATCH 16/20] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2023-11-18 19:32 ` [PATCH 17/20] x86/mce: Add wrapper for struct mce to export vendor specific info Yazen Ghannam
2023-11-18 19:32 ` [PATCH 18/20] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Yazen Ghannam
2023-11-18 19:32 ` [PATCH 19/20] x86/mce/apei: Handle variable register array size Yazen Ghannam
2023-11-18 19:32 ` [PATCH 20/20] EDAC/mce_amd: Add support for FRU Text in MCA Yazen Ghannam
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